gemini_start.S revision 1.2
1 /* $NetBSD: gemini_start.S,v 1.2 2008/11/09 08:39:31 cliff Exp $ */ 2 3 /* 4 * Machine dependant startup code for GEMINI boards. 5 * Based on omap_start.S 6 * 7 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 8 * Written by Hiroyuki Bessho for Genetec Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of Genetec Corporation may not be used to endorse or 19 * promote products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * Copyright (c) 2003 35 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Ichiro FUKUHARA. 49 * 4. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 55 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 57 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * Copyright (c) 2007 Microsoft 66 * All rights reserved. 67 * 68 * Redistribution and use in source and binary forms, with or without 69 * modification, are permitted provided that the following conditions 70 * are met: 71 * 1. Redistributions of source code must retain the above copyright 72 * notice, this list of conditions and the following disclaimer. 73 * 2. Redistributions in binary form must reproduce the above copyright 74 * notice, this list of conditions and the following disclaimer in the 75 * documentation and/or other materials provided with the distribution. 76 * 3. All advertising materials mentioning features or use of this software 77 * must display the following acknowledgement: 78 * This product includes software developed by Microsoft 79 * 80 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 81 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 82 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 83 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT, 84 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 85 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 87 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 88 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 89 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 90 * SUCH DAMAGE. 91 */ 92 93 #include "opt_gemini.h" 94 #include "opt_com.h" 95 #include "assym.h" 96 97 #include <machine/asm.h> 98 #include <arm/armreg.h> 99 #undef DOMAIN_CLIENT /* assym.h defines as 1, but pte.h defines as 0x01 */ 100 #include <arm/arm32/pmap.h> 101 #include <arm/gemini/gemini_reg.h> 102 #include <evbarm/gemini/gemini.h> 103 104 RCSID("$NetBSD: gemini_start.S,v 1.2 2008/11/09 08:39:31 cliff Exp $") 105 106 107 #ifdef VERBOSE_INIT_ARM 108 # define _PUTCHAR(addr, areg, breg, c) \ 109 ldr areg, addr; \ 110 1: \ 111 ldr breg, [ areg, #0x14 ]; /* LSR */ \ 112 tst breg, #0x20; /* TXRDY? */ \ 113 beq 1b; \ 114 mov breg, #(c); /* c */ \ 115 str breg, [ areg ]; /* TXDATA */ \ 116 2: \ 117 ldr breg, [ areg, #0x14 ]; /* LSR */ \ 118 tst breg, #0x40; /* TSRE? */ \ 119 beq 2b; 120 #else 121 # define _PUTCHAR(addr, areg, breg, c) 122 #endif 123 124 125 /* 126 * Kernel start routine for GEMINI Eval board. 127 * At this point, this code has been loaded into SDRAM 128 * and the MMU is off 129 */ 130 .section .start,"ax",%progbits 131 132 .global _C_LABEL(gemini_start) 133 _C_LABEL(gemini_start): 134 /* Move into supervisor mode and disable IRQs/FIQs. */ 135 mrs r0, cpsr 136 bic r0, r0, #PSR_MODE 137 orr r0, r0, #(I32_bit | F32_bit | PSR_SVC32_MODE) 138 msr cpsr, r0 139 140 _PUTCHAR(Lconsole_pbase, r4, r3, 'a') 141 142 /* 143 * Set up a preliminary mapping in the MMU to allow us to run 144 * at KERNEL_BASE with caches on. 145 */ 146 /* Build page table from scratch */ 147 ldr r0, Ltemp_l1_table 148 mov r1, r0 /* Save the page table address. */ 149 /* Zero the entire table so all virtual addresses are invalid. */ 150 mov r2, #L1_TABLE_SIZE /* in bytes */ 151 mov r3, #0 152 mov r4, r3 153 mov r5, r3 154 mov r6, r3 155 mov r7, r3 156 mov r8, r3 157 mov r10, r3 158 mov r11, r3 159 1: stmia r1!, {r3-r8,r10-r11} 160 stmia r1!, {r3-r8,r10-r11} 161 stmia r1!, {r3-r8,r10-r11} 162 stmia r1!, {r3-r8,r10-r11} 163 subs r2, r2, #(4 * 4 * 8) /* bytes per loop */ 164 bne 1b 165 166 _PUTCHAR(Lconsole_pbase, r4, r3, 'b') 167 168 /* Now create our entries per the mmu_init_table. */ 169 l1table .req r0 170 va .req r1 171 pa .req r2 172 n_sec .req r3 173 attr .req r4 174 itable .req r5 175 l1sfrm .req r6 176 ldr l1table, Ltemp_l1_table 177 adr itable, mmu_init_table 178 ldr l1sfrm, Ll1_s_frame 179 b 3f 180 2: str pa, [l1table, va] 181 add va, va, #4 182 add pa, pa, #(L1_S_SIZE) 183 adds n_sec, n_sec, #-1 184 bhi 2b 185 3: ldmia itable!, {va,pa,n_sec,attr} 186 /* Convert va to l1 offset: va = 4 * (va >> L1_S_SHIFT) */ 187 mov va, va, LSR #L1_S_SHIFT 188 mov va, va, LSL #2 189 /* Convert pa to l1 entry: pa = (pa & L1_S_FRAME) | attr */ 190 and pa, pa, l1sfrm 191 orr pa, pa, attr 192 cmp n_sec, #0 193 bne 2b 194 mov r5, r0 /* l1table */ 195 .unreq va 196 .unreq pa 197 .unreq n_sec 198 .unreq attr 199 .unreq itable 200 .unreq l1table 201 .unreq l1sfrm 202 203 _PUTCHAR(Lconsole_pbase, r4, r3, 'c') 204 205 /* 206 * using FA526 -specific cache ops here... 207 */ 208 mov r0, #0 209 mcr p15, 0, r0, c7, c5, 0 /* Invalidate Entire I cache */ 210 mcr p15, 0, r0, c7, c14, 0 /* Clean & Invalidate Entire D cache */ 211 212 ldr r2, Lctl_ID_dis /* Disable I+D caches */ 213 mrc p15, 0, r1, c1, c0, 0 /* " " " */ 214 and r1, r1, r2 /* " " " */ 215 mcr p15, 0, r1, c1, c0, 0 /* " " " */ 216 217 _PUTCHAR(Lconsole_pbase, r4, r3, 'd') 218 219 mcr p15, 0, r0, c7, c5, 6 /* invalidate BTB all */ 220 mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffers. */ 221 mcr p15, 0, r5, c2, c0, 0 /* Set Translation Table Base */ 222 mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ 223 224 /* Set the Domain Access register */ 225 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 226 mcr p15, 0, r0, c3, c0, 0 227 228 /* 229 * set Extension Control Enable in ECR, so we can use BTB 230 */ 231 ldr r0, Lecr_set 232 mcr p15, 0, r0, c1, c1, 0 233 234 /* 235 * Enable the MMU, etc. 236 */ 237 mrc p15, 0, r0, c1, c0, 0 238 ldr r1, Lcontrol_wax 239 and r0, r0, r1 240 ldr r1, Lcontrol_clr 241 mvn r1, r1 242 and r0, r0, r1 243 ldr r1, Lcontrol_set 244 orr r0, r0, r1 245 mcr p15, 0, r0, c1, c0, 0 246 247 /* 248 * Ensure that the coprocessor has finished turning on the MMU. 249 */ 250 mrc p15, 0, r0, c2, c0, 0 /* Read an arbitrary value. */ 251 mov r0, r0 /* Stall until read completes. */ 252 253 _PUTCHAR(Lconsole_vbase, r4, r3, 'e') 254 255 /* 256 * Zero .bss 257 */ 258 ldr r0, L_edata 259 ldr r1, L_end 260 mov r2, #0 261 1: 262 str r2, [r0], #0x04 /* *r0++ = r2 */ 263 cmp r0, r1 264 bne 1b 265 266 #if 0 267 /* 268 * Jump to start in locore.S, which in turn will call initarm and main. 269 */ 270 adr r0, Ltestjmp 271 ldr pc, [r0] 272 nop 273 nop 274 nop 275 nop 276 testjmp: 277 #endif 278 279 _PUTCHAR(Lconsole_vbase, r4, r3, 'f') 280 281 adr r0, Lstart 282 ldr pc, [r0] 283 nop 284 nop 285 nop 286 nop 287 288 /* NOTREACHED */ 289 290 L_edata: 291 .word _C_LABEL(_edata) 292 L_end: 293 .word _C_LABEL(_end) 294 295 #if 0 296 Ltestjmp: 297 .word testjmp 298 #endif 299 300 Lstart: 301 .word start 302 Ll1_s_frame: 303 .word L1_S_FRAME 304 Ltemp_l1_table: 305 /* Put the temporary L1 translation table at the end of SDRAM. */ 306 .word 0x10000000 + MEMSIZE * 0x100000 - L1_TABLE_SIZE 307 308 /* 309 * Coprocessor register initialization values 310 */ 311 #if !defined(CPU_ECR_ECE) 312 # define CPU_ECR_ECE 1 313 #endif 314 /* bits to set in the Extension Control Register */ 315 Lecr_set: 316 .word CPU_ECR_ECE 317 318 #if !defined(CPU_CONTROL_BTB_ENABLE) 319 # define CPU_CONTROL_BTB_ENABLE (1 << 11) 320 #endif 321 /* bits to set in the Control Register */ 322 /* bits 6..4 SB1 */ 323 Lcontrol_set: 324 .word CPU_CONTROL_MMU_ENABLE | \ 325 CPU_CONTROL_AFLT_ENABLE | \ 326 CPU_CONTROL_DC_ENABLE | \ 327 CPU_CONTROL_WBUF_ENABLE | \ 328 CPU_CONTROL_32BP_ENABLE | \ 329 CPU_CONTROL_32BD_ENABLE | \ 330 CPU_CONTROL_LABT_ENABLE | \ 331 CPU_CONTROL_SYST_ENABLE | \ 332 CPU_CONTROL_IC_ENABLE | \ 333 CPU_CONTROL_DC_ENABLE | \ 334 CPU_CONTROL_BTB_ENABLE 335 336 /* bits to clear in the Control Register */ 337 /* bits 31..14, 10, SBZ */ 338 Lcontrol_clr: 339 .word ((~0) << 14) | \ 340 (1 << 10) 341 342 /* bits to "write as existing" in the Control Register */ 343 Lcontrol_wax: 344 .word CPU_CONTROL_BEND_ENABLE 345 346 /* bits to disable the caches */ 347 Lctl_ID_dis: 348 .word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE) 349 350 /* console addressing */ 351 Lconsole_pbase: 352 .word CONSADDR 353 Lconsole_vbase: 354 .word GEMINI_CONSOLE_VBASE 355 356 357 /* We'll modify va and pa at run time so we can use relocatable addresses. */ 358 #define MMU_INIT(va,pa,n_sec,attr) \ 359 .word va ; \ 360 .word pa ; \ 361 .word n_sec ; \ 362 .word attr ; 363 364 mmu_init_table: 365 /* Maintain current 1:1 addressability */ 366 MMU_INIT(KERNEL_BASE_phys, KERNEL_BASE_phys, 367 (MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE, 368 L1_S_PROTO | L1_S_AP(AP_KRW) | L1_S_B | L1_S_C) 369 370 /* Map Kernel base VA:PA, write-back cacheable */ 371 MMU_INIT(KERNEL_BASE_virt, KERNEL_BASE_phys, 372 (MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE, 373 L1_S_PROTO | L1_S_AP(AP_KRW) | L1_S_B | L1_S_C) 374 375 /* Map console UART */ 376 MMU_INIT(GEMINI_CONSOLE_VBASE, CONSADDR, 377 1, 378 L1_S_PROTO | L1_S_AP(AP_KRW)) 379 380 /* end of table */ 381 MMU_INIT(0, 0, 0, 0) 382 383
Indexes created Mon Sep 29 18:09:42 GMT 2025