gumstix_machdep.c revision 1.62
1 /* $NetBSD: gumstix_machdep.c,v 1.62 2019/05/18 08:49:24 skrll Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2002, 2003, 2004, 2005 Genetec Corporation. 35 * All rights reserved. 36 * 37 * Written by Hiroyuki Bessho for Genetec Corporation. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. The name of Genetec Corporation may not be used to endorse or 48 * promote products derived from this software without specific prior 49 * written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 53 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 54 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 55 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 * 63 * Machine dependent functions for kernel setup for Genetec G4250EBX 64 * evaluation board. 65 * 66 * Based on iq80310_machhdep.c 67 */ 68 /* 69 * Copyright (c) 2001 Wasabi Systems, Inc. 70 * All rights reserved. 71 * 72 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 3. All advertising materials mentioning features or use of this software 83 * must display the following acknowledgement: 84 * This product includes software developed for the NetBSD Project by 85 * Wasabi Systems, Inc. 86 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 87 * or promote products derived from this software without specific prior 88 * written permission. 89 * 90 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 91 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 92 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 93 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 94 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 95 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 96 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 97 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 98 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 99 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 100 * POSSIBILITY OF SUCH DAMAGE. 101 */ 102 103 /* 104 * Copyright (c) 1997,1998 Mark Brinicombe. 105 * Copyright (c) 1997,1998 Causality Limited. 106 * All rights reserved. 107 * 108 * Redistribution and use in source and binary forms, with or without 109 * modification, are permitted provided that the following conditions 110 * are met: 111 * 1. Redistributions of source code must retain the above copyright 112 * notice, this list of conditions and the following disclaimer. 113 * 2. Redistributions in binary form must reproduce the above copyright 114 * notice, this list of conditions and the following disclaimer in the 115 * documentation and/or other materials provided with the distribution. 116 * 3. All advertising materials mentioning features or use of this software 117 * must display the following acknowledgement: 118 * This product includes software developed by Mark Brinicombe 119 * for the NetBSD Project. 120 * 4. The name of the company nor the name of the author may be used to 121 * endorse or promote products derived from this software without specific 122 * prior written permission. 123 * 124 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 125 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 126 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 127 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 128 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 129 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 130 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 131 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 132 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 133 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 134 * SUCH DAMAGE. 135 * 136 * Machine dependent functions for kernel setup for Intel IQ80310 evaluation 137 * boards using RedBoot firmware. 138 */ 139 140 #include "opt_arm_debug.h" 141 #include "opt_com.h" 142 #include "opt_console.h" 143 #include "opt_cputypes.h" 144 #include "opt_evbarm_boardtype.h" 145 #include "opt_gumstix.h" 146 #include "opt_kgdb.h" 147 #include "opt_multiprocessor.h" 148 #include "opt_pmap_debug.h" 149 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 150 #include "opt_omap.h" 151 152 #if defined(DUOVERO) 153 #include "arml2cc.h" 154 #endif 155 #include "prcm.h" 156 #endif 157 158 #include <sys/param.h> 159 #include <sys/conf.h> 160 #include <sys/device.h> 161 #include <sys/exec.h> 162 #include <sys/kernel.h> 163 #include <sys/proc.h> 164 #include <sys/reboot.h> 165 #include <sys/systm.h> 166 #include <sys/termios.h> 167 #include <sys/bus.h> 168 #include <sys/cpu.h> 169 #include <sys/gpio.h> 170 171 #include <prop/proplib.h> 172 173 #include <uvm/uvm_extern.h> 174 175 #include <arm/mainbus/mainbus.h> /* don't reorder */ 176 177 #include <machine/autoconf.h> /* don't reorder */ 178 #include <machine/bootconfig.h> 179 #include <arm/locore.h> 180 181 #include <arm/arm32/machdep.h> 182 183 #include <arm/omap/omap2_obiovar.h> 184 #include <arm/omap/am335x_prcm.h> 185 #include <arm/omap/omap2_gpio.h> 186 #include <arm/omap/omap2_gpmcreg.h> 187 #include <arm/omap/omap2_prcm.h> 188 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 189 #include <arm/omap/omap2_reg.h> /* Must required "opt_omap.h" */ 190 #endif 191 #include <arm/omap/omap3_sdmmcreg.h> 192 #include <arm/omap/omap_var.h> 193 #include <arm/omap/omap_com.h> 194 #include <arm/omap/tifbvar.h> 195 196 #include <arm/xscale/pxa2x0reg.h> 197 #include <arm/xscale/pxa2x0var.h> 198 #include <arm/xscale/pxa2x0_gpio.h> 199 #include <evbarm/gumstix/gumstixreg.h> 200 #include <evbarm/gumstix/gumstixvar.h> 201 202 #if defined(CPU_CORTEXA9) 203 #include <arm/cortex/pl310_var.h> 204 #include <arm/cortex/pl310_reg.h> 205 #include <arm/cortex/scu_reg.h> 206 207 #include <arm/cortex/a9tmr_var.h> 208 #endif 209 210 #if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) 211 #include <arm/cortex/gtmr_var.h> 212 #endif 213 214 #include <dev/cons.h> 215 216 #ifdef KGDB 217 #include <sys/kgdb.h> 218 #endif 219 220 #ifdef VERBOSE_INIT_ARM 221 #define VPRINTF(...) printf(__VA_ARGS__) 222 #else 223 #define VPRINTF(...) __nothing 224 #endif 225 226 /* 227 * The range 0xc1000000 - 0xfd000000 is available for kernel VM space 228 * Core-logic registers and I/O mappings occupy 229 * 230 * 0xfd000000 - 0xfd800000 on gumstix 231 * 0xc0000000 - 0xc0400000 on overo, duovero and pepper 232 */ 233 #ifndef KERNEL_VM_BASE 234 #define KERNEL_VM_BASE 0xc8000000 235 #endif 236 #define KERNEL_VM_SIZE 0x35000000 237 238 BootConfig bootconfig; /* Boot config storage */ 239 static char bootargs[MAX_BOOT_STRING]; 240 const size_t bootargs_len = sizeof(bootargs) - 1; /* without nul */ 241 char *boot_args = NULL; 242 243 uint32_t system_serial_high; 244 uint32_t system_serial_low; 245 246 /* Prototypes */ 247 #if defined(GUMSTIX) 248 static void read_system_serial(void); 249 #endif 250 #if defined(OMAP2) 251 static void omap_reset(void); 252 static void find_cpu_clock(void); 253 #endif 254 static void process_kernel_args(int, char *[]); 255 static void process_kernel_args_liner(char *); 256 #ifdef KGDB 257 static void kgdb_port_init(void); 258 #endif 259 static void gumstix_device_register(device_t, void *); 260 261 bs_protos(bs_notimpl); 262 263 #include "com.h" 264 #if NCOM > 0 265 #include <dev/ic/comreg.h> 266 #include <dev/ic/comvar.h> 267 #endif 268 269 #if defined(CPU_XSCALE) 270 #include "lcd.h" 271 #endif 272 273 #ifndef CONSPEED 274 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 275 #endif 276 #ifndef CONMODE 277 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 278 #endif 279 280 int comcnspeed = CONSPEED; 281 int comcnmode = CONMODE; 282 283 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 284 static char console[16]; 285 #endif 286 287 const struct tifb_panel_info *tifb_panel_info = NULL; 288 /* Use TPS65217 White LED Driver */ 289 bool use_tps65217_wled = false; 290 291 extern void gxio_config(void); 292 extern void gxio_config_expansion(char *); 293 294 295 static inline pd_entry_t * 296 read_ttb(void) 297 { 298 long ttb; 299 300 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); 301 302 return (pd_entry_t *)(ttb & ~((1<<14)-1)); 303 } 304 305 /* 306 * Static device mappings. These peripheral registers are mapped at 307 * fixed virtual addresses very early in initarm() so that we can use 308 * them while booting the kernel, and stay at the same address 309 * throughout whole kernel's life time. 310 * 311 * We use this table twice; once with bootstrap page table, and once 312 * with kernel's page table which we build up in initarm(). 313 * 314 * Since we map these registers into the bootstrap page table using 315 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 316 * registers segment-aligned and segment-rounded in order to avoid 317 * using the 2nd page tables. 318 */ 319 320 #define _A(a) ((a) & ~L1_S_OFFSET) 321 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 322 323 static const struct pmap_devmap gumstix_devmap[] = { 324 #if defined(GUMSTIX) 325 { 326 GUMSTIX_GPIO_VBASE, 327 _A(PXA2X0_GPIO_BASE), 328 _S(PXA250_GPIO_SIZE), 329 VM_PROT_READ | VM_PROT_WRITE, 330 PTE_NOCACHE, 331 }, 332 { 333 GUMSTIX_CLKMAN_VBASE, 334 _A(PXA2X0_CLKMAN_BASE), 335 _S(PXA2X0_CLKMAN_SIZE), 336 VM_PROT_READ | VM_PROT_WRITE, 337 PTE_NOCACHE, 338 }, 339 { 340 GUMSTIX_INTCTL_VBASE, 341 _A(PXA2X0_INTCTL_BASE), 342 _S(PXA2X0_INTCTL_SIZE), 343 VM_PROT_READ | VM_PROT_WRITE, 344 PTE_NOCACHE, 345 }, 346 { 347 GUMSTIX_FFUART_VBASE, 348 _A(PXA2X0_FFUART_BASE), 349 _S(4 * COM_NPORTS), 350 VM_PROT_READ | VM_PROT_WRITE, 351 PTE_NOCACHE, 352 }, 353 { 354 GUMSTIX_STUART_VBASE, 355 _A(PXA2X0_STUART_BASE), 356 _S(4 * COM_NPORTS), 357 VM_PROT_READ | VM_PROT_WRITE, 358 PTE_NOCACHE, 359 }, 360 { 361 GUMSTIX_BTUART_VBASE, 362 _A(PXA2X0_BTUART_BASE), 363 _S(4 * COM_NPORTS), 364 VM_PROT_READ | VM_PROT_WRITE, 365 PTE_NOCACHE, 366 }, 367 { 368 GUMSTIX_HWUART_VBASE, 369 _A(PXA2X0_HWUART_BASE), 370 _S(4 * COM_NPORTS), 371 VM_PROT_READ | VM_PROT_WRITE, 372 PTE_NOCACHE, 373 }, 374 { 375 GUMSTIX_LCDC_VBASE, 376 _A(PXA2X0_LCDC_BASE), 377 _S(4 * COM_NPORTS), 378 VM_PROT_READ | VM_PROT_WRITE, 379 PTE_NOCACHE, 380 }, 381 #elif defined(OVERO) 382 { /* SCM, PRCM */ 383 OVERO_L4_CORE_VBASE, 384 _A(OMAP3530_L4_CORE_BASE), 385 _S(L1_S_SIZE), /* No need 16MB. Use only first 1MB */ 386 VM_PROT_READ | VM_PROT_WRITE, 387 PTE_NOCACHE 388 }, 389 { /* Console, GPIO[2-6] */ 390 OVERO_L4_PERIPHERAL_VBASE, 391 _A(OMAP3530_L4_PERIPHERAL_BASE), 392 _S(OMAP3530_L4_PERIPHERAL_SIZE), 393 VM_PROT_READ | VM_PROT_WRITE, 394 PTE_NOCACHE 395 }, 396 { /* GPIO1 */ 397 OVERO_L4_WAKEUP_VBASE, 398 _A(OMAP3530_L4_WAKEUP_BASE), 399 _S(OMAP3530_L4_WAKEUP_SIZE), 400 VM_PROT_READ | VM_PROT_WRITE, 401 PTE_NOCACHE 402 }, 403 { 404 OVERO_GPMC_VBASE, 405 _A(GPMC_BASE), 406 _S(GPMC_SIZE), 407 VM_PROT_READ | VM_PROT_WRITE, 408 PTE_NOCACHE 409 }, 410 { 411 OVERO_SRDC_VBASE, 412 _A(OMAP3530_SDRC_BASE), 413 _S(OMAP3530_SDRC_SIZE), 414 VM_PROT_READ | VM_PROT_WRITE, 415 PTE_NOCACHE 416 }, 417 #elif defined(DUOVERO) 418 { 419 DUOVERO_L4_CM_VBASE, 420 _A(OMAP4430_L4_CORE_BASE + 0x100000), 421 _S(L1_S_SIZE), 422 VM_PROT_READ | VM_PROT_WRITE, 423 PTE_NOCACHE 424 }, 425 { /* Console, SCU, L2CC, GPIO[2-6] */ 426 DUOVERO_L4_PERIPHERAL_VBASE, 427 _A(OMAP4430_L4_PERIPHERAL_BASE), 428 _S(L1_S_SIZE * 3), 429 VM_PROT_READ | VM_PROT_WRITE, 430 PTE_NOCACHE 431 }, 432 { /* PRCM, GPIO1 */ 433 DUOVERO_L4_WAKEUP_VBASE, 434 _A(OMAP4430_L4_WAKEUP_BASE), 435 _S(OMAP4430_L4_WAKEUP_SIZE), 436 VM_PROT_READ | VM_PROT_WRITE, 437 PTE_NOCACHE 438 }, 439 { 440 DUOVERO_GPMC_VBASE, 441 _A(GPMC_BASE), 442 _S(GPMC_SIZE), 443 VM_PROT_READ | VM_PROT_WRITE, 444 PTE_NOCACHE 445 }, 446 { 447 DUOVERO_DMM_VBASE, 448 _A(OMAP4430_DMM_BASE), 449 _S(OMAP4430_DMM_SIZE), 450 VM_PROT_READ | VM_PROT_WRITE, 451 PTE_NOCACHE 452 }, 453 #elif defined(PEPPER) 454 { 455 /* CM, Control Module, GPIO0, Console */ 456 PEPPER_PRCM_VBASE, 457 _A(OMAP2_CM_BASE), 458 _S(L1_S_SIZE), 459 VM_PROT_READ | VM_PROT_WRITE, 460 PTE_NOCACHE 461 }, 462 { 463 /* GPIO[1-3] */ 464 PEPPER_L4_PERIPHERAL_VBASE, 465 _A(TI_AM335X_L4_PERIPHERAL_BASE), 466 _S(L1_S_SIZE), 467 VM_PROT_READ | VM_PROT_WRITE, 468 PTE_NOCACHE 469 }, 470 #endif 471 { 0, 0, 0, 0, 0 } 472 }; 473 474 #undef _A 475 #undef _S 476 477 #ifdef MULTIPROCESSOR 478 void gumstix_cpu_hatch(struct cpu_info *); 479 480 void 481 gumstix_cpu_hatch(struct cpu_info *ci) 482 { 483 #if defined(CPU_CORTEXA9) 484 a9tmr_init_cpu_clock(ci); 485 #elif defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) 486 gtmr_init_cpu_clock(ci); 487 #endif 488 } 489 #endif 490 491 492 static void 493 gumstix_mpstart(void) 494 { 495 #if defined(MULTIPROCESSOR) 496 const bus_space_tag_t iot = &omap_bs_tag; 497 int error; 498 499 #if defined(CPU_CORTEXA9) 500 bus_space_handle_t scu_ioh; 501 error = bus_space_map(iot, OMAP4_SCU_BASE, OMAP4_SCU_SIZE, 0, &scu_ioh); 502 if (error) 503 panic("Could't map OMAP4_SCU_BASE"); 504 505 /* 506 * Invalidate all SCU cache tags. That is, for all cores (0-3) 507 */ 508 bus_space_write_4(iot, scu_ioh, SCU_INV_ALL_REG, 0xffff); 509 510 uint32_t diagctl = bus_space_read_4(iot, scu_ioh, SCU_DIAG_CONTROL); 511 diagctl |= SCU_DIAG_DISABLE_MIGBIT; 512 bus_space_write_4(iot, scu_ioh, SCU_DIAG_CONTROL, diagctl); 513 514 uint32_t scu_ctl = bus_space_read_4(iot, scu_ioh, SCU_CTL); 515 scu_ctl |= SCU_CTL_SCU_ENA; 516 bus_space_write_4(iot, scu_ioh, SCU_CTL, scu_ctl); 517 518 armv7_dcache_wbinv_all(); 519 #endif 520 bus_space_handle_t wugen_ioh; 521 error = bus_space_map(iot, OMAP4_WUGEN_BASE, OMAP4_WUGEN_SIZE, 0, 522 &wugen_ioh); 523 if (error) 524 panic("Couldn't map OMAP4_WUGEN_BASE"); 525 const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart); 526 527 bus_space_write_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT1, mpstart); 528 529 for (size_t i = 1; i < arm_cpu_max; i++) { 530 uint32_t boot = bus_space_read_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT0); 531 boot |= __SHIFTIN(0xf, i * 4); 532 bus_space_write_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT0, boot); 533 } 534 535 arm_dsb(); 536 __asm __volatile("sev" ::: "memory"); 537 538 for (int loop = 0; loop < 16; loop++) { 539 VPRINTF("%u hatched %#x\n", loop, arm_cpu_hatched); 540 if (arm_cpu_hatched == __BITS(arm_cpu_max - 1, 1)) 541 break; 542 int timo = 1500000; 543 while (arm_cpu_hatched != __BITS(arm_cpu_max - 1, 1)) 544 if (--timo == 0) 545 break; 546 } 547 for (size_t i = 1; i < arm_cpu_max; i++) { 548 if ((arm_cpu_hatched & __BIT(i)) == 0) { 549 printf("%s: warning: cpu%zu failed to hatch\n", 550 __func__, i); 551 } 552 } 553 554 VPRINTF(" (%u cpu%s, hatched %#x)", 555 arm_cpu_max, arm_cpu_max ? "s" : "", 556 arm_cpu_hatched); 557 #endif 558 } 559 560 #if defined(CPU_CORTEX) 561 /* filled in before cleaning bss. keep in .data */ 562 u_int uboot_args[4] __attribute__((__section__(".data"))); 563 #else 564 extern uint32_t *uboot_args; 565 #endif 566 567 /* 568 * u_int initarm(...) 569 * 570 * Initial entry point on startup. This gets called before main() is 571 * entered. 572 * It should be responsible for setting up everything that must be 573 * in place when main is called. 574 * This includes 575 * Taking a copy of the boot configuration structure. 576 * Initialising the physical console so characters can be printed. 577 * Setting up page tables for the kernel 578 * Relocating the kernel to the bottom of physical memory 579 */ 580 u_int 581 initarm(void *arg) 582 { 583 extern char KERNEL_BASE_phys[]; 584 uint32_t ram_size = 0x400000; 585 enum { r0 = 0, r1 = 1, r2 = 2, r3 = 3 }; /* args from u-boot */ 586 587 #if defined(OVERO) || defined(DUOVERO) /* || defined(PEPPER) */ 588 const bus_space_tag_t iot = &omap_bs_tag; 589 #endif 590 591 #if defined(CPU_XSCALE) 592 593 /* 594 * We mapped PA == VA in gumstix_start.S. 595 * Also mapped SDRAM to KERNEL_BASE first 64Mbyte only with cachable. 596 * 597 * Gumstix (basix, connex, verdex, verdex-pro): 598 * Physical Address Range Description 599 * ----------------------- ---------------------------------- 600 * 0x00000000 - 0x00ffffff flash Memory (16MB or 4MB) 601 * 0x40000000 - 0x480fffff Processor Registers 602 * 0xa0000000 - 0xa3ffffff SDRAM Bank 0 (64MB or 128MB) 603 * 0xc0000000 - 0xc3ffffff KERNEL_BASE 604 */ 605 extern vaddr_t xscale_cache_clean_addr; 606 xscale_cache_clean_addr = 0xff000000U; 607 608 cpu_reset_address = NULL; 609 #elif defined(OMAP2) 610 cpu_reset_address = omap_reset; 611 612 find_cpu_clock(); 613 #endif 614 615 /* 616 * Heads up ... Setup the CPU / MMU / TLB functions 617 */ 618 if (set_cpufuncs()) 619 panic("cpu not recognized!"); 620 621 /* map some peripheral registers at static I/O area */ 622 pmap_devmap_bootstrap((vaddr_t)read_ttb(), gumstix_devmap); 623 624 #if defined(CPU_XSCALE) 625 /* start 32.768kHz OSC */ 626 ioreg_write(GUMSTIX_CLKMAN_VBASE + CLKMAN_OSCC, OSCC_OON); 627 628 /* Get ready for splfoo() */ 629 pxa2x0_intr_bootstrap(GUMSTIX_INTCTL_VBASE); 630 631 /* setup GPIO for {FF,ST,HW}UART. */ 632 pxa2x0_gpio_bootstrap(GUMSTIX_GPIO_VBASE); 633 634 pxa2x0_clkman_bootstrap(GUMSTIX_CLKMAN_VBASE); 635 #endif 636 637 638 #if defined(OVERO) 639 640 #define OMAP3530_SRDC_MCFG_p(p) (0x80 + ((p) * 0x30)) 641 #define OMAP3530_SRDC_MCFG_RAMSIZE __BITS(17,8) 642 643 bus_space_handle_t sdrcioh; 644 if (bus_space_map(iot, OMAP3530_SDRC_BASE, OMAP3530_SDRC_SIZE, 645 0, &sdrcioh) != 0) 646 panic("OMAP_SDRC_BASE map failed\n"); 647 648 ram_size = 0; 649 for (u_int p = 0; p < 2; p++) { 650 uint32_t mcfg = bus_space_read_4(iot, sdrcioh, 651 OMAP3530_SRDC_MCFG_p(p)); 652 ram_size += __SHIFTOUT(mcfg, OMAP3530_SRDC_MCFG_RAMSIZE) * 653 (2 * 1024 * 1024); 654 } 655 656 #elif defined(DUOVERO) 657 658 #define OMAP4_DMM_LISA_MAP_i(i) (0x40 + ((i) * 0x4)) 659 #define OMAP4_DMM_LISA_SYS_ADDR __BITS(31,24) 660 #define OMAP4_DMM_LISA_SYS_SIZE __BITS(22,20) 661 #define OMAP4_DMM_LISA_SDRC_ADDRSPC __BITS(17,16) 662 663 bus_space_handle_t dmmioh; 664 if (bus_space_map(iot, OMAP4430_DMM_BASE, OMAP4430_DMM_SIZE, 0, 665 &dmmioh) != 0) 666 panic("OMAP4_DMM_BASE map failed\n"); 667 668 ram_size = 0; 669 for (u_int i = 0; i < 4; i++) { 670 const uint32_t lisa = bus_space_read_4(iot, dmmioh, 671 OMAP4_DMM_LISA_MAP_i(i)); 672 673 const uint32_t sys_addr = 674 __SHIFTOUT(lisa, OMAP4_DMM_LISA_SYS_ADDR); 675 /* skip non-physical */ 676 if ((sys_addr & 0x80) != 0) 677 continue; 678 679 const uint32_t sdrc_addrspc = 680 __SHIFTOUT(lisa, OMAP4_DMM_LISA_SDRC_ADDRSPC); 681 /* Skip reserced areas */ 682 if (sdrc_addrspc == 2) 683 continue; 684 685 const uint32_t sys_size = 686 __SHIFTOUT(lisa, OMAP4_DMM_LISA_SYS_SIZE); 687 ram_size += (16 * 1024 * 1024) << sys_size; 688 } 689 690 691 #endif 692 693 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 694 695 /* configure MUX, GPIO and CLK. */ 696 gxio_config(); 697 698 #ifndef GUMSTIX_NETBSD_ARGS_CONSOLE 699 consinit(); 700 #endif 701 #ifdef KGDB 702 kgdb_port_init(); 703 #endif 704 705 /* 706 * Examine the boot args string for options we need to know about 707 * now. 708 */ 709 #if defined(GUMSTIX) 710 #define SDRAM_START 0xa0000000UL 711 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 712 #define SDRAM_START 0x80000000UL 713 #endif 714 if (uboot_args[r0] < SDRAM_START || 715 uboot_args[r0] >= SDRAM_START + ram_size) 716 /* Maybe r0 is 'argc'. We are booted by command 'go'. */ 717 process_kernel_args(uboot_args[r0], (char **)uboot_args[r1]); 718 else 719 /* 720 * Maybe r3 is 'boot args string' of 'bootm'. This string is 721 * linely. 722 */ 723 process_kernel_args_liner((char *)uboot_args[r3]); 724 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 725 consinit(); 726 #endif 727 728 /* Talk to the user */ 729 #define BDSTR(s) _BDSTR(s) 730 #define _BDSTR(s) #s 731 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 732 733 /* Read system serial */ 734 #if defined(GUMSTIX) 735 read_system_serial(); 736 #endif 737 738 VPRINTF("initarm: Configuring system ...\n"); 739 740 #if defined(OMAP_4430) 741 bus_space_handle_t ioh; 742 743 #if NARML2CC > 0 744 /* 745 * Initialize L2-Cache parameters 746 */ 747 748 if (bus_space_map(iot, OMAP4_L2CC_BASE, OMAP4_L2CC_SIZE, 0, &ioh) != 0) 749 panic("OMAP4_L2CC_BASE map failed\n"); 750 arml2cc_init(iot, ioh, 0); 751 #endif 752 753 #ifdef MULTIPROCESSOR 754 if (bus_space_map(iot, OMAP4_SCU_BASE, SCU_SIZE, 0, &ioh) != 0) 755 panic("OMAP4_SCU_BASE map failed\n"); 756 arm_cpu_max = 757 1 + (bus_space_read_4(iot, ioh, SCU_CFG) & SCU_CFG_CPUMAX); 758 #endif 759 #endif 760 761 /* Fake bootconfig structure for the benefit of pmap.c */ 762 /* XXX must make the memory description h/w independent */ 763 bootconfig.dramblocks = 1; 764 bootconfig.dram[0].address = SDRAM_START; 765 bootconfig.dram[0].pages = ram_size / PAGE_SIZE; 766 767 KASSERT(ram_size <= KERNEL_VM_BASE - KERNEL_BASE); 768 769 arm32_bootmem_init(bootconfig.dram[0].address, ram_size, 770 (uintptr_t) KERNEL_BASE_phys); 771 arm32_kernel_vm_init(KERNEL_VM_BASE, 772 #if defined(CPU_XSCALE) 773 ARM_VECTORS_LOW, 774 #elif defined(CPU_CORTEX) 775 ARM_VECTORS_HIGH, 776 #endif 777 0, gumstix_devmap, true); 778 779 evbarm_device_register = gumstix_device_register; 780 781 u_int sp = initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 782 783 /* 784 * initarm_common flushes cache if required before AP start 785 */ 786 gumstix_mpstart(); 787 788 return sp; 789 } 790 791 #if defined(GUMSTIX) 792 static void 793 read_system_serial(void) 794 { 795 #define GUMSTIX_SYSTEM_SERIAL_ADDR 0 796 #define GUMSTIX_SYSTEM_SERIAL_SIZE 8 797 #define FLASH_OFFSET_INTEL_PROTECTION 0x81 798 #define FLASH_OFFSET_USER_PROTECTION 0x85 799 #define FLASH_CMD_READ_ID 0x90 800 #define FLASH_CMD_RESET 0xff 801 int i; 802 char system_serial[GUMSTIX_SYSTEM_SERIAL_SIZE], *src; 803 char x; 804 805 src = (char *)(FLASH_OFFSET_USER_PROTECTION * 2 /*word*/); 806 *(volatile uint16_t *)0 = FLASH_CMD_READ_ID; 807 memcpy(system_serial, 808 src + GUMSTIX_SYSTEM_SERIAL_ADDR, sizeof (system_serial)); 809 *(volatile uint16_t *)0 = FLASH_CMD_RESET; 810 811 for (i = 1, x = system_serial[0]; i < sizeof (system_serial); i++) 812 x &= system_serial[i]; 813 if (x == 0xff) { 814 src = (char *)(FLASH_OFFSET_INTEL_PROTECTION * 2 /*word*/); 815 *(volatile uint16_t *)0 = FLASH_CMD_READ_ID; 816 memcpy(system_serial, 817 src + GUMSTIX_SYSTEM_SERIAL_ADDR, sizeof (system_serial)); 818 *(volatile uint16_t *)0 = FLASH_CMD_RESET; 819 820 /* 821 * XXXX: Don't need ??? 822 * gumstix_serial_hash(system_serial); 823 */ 824 } 825 system_serial_high = system_serial[0] << 24 | system_serial[1] << 16 | 826 system_serial[2] << 8 | system_serial[3]; 827 system_serial_low = system_serial[4] << 24 | system_serial[5] << 16 | 828 system_serial[6] << 8 | system_serial[7]; 829 830 printf("system serial: 0x"); 831 for (i = 0; i < sizeof (system_serial); i++) 832 printf("%02x", system_serial[i]); 833 printf("\n"); 834 } 835 #endif 836 837 #if defined(OMAP2) 838 static void 839 omap_reset(void) 840 { 841 842 #if defined(TI_AM335X) 843 vaddr_t prm_base = (PEPPER_PRCM_VBASE + AM335X_PRCM_PRM_DEVICE); 844 845 *(volatile uint32_t *)(prm_base + PRM_RSTCTRL) = RST_GLOBAL_WARM_SW; 846 #elif defined(OMAP_4430) 847 *(volatile uint32_t *)(DUOVERO_L4_WAKEUP_VBASE + OMAP4_PRM_RSTCTRL) = 848 OMAP4_PRM_RSTCTRL_WARM; 849 #endif 850 851 #if NPRCM > 0 852 prcm_cold_reset(); 853 #endif 854 } 855 856 static void 857 find_cpu_clock(void) 858 { 859 const vaddr_t prm_base __unused = OMAP2_PRM_BASE; 860 const vaddr_t cm_base = OMAP2_CM_BASE; 861 862 #if defined(OMAP_3530) 863 864 const uint32_t prm_clksel = 865 *(volatile uint32_t *)(prm_base + PLL_MOD + OMAP3_PRM_CLKSEL); 866 static const uint32_t prm_clksel_freqs[] = OMAP3_PRM_CLKSEL_FREQS; 867 const uint32_t sys_clk = 868 prm_clksel_freqs[__SHIFTOUT(prm_clksel, OMAP3_PRM_CLKSEL_CLKIN)]; 869 const uint32_t dpll1 = 870 *(volatile uint32_t *)(cm_base + OMAP3_CM_CLKSEL1_PLL_MPU); 871 const uint32_t dpll2 = 872 *(volatile uint32_t *)(cm_base + OMAP3_CM_CLKSEL2_PLL_MPU); 873 const uint32_t m = 874 __SHIFTOUT(dpll1, OMAP3_CM_CLKSEL1_PLL_MPU_DPLL_MULT); 875 const uint32_t n = __SHIFTOUT(dpll1, OMAP3_CM_CLKSEL1_PLL_MPU_DPLL_DIV); 876 const uint32_t m2 = 877 __SHIFTOUT(dpll2, OMAP3_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV); 878 879 /* 880 * MPU_CLK supplies ARM_FCLK which is twice the CPU frequency. 881 */ 882 curcpu()->ci_data.cpu_cc_freq = 883 ((sys_clk * m) / ((n + 1) * m2 * 2)) * OMAP3_PRM_CLKSEL_MULT; 884 omap_sys_clk = sys_clk * OMAP3_PRM_CLKSEL_MULT; 885 886 #elif defined(OMAP_4430) 887 888 const uint32_t prm_clksel = 889 *(volatile uint32_t *)(prm_base + OMAP4_CM_SYS_CLKSEL); 890 static const uint32_t cm_clksel_freqs[] = OMAP4_CM_CLKSEL_FREQS; 891 const uint32_t sys_clk = 892 cm_clksel_freqs[__SHIFTOUT(prm_clksel, OMAP4_CM_SYS_CLKSEL_CLKIN)]; 893 const uint32_t dpll1 = 894 *(volatile uint32_t *)(cm_base + OMAP4_CM_CLKSEL_DPLL_MPU); 895 const uint32_t dpll2 = 896 *(volatile uint32_t *)(cm_base + OMAP4_CM_DIV_M2_DPLL_MPU); 897 const uint32_t m = 898 __SHIFTOUT(dpll1, OMAP4_CM_CLKSEL_DPLL_MPU_DPLL_MULT); 899 const uint32_t n = __SHIFTOUT(dpll1, OMAP4_CM_CLKSEL_DPLL_MPU_DPLL_DIV); 900 const uint32_t m2 = 901 __SHIFTOUT(dpll2, OMAP4_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIV); 902 903 /* 904 * MPU_CLK supplies ARM_FCLK which is twice the CPU frequency. 905 */ 906 curcpu()->ci_data.cpu_cc_freq = 907 ((sys_clk * 2 * m) / ((n + 1) * m2)) * OMAP4_CM_CLKSEL_MULT / 2; 908 omap_sys_clk = sys_clk * OMAP4_CM_CLKSEL_MULT; 909 910 #elif defined(TI_AM335X) 911 912 prcm_bootstrap(cm_base); 913 am335x_sys_clk(TI_AM335X_CTLMOD_BASE); 914 am335x_cpu_clk(); 915 916 #endif 917 } 918 #endif 919 920 #ifdef GUMSTIX_NETBSD_ARGS_BUSHEADER 921 static const char busheader_name[] = "busheader="; 922 #endif 923 #if defined(GUMSTIX_NETBSD_ARGS_BUSHEADER) || \ 924 defined(GUMSTIX_NETBSD_ARGS_EXPANSION) 925 static const char expansion_name[] = "expansion="; 926 #endif 927 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 928 static const char console_name[] = "console="; 929 #endif 930 static void 931 process_kernel_args(int argc, char *argv[]) 932 { 933 int gxio_configured = 0, i, j; 934 935 boothowto = 0; 936 937 for (i = 1, j = 0; i < argc; i++) { 938 #ifdef GUMSTIX_NETBSD_ARGS_BUSHEADER 939 if (!strncmp(argv[i], busheader_name, strlen(busheader_name))) { 940 /* Configure for GPIOs of busheader side */ 941 gxio_config_expansion(argv[i] + strlen(busheader_name)); 942 gxio_configured = 1; 943 continue; 944 } 945 #endif 946 #if defined(GUMSTIX_NETBSD_ARGS_BUSHEADER) || \ 947 defined(GUMSTIX_NETBSD_ARGS_EXPANSION) 948 if (!strncmp(argv[i], expansion_name, strlen(expansion_name))) { 949 /* Configure expansion */ 950 gxio_config_expansion(argv[i] + strlen(expansion_name)); 951 gxio_configured = 1; 952 continue; 953 } 954 #endif 955 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 956 if (!strncmp(argv[i], console_name, strlen(console_name))) { 957 strncpy(console, argv[i] + strlen(console_name), 958 sizeof(console)); 959 consinit(); 960 } 961 #endif 962 if (j == bootargs_len) { 963 *(bootargs + j) = '\0'; 964 continue; 965 } 966 if (j != 0) 967 *(bootargs + j++) = ' '; 968 strncpy(bootargs + j, argv[i], bootargs_len - j); 969 bootargs[bootargs_len] = '\0'; 970 j += strlen(argv[i]); 971 } 972 boot_args = bootargs; 973 974 parse_mi_bootargs(boot_args); 975 976 if (!gxio_configured) 977 gxio_config_expansion(NULL); 978 } 979 980 static void 981 process_kernel_args_liner(char *args) 982 { 983 int i = 0; 984 char *p = NULL; 985 986 boothowto = 0; 987 988 strncpy(bootargs, args, sizeof(bootargs)); 989 #if defined(GUMSTIX_NETBSD_ARGS_BUSHEADER) || \ 990 defined(GUMSTIX_NETBSD_ARGS_EXPANSION) 991 { 992 char *q; 993 994 if ((p = strstr(bootargs, expansion_name))) 995 q = p + strlen(expansion_name); 996 #ifdef GUMSTIX_NETBSD_ARGS_BUSHEADER 997 else if ((p = strstr(bootargs, busheader_name))) 998 q = p + strlen(busheader_name); 999 #endif 1000 if (p) { 1001 char expansion[256], c; 1002 1003 i = 0; 1004 do { 1005 c = *(q + i); 1006 if (c == ' ') 1007 c = '\0'; 1008 expansion[i++] = c; 1009 } while (c != '\0' && i < sizeof(expansion)); 1010 gxio_config_expansion(expansion); 1011 strcpy(p, q + i); 1012 } 1013 } 1014 #endif 1015 if (p == NULL) 1016 gxio_config_expansion(NULL); 1017 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 1018 p = strstr(bootargs, console_name); 1019 if (p != NULL) { 1020 char c; 1021 1022 i = 0; 1023 do { 1024 c = *(p + strlen(console_name) + i); 1025 if (c == ' ') 1026 c = '\0'; 1027 console[i++] = c; 1028 } while (c != '\0' && i < sizeof(console)); 1029 consinit(); 1030 strcpy(p, p + strlen(console_name) + i); 1031 } 1032 #endif 1033 boot_args = bootargs; 1034 1035 parse_mi_bootargs(boot_args); 1036 } 1037 1038 #ifdef KGDB 1039 #ifndef KGDB_DEVNAME 1040 #define KGDB_DEVNAME "ffuart" 1041 #endif 1042 const char kgdb_devname[] = KGDB_DEVNAME; 1043 1044 #ifndef KGDB_DEVRATE 1045 #define KGDB_DEVRATE CONSPEED 1046 #endif 1047 int kgdb_devrate = KGDB_DEVRATE; 1048 1049 #if (NCOM > 0) 1050 #ifndef KGDB_DEVMODE 1051 #define KGDB_DEVMODE CONMODE 1052 #endif 1053 int comkgdbmode = KGDB_DEVMODE; 1054 #endif /* NCOM */ 1055 1056 #endif /* KGDB */ 1057 1058 1059 void 1060 consinit(void) 1061 { 1062 static int consinit_called = 0; 1063 1064 if (consinit_called != 0) 1065 return; 1066 1067 consinit_called = 1; 1068 1069 #if NCOM > 0 1070 1071 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 1072 /* Maybe passed Linux's bootargs 'console=ttyS?,<speed>...' */ 1073 if (strncmp(console, "ttyS", 4) == 0 && console[5] == ',') { 1074 int i; 1075 1076 comcnspeed = 0; 1077 for (i = 6; i < strlen(console) && isdigit(console[i]); i++) 1078 comcnspeed = comcnspeed * 10 + (console[i] - '0'); 1079 } 1080 #endif 1081 1082 #if defined(GUMSTIX) 1083 1084 #ifdef FFUARTCONSOLE 1085 #ifdef KGDB 1086 if (strcmp(kgdb_devname, "ffuart") == 0){ 1087 /* port is reserved for kgdb */ 1088 } else 1089 #endif 1090 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1091 if (console[0] == '\0' || strcasecmp(console, "ffuart") == 0 || 1092 strncmp(console, "ttyS0,", 6) == 0) 1093 #endif 1094 { 1095 int rv; 1096 1097 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_FFUART_BASE, 1098 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1099 if (rv == 0) { 1100 pxa2x0_clkman_config(CKEN_FFUART, 1); 1101 return; 1102 } 1103 } 1104 #endif /* FFUARTCONSOLE */ 1105 1106 #ifdef STUARTCONSOLE 1107 #ifdef KGDB 1108 if (strcmp(kgdb_devname, "stuart") == 0) { 1109 /* port is reserved for kgdb */ 1110 } else 1111 #endif 1112 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1113 if (console[0] == '\0' || strcasecmp(console, "stuart") == 0) 1114 #endif 1115 { 1116 int rv; 1117 1118 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_STUART_BASE, 1119 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1120 if (rv == 0) { 1121 pxa2x0_clkman_config(CKEN_STUART, 1); 1122 return; 1123 } 1124 } 1125 #endif /* STUARTCONSOLE */ 1126 1127 #ifdef BTUARTCONSOLE 1128 #ifdef KGDB 1129 if (strcmp(kgdb_devname, "btuart") == 0) { 1130 /* port is reserved for kgdb */ 1131 } else 1132 #endif 1133 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1134 if (console[0] == '\0' || strcasecmp(console, "btuart") == 0) 1135 #endif 1136 { 1137 int rv; 1138 1139 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_BTUART_BASE, 1140 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1141 if (rv == 0) { 1142 pxa2x0_clkman_config(CKEN_BTUART, 1); 1143 return; 1144 } 1145 } 1146 #endif /* BTUARTCONSOLE */ 1147 1148 #ifdef HWUARTCONSOLE 1149 #ifdef KGDB 1150 if (strcmp(kgdb_devname, "hwuart") == 0) { 1151 /* port is reserved for kgdb */ 1152 } else 1153 #endif 1154 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1155 if (console[0] == '\0' || strcasecmp(console, "hwuart") == 0) 1156 #endif 1157 { 1158 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_HWUART_BASE, 1159 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1160 if (rv == 0) { 1161 pxa2x0_clkman_config(CKEN_HWUART, 1); 1162 return; 1163 } 1164 } 1165 #endif /* HWUARTCONSOLE */ 1166 1167 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1168 1169 if (comcnattach(&omap_a4x_bs_tag, CONSADDR, comcnspeed, 1170 OMAP_COM_FREQ, COM_TYPE_NORMAL, comcnmode) == 0) 1171 return; 1172 1173 #endif /* GUMSTIX or OVERO */ 1174 1175 #endif /* NCOM */ 1176 1177 #if NLCD > 0 1178 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1179 if (console[0] == '\0' || strcasecmp(console, "lcd") == 0) 1180 #endif 1181 { 1182 gxlcd_cnattach(); 1183 } 1184 #endif 1185 } 1186 1187 #ifdef KGDB 1188 static void 1189 kgdb_port_init(void) 1190 { 1191 #if (NCOM > 0) && defined(COM_PXA2X0) 1192 paddr_t paddr = 0; 1193 int cken = 0; 1194 1195 if (0 == strcmp(kgdb_devname, "ffuart")) { 1196 paddr = PXA2X0_FFUART_BASE; 1197 cken = CKEN_FFUART; 1198 } else if (0 == strcmp(kgdb_devname, "stuart")) { 1199 paddr = PXA2X0_STUART_BASE; 1200 cken = CKEN_STUART; 1201 } else if (0 == strcmp(kgdb_devname, "btuart")) { 1202 paddr = PXA2X0_BTUART_BASE; 1203 cken = CKEN_BTUART; 1204 } else if (0 == strcmp(kgdb_devname, "hwuart")) { 1205 paddr = PXA2X0_HWUART_BASE; 1206 cken = CKEN_HWUART; 1207 } 1208 1209 if (paddr && 1210 0 == com_kgdb_attach(&pxa2x0_a4x_bs_tag, paddr, 1211 kgdb_devrate, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comkgdbmode)) { 1212 1213 pxa2x0_clkman_config(cken, 1); 1214 } 1215 1216 #endif 1217 } 1218 #endif 1219 1220 static void 1221 gumstix_device_register(device_t dev, void *aux) 1222 { 1223 prop_dictionary_t dict = device_properties(dev); 1224 1225 if (device_is_a(dev, "arma9tmr") || 1226 device_is_a(dev, "a9wdt")) { 1227 /* 1228 * We need to tell the A9 Global/Watchdog Timer 1229 * what frequency it runs at. 1230 */ 1231 1232 /* 1233 * This clock always runs at (arm_clk div 2) and only goes 1234 * to timers that are part of the A9 MP core subsystem. 1235 */ 1236 prop_dictionary_set_uint32(dict, "frequency", 1237 curcpu()->ci_data.cpu_cc_freq / 2); 1238 } 1239 if (device_is_a(dev, "armperiph")) { 1240 if (device_is_a(device_parent(dev), "mainbus")) { 1241 #if defined(OMAP2) 1242 /* 1243 * XXX KLUDGE ALERT XXX 1244 * The iot mainbus supplies is completely wrong since 1245 * it scales addresses by 2. The simpliest remedy is 1246 * to replace with our bus space used for the armcore 1247 * registers (which armperiph uses). 1248 */ 1249 struct mainbus_attach_args * const mb = aux; 1250 mb->mb_iot = &omap_bs_tag; 1251 #endif 1252 } 1253 } 1254 if (device_is_a(dev, "ehci")) { 1255 #if defined(OVERO) 1256 prop_dictionary_set_uint16(dict, "nports", 2); 1257 prop_dictionary_set_bool(dict, "phy-reset", true); 1258 prop_dictionary_set_cstring(dict, "port0-mode", "none"); 1259 prop_dictionary_set_int16(dict, "port0-gpio", -1); 1260 prop_dictionary_set_cstring(dict, "port1-mode", "phy"); 1261 prop_dictionary_set_int16(dict, "port1-gpio", 183); 1262 prop_dictionary_set_bool(dict, "port1-gpioval", true); 1263 #elif defined(DUOVERO) 1264 prop_dictionary_set_uint16(dict, "nports", 1); 1265 prop_dictionary_set_bool(dict, "phy-reset", true); 1266 prop_dictionary_set_cstring(dict, "port0-mode", "phy"); 1267 prop_dictionary_set_int16(dict, "port0-gpio", 62); 1268 prop_dictionary_set_bool(dict, "port0-gpioval", false); 1269 prop_dictionary_set_bool(dict, "port0-extclk", true); 1270 #endif 1271 prop_dictionary_set_uint16(dict, "dpll5-m", 443); 1272 prop_dictionary_set_uint16(dict, "dpll5-n", 11); 1273 prop_dictionary_set_uint16(dict, "dpll5-m2", 4); 1274 } 1275 if (device_is_a(dev, "ohci")) { 1276 if (prop_dictionary_set_bool(dict, 1277 "Ganged-power-mask-on-port1", 1) == false) { 1278 printf("WARNING: unable to set power-mask for port1" 1279 " property for %s\n", device_xname(dev)); 1280 } 1281 if (prop_dictionary_set_bool(dict, 1282 "Ganged-power-mask-on-port2", 1) == false) { 1283 printf("WARNING: unable to set power-mask for port2" 1284 " property for %s\n", device_xname(dev)); 1285 } 1286 if (prop_dictionary_set_bool(dict, 1287 "Ganged-power-mask-on-port3", 1) == false) { 1288 printf("WARNING: unable to set power-mask for port3" 1289 " property for %s\n", device_xname(dev)); 1290 } 1291 } 1292 if (device_is_a(dev, "omapmputmr")) { 1293 struct obio_attach_args *obio = aux; 1294 1295 switch (obio->obio_addr) { 1296 case 0x49032000: /* GPTIMER2 */ 1297 case 0x49034000: /* GPTIMER3 */ 1298 case 0x49036000: /* GPTIMER4 */ 1299 case 0x49038000: /* GPTIMER5 */ 1300 case 0x4903a000: /* GPTIMER6 */ 1301 case 0x4903c000: /* GPTIMER7 */ 1302 case 0x4903e000: /* GPTIMER8 */ 1303 case 0x49040000: /* GPTIMER9 */ 1304 #if defined(OVERO) 1305 { 1306 /* Ensure enable PRCM.CM_[FI]CLKEN_PER[3:10]. */ 1307 const int en = 1308 1 << (((obio->obio_addr >> 13) & 0x3f) - 0x16); 1309 1310 ioreg_write(OVERO_L4_CORE_VBASE + 0x5000, 1311 ioreg_read(OVERO_L4_CORE_VBASE + 0x5000) | en); 1312 ioreg_write(OVERO_L4_CORE_VBASE + 0x5010, 1313 ioreg_read(OVERO_L4_CORE_VBASE + 0x5010) | en); 1314 } 1315 #endif 1316 break; 1317 } 1318 } 1319 if (device_is_a(dev, "sdhc")) { 1320 bool dualvolt = false; 1321 1322 #if defined(OVERO) || defined(DUOVERO) 1323 if (device_is_a(device_parent(dev), "obio")) { 1324 struct obio_attach_args *obio = aux; 1325 1326 #if defined(OVERO) 1327 if (obio->obio_addr == SDMMC2_BASE_3530) 1328 dualvolt = true; 1329 #elif defined(DUOVERO) 1330 if (obio->obio_addr == SDMMC5_BASE_4430) 1331 dualvolt = true; 1332 #endif 1333 } 1334 #endif 1335 #if defined(PEPPER) 1336 if (device_is_a(device_parent(dev), "mainbus")) { 1337 struct mainbus_attach_args * const mb = aux; 1338 1339 if (mb->mb_iobase == SDMMC3_BASE_TIAM335X) 1340 dualvolt = true; 1341 } 1342 #endif 1343 prop_dictionary_set_bool(dict, "dual-volt", dualvolt); 1344 } 1345 if (device_is_a(dev, "tifb")) { 1346 prop_data_t panel_info; 1347 1348 panel_info = prop_data_create_data_nocopy(tifb_panel_info, 1349 sizeof(struct tifb_panel_info)); 1350 KASSERT(panel_info != NULL); 1351 prop_dictionary_set(dict, "panel-info", panel_info); 1352 prop_object_release(panel_info); 1353 1354 #if defined(OMAP2) 1355 /* enable LCD */ 1356 omap2_gpio_ctl(59, GPIO_PIN_OUTPUT); 1357 omap2_gpio_write(59, 0); /* reset */ 1358 delay(100); 1359 omap2_gpio_write(59, 1); 1360 #endif 1361 } 1362 if (device_is_a(dev, "tps65217pmic")) { 1363 #if defined(TI_AM335X) 1364 extern const char *mpu_supply; 1365 1366 mpu_supply = "DCDC3"; 1367 #endif 1368 1369 if (use_tps65217_wled) { 1370 prop_dictionary_set_int32(dict, "isel", 1); 1371 prop_dictionary_set_int32(dict, "fdim", 200); 1372 prop_dictionary_set_int32(dict, "brightness", 80); 1373 } 1374 } 1375 } 1376
Indexes created Thu Oct 02 14:10:14 GMT 2025