gumstix_machdep.c revision 1.66
1 /* $NetBSD: gumstix_machdep.c,v 1.66 2020/04/18 11:00:39 skrll Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2002, 2003, 2004, 2005 Genetec Corporation. 35 * All rights reserved. 36 * 37 * Written by Hiroyuki Bessho for Genetec Corporation. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. The name of Genetec Corporation may not be used to endorse or 48 * promote products derived from this software without specific prior 49 * written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 53 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 54 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 55 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 * 63 * Machine dependent functions for kernel setup for Genetec G4250EBX 64 * evaluation board. 65 * 66 * Based on iq80310_machhdep.c 67 */ 68 /* 69 * Copyright (c) 2001 Wasabi Systems, Inc. 70 * All rights reserved. 71 * 72 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 3. All advertising materials mentioning features or use of this software 83 * must display the following acknowledgement: 84 * This product includes software developed for the NetBSD Project by 85 * Wasabi Systems, Inc. 86 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 87 * or promote products derived from this software without specific prior 88 * written permission. 89 * 90 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 91 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 92 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 93 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 94 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 95 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 96 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 97 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 98 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 99 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 100 * POSSIBILITY OF SUCH DAMAGE. 101 */ 102 103 /* 104 * Copyright (c) 1997,1998 Mark Brinicombe. 105 * Copyright (c) 1997,1998 Causality Limited. 106 * All rights reserved. 107 * 108 * Redistribution and use in source and binary forms, with or without 109 * modification, are permitted provided that the following conditions 110 * are met: 111 * 1. Redistributions of source code must retain the above copyright 112 * notice, this list of conditions and the following disclaimer. 113 * 2. Redistributions in binary form must reproduce the above copyright 114 * notice, this list of conditions and the following disclaimer in the 115 * documentation and/or other materials provided with the distribution. 116 * 3. All advertising materials mentioning features or use of this software 117 * must display the following acknowledgement: 118 * This product includes software developed by Mark Brinicombe 119 * for the NetBSD Project. 120 * 4. The name of the company nor the name of the author may be used to 121 * endorse or promote products derived from this software without specific 122 * prior written permission. 123 * 124 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 125 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 126 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 127 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 128 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 129 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 130 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 131 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 132 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 133 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 134 * SUCH DAMAGE. 135 * 136 * Machine dependent functions for kernel setup for Intel IQ80310 evaluation 137 * boards using RedBoot firmware. 138 */ 139 140 #include "opt_arm_debug.h" 141 #include "opt_com.h" 142 #include "opt_console.h" 143 #include "opt_cputypes.h" 144 #include "opt_evbarm_boardtype.h" 145 #include "opt_gumstix.h" 146 #include "opt_kgdb.h" 147 #include "opt_multiprocessor.h" 148 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 149 #include "opt_omap.h" 150 151 #if defined(DUOVERO) 152 #include "arml2cc.h" 153 #endif 154 #include "prcm.h" 155 #endif 156 157 #include <sys/param.h> 158 #include <sys/conf.h> 159 #include <sys/device.h> 160 #include <sys/exec.h> 161 #include <sys/kernel.h> 162 #include <sys/proc.h> 163 #include <sys/reboot.h> 164 #include <sys/systm.h> 165 #include <sys/termios.h> 166 #include <sys/bus.h> 167 #include <sys/cpu.h> 168 #include <sys/gpio.h> 169 170 #include <prop/proplib.h> 171 172 #include <uvm/uvm_extern.h> 173 174 #include <arm/mainbus/mainbus.h> /* don't reorder */ 175 176 #include <machine/autoconf.h> /* don't reorder */ 177 #include <machine/bootconfig.h> 178 #include <arm/locore.h> 179 180 #include <arm/arm32/machdep.h> 181 182 #include <arm/omap/omap2_obiovar.h> 183 #include <arm/omap/am335x_prcm.h> 184 #include <arm/omap/omap2_gpio.h> 185 #include <arm/omap/omap2_gpmcreg.h> 186 #include <arm/omap/omap2_prcm.h> 187 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 188 #include <arm/omap/omap2_reg.h> /* Must required "opt_omap.h" */ 189 #endif 190 #include <arm/omap/omap3_sdmmcreg.h> 191 #include <arm/omap/omap_var.h> 192 #include <arm/omap/omap_com.h> 193 #include <arm/omap/tifbvar.h> 194 195 #include <arm/xscale/pxa2x0reg.h> 196 #include <arm/xscale/pxa2x0var.h> 197 #include <arm/xscale/pxa2x0_gpio.h> 198 #include <evbarm/gumstix/gumstixreg.h> 199 #include <evbarm/gumstix/gumstixvar.h> 200 201 #if defined(CPU_CORTEXA9) 202 #include <arm/cortex/pl310_var.h> 203 #include <arm/cortex/pl310_reg.h> 204 #include <arm/cortex/scu_reg.h> 205 206 #include <arm/cortex/a9tmr_var.h> 207 #endif 208 209 #if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) 210 #include <arm/cortex/gtmr_var.h> 211 #endif 212 213 #include <dev/cons.h> 214 215 #ifdef KGDB 216 #include <sys/kgdb.h> 217 #endif 218 219 #ifdef VERBOSE_INIT_ARM 220 #define VPRINTF(...) printf(__VA_ARGS__) 221 #else 222 #define VPRINTF(...) __nothing 223 #endif 224 225 /* 226 * The range 0xc1000000 - 0xfd000000 is available for kernel VM space 227 * Core-logic registers and I/O mappings occupy 228 * 229 * 0xfd000000 - 0xfd800000 on gumstix 230 * 0xc0000000 - 0xc0400000 on overo, duovero and pepper 231 */ 232 #ifndef KERNEL_VM_BASE 233 #define KERNEL_VM_BASE 0xc8000000 234 #endif 235 #define KERNEL_VM_SIZE 0x35000000 236 237 BootConfig bootconfig; /* Boot config storage */ 238 static char bootargs[MAX_BOOT_STRING]; 239 const size_t bootargs_len = sizeof(bootargs) - 1; /* without nul */ 240 char *boot_args = NULL; 241 242 uint32_t system_serial_high; 243 uint32_t system_serial_low; 244 245 /* Prototypes */ 246 #if defined(GUMSTIX) 247 static void read_system_serial(void); 248 #endif 249 #if defined(OMAP2) 250 static void omap_reset(void); 251 static void find_cpu_clock(void); 252 #endif 253 static void process_kernel_args(int, char *[]); 254 static void process_kernel_args_liner(char *); 255 #ifdef KGDB 256 static void kgdb_port_init(void); 257 #endif 258 static void gumstix_device_register(device_t, void *); 259 260 bs_protos(bs_notimpl); 261 262 #include "com.h" 263 #if NCOM > 0 264 #include <dev/ic/comreg.h> 265 #include <dev/ic/comvar.h> 266 #endif 267 268 #if defined(CPU_XSCALE) 269 #include "lcd.h" 270 #endif 271 272 #ifndef CONSPEED 273 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 274 #endif 275 #ifndef CONMODE 276 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 277 #endif 278 279 int comcnspeed = CONSPEED; 280 int comcnmode = CONMODE; 281 282 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 283 static char console[16]; 284 #endif 285 286 const struct tifb_panel_info *tifb_panel_info = NULL; 287 /* Use TPS65217 White LED Driver */ 288 bool use_tps65217_wled = false; 289 290 extern void gxio_config(void); 291 extern void gxio_config_expansion(char *); 292 293 294 static inline pd_entry_t * 295 read_ttb(void) 296 { 297 long ttb; 298 299 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); 300 301 return (pd_entry_t *)(ttb & ~((1<<14)-1)); 302 } 303 304 /* 305 * Static device mappings. These peripheral registers are mapped at 306 * fixed virtual addresses very early in initarm() so that we can use 307 * them while booting the kernel, and stay at the same address 308 * throughout whole kernel's life time. 309 * 310 * We use this table twice; once with bootstrap page table, and once 311 * with kernel's page table which we build up in initarm(). 312 * 313 * Since we map these registers into the bootstrap page table using 314 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 315 * registers segment-aligned and segment-rounded in order to avoid 316 * using the 2nd page tables. 317 */ 318 319 #define _A(a) ((a) & ~L1_S_OFFSET) 320 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 321 322 static const struct pmap_devmap gumstix_devmap[] = { 323 #if defined(GUMSTIX) 324 { 325 GUMSTIX_GPIO_VBASE, 326 _A(PXA2X0_GPIO_BASE), 327 _S(PXA250_GPIO_SIZE), 328 VM_PROT_READ | VM_PROT_WRITE, 329 PTE_NOCACHE, 330 }, 331 { 332 GUMSTIX_CLKMAN_VBASE, 333 _A(PXA2X0_CLKMAN_BASE), 334 _S(PXA2X0_CLKMAN_SIZE), 335 VM_PROT_READ | VM_PROT_WRITE, 336 PTE_NOCACHE, 337 }, 338 { 339 GUMSTIX_INTCTL_VBASE, 340 _A(PXA2X0_INTCTL_BASE), 341 _S(PXA2X0_INTCTL_SIZE), 342 VM_PROT_READ | VM_PROT_WRITE, 343 PTE_NOCACHE, 344 }, 345 { 346 GUMSTIX_FFUART_VBASE, 347 _A(PXA2X0_FFUART_BASE), 348 _S(4 * COM_NPORTS), 349 VM_PROT_READ | VM_PROT_WRITE, 350 PTE_NOCACHE, 351 }, 352 { 353 GUMSTIX_STUART_VBASE, 354 _A(PXA2X0_STUART_BASE), 355 _S(4 * COM_NPORTS), 356 VM_PROT_READ | VM_PROT_WRITE, 357 PTE_NOCACHE, 358 }, 359 { 360 GUMSTIX_BTUART_VBASE, 361 _A(PXA2X0_BTUART_BASE), 362 _S(4 * COM_NPORTS), 363 VM_PROT_READ | VM_PROT_WRITE, 364 PTE_NOCACHE, 365 }, 366 { 367 GUMSTIX_HWUART_VBASE, 368 _A(PXA2X0_HWUART_BASE), 369 _S(4 * COM_NPORTS), 370 VM_PROT_READ | VM_PROT_WRITE, 371 PTE_NOCACHE, 372 }, 373 { 374 GUMSTIX_LCDC_VBASE, 375 _A(PXA2X0_LCDC_BASE), 376 _S(4 * COM_NPORTS), 377 VM_PROT_READ | VM_PROT_WRITE, 378 PTE_NOCACHE, 379 }, 380 #elif defined(OVERO) 381 { /* SCM, PRCM */ 382 OVERO_L4_CORE_VBASE, 383 _A(OMAP3530_L4_CORE_BASE), 384 _S(L1_S_SIZE), /* No need 16MB. Use only first 1MB */ 385 VM_PROT_READ | VM_PROT_WRITE, 386 PTE_NOCACHE 387 }, 388 { /* Console, GPIO[2-6] */ 389 OVERO_L4_PERIPHERAL_VBASE, 390 _A(OMAP3530_L4_PERIPHERAL_BASE), 391 _S(OMAP3530_L4_PERIPHERAL_SIZE), 392 VM_PROT_READ | VM_PROT_WRITE, 393 PTE_NOCACHE 394 }, 395 { /* GPIO1 */ 396 OVERO_L4_WAKEUP_VBASE, 397 _A(OMAP3530_L4_WAKEUP_BASE), 398 _S(OMAP3530_L4_WAKEUP_SIZE), 399 VM_PROT_READ | VM_PROT_WRITE, 400 PTE_NOCACHE 401 }, 402 { 403 OVERO_GPMC_VBASE, 404 _A(GPMC_BASE), 405 _S(GPMC_SIZE), 406 VM_PROT_READ | VM_PROT_WRITE, 407 PTE_NOCACHE 408 }, 409 { 410 OVERO_SRDC_VBASE, 411 _A(OMAP3530_SDRC_BASE), 412 _S(OMAP3530_SDRC_SIZE), 413 VM_PROT_READ | VM_PROT_WRITE, 414 PTE_NOCACHE 415 }, 416 #elif defined(DUOVERO) 417 { 418 DUOVERO_L4_CM_VBASE, 419 _A(OMAP4430_L4_CORE_BASE + 0x100000), 420 _S(L1_S_SIZE), 421 VM_PROT_READ | VM_PROT_WRITE, 422 PTE_NOCACHE 423 }, 424 { /* Console, SCU, L2CC, GPIO[2-6] */ 425 DUOVERO_L4_PERIPHERAL_VBASE, 426 _A(OMAP4430_L4_PERIPHERAL_BASE), 427 _S(L1_S_SIZE * 3), 428 VM_PROT_READ | VM_PROT_WRITE, 429 PTE_NOCACHE 430 }, 431 { /* PRCM, GPIO1 */ 432 DUOVERO_L4_WAKEUP_VBASE, 433 _A(OMAP4430_L4_WAKEUP_BASE), 434 _S(OMAP4430_L4_WAKEUP_SIZE), 435 VM_PROT_READ | VM_PROT_WRITE, 436 PTE_NOCACHE 437 }, 438 { 439 DUOVERO_GPMC_VBASE, 440 _A(GPMC_BASE), 441 _S(GPMC_SIZE), 442 VM_PROT_READ | VM_PROT_WRITE, 443 PTE_NOCACHE 444 }, 445 { 446 DUOVERO_DMM_VBASE, 447 _A(OMAP4430_DMM_BASE), 448 _S(OMAP4430_DMM_SIZE), 449 VM_PROT_READ | VM_PROT_WRITE, 450 PTE_NOCACHE 451 }, 452 #elif defined(PEPPER) 453 { 454 /* CM, Control Module, GPIO0, Console */ 455 PEPPER_PRCM_VBASE, 456 _A(OMAP2_CM_BASE), 457 _S(L1_S_SIZE), 458 VM_PROT_READ | VM_PROT_WRITE, 459 PTE_NOCACHE 460 }, 461 { 462 /* GPIO[1-3] */ 463 PEPPER_L4_PERIPHERAL_VBASE, 464 _A(TI_AM335X_L4_PERIPHERAL_BASE), 465 _S(L1_S_SIZE), 466 VM_PROT_READ | VM_PROT_WRITE, 467 PTE_NOCACHE 468 }, 469 #endif 470 { 0, 0, 0, 0, 0 } 471 }; 472 473 #undef _A 474 #undef _S 475 476 #ifdef MULTIPROCESSOR 477 void gumstix_cpu_hatch(struct cpu_info *); 478 479 void 480 gumstix_cpu_hatch(struct cpu_info *ci) 481 { 482 #if defined(CPU_CORTEXA9) 483 a9tmr_init_cpu_clock(ci); 484 #elif defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) 485 gtmr_init_cpu_clock(ci); 486 #endif 487 } 488 #endif 489 490 491 static void 492 gumstix_mpstart(void) 493 { 494 #if defined(MULTIPROCESSOR) 495 const bus_space_tag_t iot = &omap_bs_tag; 496 int error; 497 498 #if defined(CPU_CORTEXA9) 499 bus_space_handle_t scu_ioh; 500 error = bus_space_map(iot, OMAP4_SCU_BASE, OMAP4_SCU_SIZE, 0, &scu_ioh); 501 if (error) 502 panic("Could't map OMAP4_SCU_BASE"); 503 504 /* 505 * Invalidate all SCU cache tags. That is, for all cores (0-3) 506 */ 507 bus_space_write_4(iot, scu_ioh, SCU_INV_ALL_REG, 0xffff); 508 509 uint32_t diagctl = bus_space_read_4(iot, scu_ioh, SCU_DIAG_CONTROL); 510 diagctl |= SCU_DIAG_DISABLE_MIGBIT; 511 bus_space_write_4(iot, scu_ioh, SCU_DIAG_CONTROL, diagctl); 512 513 uint32_t scu_ctl = bus_space_read_4(iot, scu_ioh, SCU_CTL); 514 scu_ctl |= SCU_CTL_SCU_ENA; 515 bus_space_write_4(iot, scu_ioh, SCU_CTL, scu_ctl); 516 517 armv7_dcache_wbinv_all(); 518 #endif 519 bus_space_handle_t wugen_ioh; 520 error = bus_space_map(iot, OMAP4_WUGEN_BASE, OMAP4_WUGEN_SIZE, 0, 521 &wugen_ioh); 522 if (error) 523 panic("Couldn't map OMAP4_WUGEN_BASE"); 524 const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart); 525 526 bus_space_write_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT1, mpstart); 527 528 for (size_t i = 1; i < arm_cpu_max; i++) { 529 uint32_t boot = bus_space_read_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT0); 530 boot |= __SHIFTIN(0xf, i * 4); 531 bus_space_write_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT0, boot); 532 } 533 534 arm_dsb(); 535 __asm __volatile("sev" ::: "memory"); 536 537 for (int loop = 0; loop < 16; loop++) { 538 VPRINTF("%u hatched %#x\n", loop, arm_cpu_hatched); 539 if (arm_cpu_hatched == __BITS(arm_cpu_max - 1, 1)) 540 break; 541 int timo = 1500000; 542 while (arm_cpu_hatched != __BITS(arm_cpu_max - 1, 1)) 543 if (--timo == 0) 544 break; 545 } 546 for (size_t i = 1; i < arm_cpu_max; i++) { 547 if (cpu_hatched_p(i)) { 548 printf("%s: warning: cpu%zu failed to hatch\n", 549 __func__, i); 550 } 551 } 552 553 VPRINTF(" (%u cpu%s, hatched %#x)", 554 arm_cpu_max, arm_cpu_max ? "s" : "", 555 arm_cpu_hatched); 556 #endif 557 } 558 559 #if defined(CPU_CORTEX) 560 /* filled in before cleaning bss. keep in .data */ 561 u_int uboot_args[4] __attribute__((__section__(".data"))); 562 #else 563 extern uint32_t *uboot_args; 564 #endif 565 566 /* 567 * vaddr_t initarm(...) 568 * 569 * Initial entry point on startup. This gets called before main() is 570 * entered. 571 * It should be responsible for setting up everything that must be 572 * in place when main is called. 573 * This includes 574 * Taking a copy of the boot configuration structure. 575 * Initialising the physical console so characters can be printed. 576 * Setting up page tables for the kernel 577 * Relocating the kernel to the bottom of physical memory 578 */ 579 vaddr_t 580 initarm(void *arg) 581 { 582 extern char KERNEL_BASE_phys[]; 583 uint32_t ram_size = 0x400000; 584 enum { r0 = 0, r1 = 1, r2 = 2, r3 = 3 }; /* args from u-boot */ 585 586 #if defined(OVERO) || defined(DUOVERO) /* || defined(PEPPER) */ 587 const bus_space_tag_t iot = &omap_bs_tag; 588 #endif 589 590 #if defined(CPU_XSCALE) 591 592 /* 593 * We mapped PA == VA in gumstix_start.S. 594 * Also mapped SDRAM to KERNEL_BASE first 64Mbyte only with cachable. 595 * 596 * Gumstix (basix, connex, verdex, verdex-pro): 597 * Physical Address Range Description 598 * ----------------------- ---------------------------------- 599 * 0x00000000 - 0x00ffffff flash Memory (16MB or 4MB) 600 * 0x40000000 - 0x480fffff Processor Registers 601 * 0xa0000000 - 0xa3ffffff SDRAM Bank 0 (64MB or 128MB) 602 * 0xc0000000 - 0xc3ffffff KERNEL_BASE 603 */ 604 extern vaddr_t xscale_cache_clean_addr; 605 xscale_cache_clean_addr = 0xff000000U; 606 607 cpu_reset_address = NULL; 608 #elif defined(OMAP2) 609 cpu_reset_address = omap_reset; 610 611 find_cpu_clock(); 612 #endif 613 614 /* 615 * Heads up ... Setup the CPU / MMU / TLB functions 616 */ 617 if (set_cpufuncs()) 618 panic("cpu not recognized!"); 619 620 /* map some peripheral registers at static I/O area */ 621 pmap_devmap_bootstrap((vaddr_t)read_ttb(), gumstix_devmap); 622 623 #if defined(CPU_XSCALE) 624 /* start 32.768kHz OSC */ 625 ioreg_write(GUMSTIX_CLKMAN_VBASE + CLKMAN_OSCC, OSCC_OON); 626 627 /* Get ready for splfoo() */ 628 pxa2x0_intr_bootstrap(GUMSTIX_INTCTL_VBASE); 629 630 /* setup GPIO for {FF,ST,HW}UART. */ 631 pxa2x0_gpio_bootstrap(GUMSTIX_GPIO_VBASE); 632 633 pxa2x0_clkman_bootstrap(GUMSTIX_CLKMAN_VBASE); 634 #endif 635 636 637 #if defined(OVERO) 638 639 #define OMAP3530_SRDC_MCFG_p(p) (0x80 + ((p) * 0x30)) 640 #define OMAP3530_SRDC_MCFG_RAMSIZE __BITS(17,8) 641 642 bus_space_handle_t sdrcioh; 643 if (bus_space_map(iot, OMAP3530_SDRC_BASE, OMAP3530_SDRC_SIZE, 644 0, &sdrcioh) != 0) 645 panic("OMAP_SDRC_BASE map failed\n"); 646 647 ram_size = 0; 648 for (u_int p = 0; p < 2; p++) { 649 uint32_t mcfg = bus_space_read_4(iot, sdrcioh, 650 OMAP3530_SRDC_MCFG_p(p)); 651 ram_size += __SHIFTOUT(mcfg, OMAP3530_SRDC_MCFG_RAMSIZE) * 652 (2 * 1024 * 1024); 653 } 654 655 #elif defined(DUOVERO) 656 657 #define OMAP4_DMM_LISA_MAP_i(i) (0x40 + ((i) * 0x4)) 658 #define OMAP4_DMM_LISA_SYS_ADDR __BITS(31,24) 659 #define OMAP4_DMM_LISA_SYS_SIZE __BITS(22,20) 660 #define OMAP4_DMM_LISA_SDRC_ADDRSPC __BITS(17,16) 661 662 bus_space_handle_t dmmioh; 663 if (bus_space_map(iot, OMAP4430_DMM_BASE, OMAP4430_DMM_SIZE, 0, 664 &dmmioh) != 0) 665 panic("OMAP4_DMM_BASE map failed\n"); 666 667 ram_size = 0; 668 for (u_int i = 0; i < 4; i++) { 669 const uint32_t lisa = bus_space_read_4(iot, dmmioh, 670 OMAP4_DMM_LISA_MAP_i(i)); 671 672 const uint32_t sys_addr = 673 __SHIFTOUT(lisa, OMAP4_DMM_LISA_SYS_ADDR); 674 /* skip non-physical */ 675 if ((sys_addr & 0x80) != 0) 676 continue; 677 678 const uint32_t sdrc_addrspc = 679 __SHIFTOUT(lisa, OMAP4_DMM_LISA_SDRC_ADDRSPC); 680 /* Skip reserced areas */ 681 if (sdrc_addrspc == 2) 682 continue; 683 684 const uint32_t sys_size = 685 __SHIFTOUT(lisa, OMAP4_DMM_LISA_SYS_SIZE); 686 ram_size += (16 * 1024 * 1024) << sys_size; 687 } 688 689 690 #endif 691 692 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 693 694 /* configure MUX, GPIO and CLK. */ 695 gxio_config(); 696 697 #ifndef GUMSTIX_NETBSD_ARGS_CONSOLE 698 consinit(); 699 #endif 700 #ifdef KGDB 701 kgdb_port_init(); 702 #endif 703 704 /* 705 * Examine the boot args string for options we need to know about 706 * now. 707 */ 708 #if defined(GUMSTIX) 709 #define SDRAM_START 0xa0000000UL 710 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 711 #define SDRAM_START 0x80000000UL 712 #endif 713 if (uboot_args[r0] < SDRAM_START || 714 uboot_args[r0] >= SDRAM_START + ram_size) 715 /* Maybe r0 is 'argc'. We are booted by command 'go'. */ 716 process_kernel_args(uboot_args[r0], (char **)uboot_args[r1]); 717 else 718 /* 719 * Maybe r3 is 'boot args string' of 'bootm'. This string is 720 * linely. 721 */ 722 process_kernel_args_liner((char *)uboot_args[r3]); 723 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 724 consinit(); 725 #endif 726 727 /* Talk to the user */ 728 #define BDSTR(s) _BDSTR(s) 729 #define _BDSTR(s) #s 730 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 731 732 /* Read system serial */ 733 #if defined(GUMSTIX) 734 read_system_serial(); 735 #endif 736 737 VPRINTF("initarm: Configuring system ...\n"); 738 739 #if defined(OMAP_4430) 740 bus_space_handle_t ioh; 741 742 #if NARML2CC > 0 743 /* 744 * Initialize L2-Cache parameters 745 */ 746 747 if (bus_space_map(iot, OMAP4_L2CC_BASE, OMAP4_L2CC_SIZE, 0, &ioh) != 0) 748 panic("OMAP4_L2CC_BASE map failed\n"); 749 arml2cc_init(iot, ioh, 0); 750 #endif 751 752 #ifdef MULTIPROCESSOR 753 if (bus_space_map(iot, OMAP4_SCU_BASE, SCU_SIZE, 0, &ioh) != 0) 754 panic("OMAP4_SCU_BASE map failed\n"); 755 arm_cpu_max = 756 1 + (bus_space_read_4(iot, ioh, SCU_CFG) & SCU_CFG_CPUMAX); 757 #endif 758 #endif 759 760 /* Fake bootconfig structure for the benefit of pmap.c */ 761 /* XXX must make the memory description h/w independent */ 762 bootconfig.dramblocks = 1; 763 bootconfig.dram[0].address = SDRAM_START; 764 bootconfig.dram[0].pages = ram_size / PAGE_SIZE; 765 766 KASSERT(ram_size <= KERNEL_VM_BASE - KERNEL_BASE); 767 768 arm32_bootmem_init(bootconfig.dram[0].address, ram_size, 769 (uintptr_t) KERNEL_BASE_phys); 770 arm32_kernel_vm_init(KERNEL_VM_BASE, 771 #if defined(CPU_XSCALE) 772 ARM_VECTORS_LOW, 773 #elif defined(CPU_CORTEX) 774 ARM_VECTORS_HIGH, 775 #endif 776 0, gumstix_devmap, true); 777 778 evbarm_device_register = gumstix_device_register; 779 780 vaddr_t sp = initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 781 782 /* 783 * initarm_common flushes cache if required before AP start 784 */ 785 gumstix_mpstart(); 786 787 return sp; 788 } 789 790 #if defined(GUMSTIX) 791 static void 792 read_system_serial(void) 793 { 794 #define GUMSTIX_SYSTEM_SERIAL_ADDR 0 795 #define GUMSTIX_SYSTEM_SERIAL_SIZE 8 796 #define FLASH_OFFSET_INTEL_PROTECTION 0x81 797 #define FLASH_OFFSET_USER_PROTECTION 0x85 798 #define FLASH_CMD_READ_ID 0x90 799 #define FLASH_CMD_RESET 0xff 800 int i; 801 char system_serial[GUMSTIX_SYSTEM_SERIAL_SIZE], *src; 802 char x; 803 804 src = (char *)(FLASH_OFFSET_USER_PROTECTION * 2 /*word*/); 805 *(volatile uint16_t *)0 = FLASH_CMD_READ_ID; 806 memcpy(system_serial, 807 src + GUMSTIX_SYSTEM_SERIAL_ADDR, sizeof (system_serial)); 808 *(volatile uint16_t *)0 = FLASH_CMD_RESET; 809 810 for (i = 1, x = system_serial[0]; i < sizeof (system_serial); i++) 811 x &= system_serial[i]; 812 if (x == 0xff) { 813 src = (char *)(FLASH_OFFSET_INTEL_PROTECTION * 2 /*word*/); 814 *(volatile uint16_t *)0 = FLASH_CMD_READ_ID; 815 memcpy(system_serial, 816 src + GUMSTIX_SYSTEM_SERIAL_ADDR, sizeof (system_serial)); 817 *(volatile uint16_t *)0 = FLASH_CMD_RESET; 818 819 /* 820 * XXXX: Don't need ??? 821 * gumstix_serial_hash(system_serial); 822 */ 823 } 824 system_serial_high = system_serial[0] << 24 | system_serial[1] << 16 | 825 system_serial[2] << 8 | system_serial[3]; 826 system_serial_low = system_serial[4] << 24 | system_serial[5] << 16 | 827 system_serial[6] << 8 | system_serial[7]; 828 829 printf("system serial: 0x"); 830 for (i = 0; i < sizeof (system_serial); i++) 831 printf("%02x", system_serial[i]); 832 printf("\n"); 833 } 834 #endif 835 836 #if defined(OMAP2) 837 static void 838 omap_reset(void) 839 { 840 841 #if defined(TI_AM335X) 842 vaddr_t prm_base = (PEPPER_PRCM_VBASE + AM335X_PRCM_PRM_DEVICE); 843 844 *(volatile uint32_t *)(prm_base + PRM_RSTCTRL) = RST_GLOBAL_WARM_SW; 845 #elif defined(OMAP_4430) 846 *(volatile uint32_t *)(DUOVERO_L4_WAKEUP_VBASE + OMAP4_PRM_RSTCTRL) = 847 OMAP4_PRM_RSTCTRL_WARM; 848 #endif 849 850 #if NPRCM > 0 851 prcm_cold_reset(); 852 #endif 853 } 854 855 static void 856 find_cpu_clock(void) 857 { 858 const vaddr_t prm_base __unused = OMAP2_PRM_BASE; 859 const vaddr_t cm_base = OMAP2_CM_BASE; 860 861 #if defined(OMAP_3530) 862 863 const uint32_t prm_clksel = 864 *(volatile uint32_t *)(prm_base + PLL_MOD + OMAP3_PRM_CLKSEL); 865 static const uint32_t prm_clksel_freqs[] = OMAP3_PRM_CLKSEL_FREQS; 866 const uint32_t sys_clk = 867 prm_clksel_freqs[__SHIFTOUT(prm_clksel, OMAP3_PRM_CLKSEL_CLKIN)]; 868 const uint32_t dpll1 = 869 *(volatile uint32_t *)(cm_base + OMAP3_CM_CLKSEL1_PLL_MPU); 870 const uint32_t dpll2 = 871 *(volatile uint32_t *)(cm_base + OMAP3_CM_CLKSEL2_PLL_MPU); 872 const uint32_t m = 873 __SHIFTOUT(dpll1, OMAP3_CM_CLKSEL1_PLL_MPU_DPLL_MULT); 874 const uint32_t n = __SHIFTOUT(dpll1, OMAP3_CM_CLKSEL1_PLL_MPU_DPLL_DIV); 875 const uint32_t m2 = 876 __SHIFTOUT(dpll2, OMAP3_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV); 877 878 /* 879 * MPU_CLK supplies ARM_FCLK which is twice the CPU frequency. 880 */ 881 curcpu()->ci_data.cpu_cc_freq = 882 ((sys_clk * m) / ((n + 1) * m2 * 2)) * OMAP3_PRM_CLKSEL_MULT; 883 omap_sys_clk = sys_clk * OMAP3_PRM_CLKSEL_MULT; 884 885 #elif defined(OMAP_4430) 886 887 const uint32_t prm_clksel = 888 *(volatile uint32_t *)(prm_base + OMAP4_CM_SYS_CLKSEL); 889 static const uint32_t cm_clksel_freqs[] = OMAP4_CM_CLKSEL_FREQS; 890 const uint32_t sys_clk = 891 cm_clksel_freqs[__SHIFTOUT(prm_clksel, OMAP4_CM_SYS_CLKSEL_CLKIN)]; 892 const uint32_t dpll1 = 893 *(volatile uint32_t *)(cm_base + OMAP4_CM_CLKSEL_DPLL_MPU); 894 const uint32_t dpll2 = 895 *(volatile uint32_t *)(cm_base + OMAP4_CM_DIV_M2_DPLL_MPU); 896 const uint32_t m = 897 __SHIFTOUT(dpll1, OMAP4_CM_CLKSEL_DPLL_MPU_DPLL_MULT); 898 const uint32_t n = __SHIFTOUT(dpll1, OMAP4_CM_CLKSEL_DPLL_MPU_DPLL_DIV); 899 const uint32_t m2 = 900 __SHIFTOUT(dpll2, OMAP4_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIV); 901 902 /* 903 * MPU_CLK supplies ARM_FCLK which is twice the CPU frequency. 904 */ 905 curcpu()->ci_data.cpu_cc_freq = 906 ((sys_clk * 2 * m) / ((n + 1) * m2)) * OMAP4_CM_CLKSEL_MULT / 2; 907 omap_sys_clk = sys_clk * OMAP4_CM_CLKSEL_MULT; 908 909 #elif defined(TI_AM335X) 910 911 prcm_bootstrap(cm_base); 912 am335x_sys_clk(TI_AM335X_CTLMOD_BASE); 913 am335x_cpu_clk(); 914 915 #endif 916 } 917 #endif 918 919 #ifdef GUMSTIX_NETBSD_ARGS_BUSHEADER 920 static const char busheader_name[] = "busheader="; 921 #endif 922 #if defined(GUMSTIX_NETBSD_ARGS_BUSHEADER) || \ 923 defined(GUMSTIX_NETBSD_ARGS_EXPANSION) 924 static const char expansion_name[] = "expansion="; 925 #endif 926 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 927 static const char console_name[] = "console="; 928 #endif 929 static void 930 process_kernel_args(int argc, char *argv[]) 931 { 932 int gxio_configured = 0, i, j; 933 934 boothowto = 0; 935 936 for (i = 1, j = 0; i < argc; i++) { 937 #ifdef GUMSTIX_NETBSD_ARGS_BUSHEADER 938 if (!strncmp(argv[i], busheader_name, strlen(busheader_name))) { 939 /* Configure for GPIOs of busheader side */ 940 gxio_config_expansion(argv[i] + strlen(busheader_name)); 941 gxio_configured = 1; 942 continue; 943 } 944 #endif 945 #if defined(GUMSTIX_NETBSD_ARGS_BUSHEADER) || \ 946 defined(GUMSTIX_NETBSD_ARGS_EXPANSION) 947 if (!strncmp(argv[i], expansion_name, strlen(expansion_name))) { 948 /* Configure expansion */ 949 gxio_config_expansion(argv[i] + strlen(expansion_name)); 950 gxio_configured = 1; 951 continue; 952 } 953 #endif 954 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 955 if (!strncmp(argv[i], console_name, strlen(console_name))) { 956 strncpy(console, argv[i] + strlen(console_name), 957 sizeof(console)); 958 consinit(); 959 } 960 #endif 961 if (j == bootargs_len) { 962 *(bootargs + j) = '\0'; 963 continue; 964 } 965 if (j != 0) 966 *(bootargs + j++) = ' '; 967 strncpy(bootargs + j, argv[i], bootargs_len - j); 968 bootargs[bootargs_len] = '\0'; 969 j += strlen(argv[i]); 970 } 971 boot_args = bootargs; 972 973 parse_mi_bootargs(boot_args); 974 975 if (!gxio_configured) 976 gxio_config_expansion(NULL); 977 } 978 979 static void 980 process_kernel_args_liner(char *args) 981 { 982 int i = 0; 983 char *p = NULL; 984 985 boothowto = 0; 986 987 strncpy(bootargs, args, sizeof(bootargs)); 988 #if defined(GUMSTIX_NETBSD_ARGS_BUSHEADER) || \ 989 defined(GUMSTIX_NETBSD_ARGS_EXPANSION) 990 { 991 char *q; 992 993 if ((p = strstr(bootargs, expansion_name))) 994 q = p + strlen(expansion_name); 995 #ifdef GUMSTIX_NETBSD_ARGS_BUSHEADER 996 else if ((p = strstr(bootargs, busheader_name))) 997 q = p + strlen(busheader_name); 998 #endif 999 if (p) { 1000 char expansion[256], c; 1001 1002 i = 0; 1003 do { 1004 c = *(q + i); 1005 if (c == ' ') 1006 c = '\0'; 1007 expansion[i++] = c; 1008 } while (c != '\0' && i < sizeof(expansion)); 1009 gxio_config_expansion(expansion); 1010 strcpy(p, q + i); 1011 } 1012 } 1013 #endif 1014 if (p == NULL) 1015 gxio_config_expansion(NULL); 1016 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 1017 p = strstr(bootargs, console_name); 1018 if (p != NULL) { 1019 char c; 1020 1021 i = 0; 1022 do { 1023 c = *(p + strlen(console_name) + i); 1024 if (c == ' ') 1025 c = '\0'; 1026 console[i++] = c; 1027 } while (c != '\0' && i < sizeof(console)); 1028 consinit(); 1029 strcpy(p, p + strlen(console_name) + i); 1030 } 1031 #endif 1032 boot_args = bootargs; 1033 1034 parse_mi_bootargs(boot_args); 1035 } 1036 1037 #ifdef KGDB 1038 #ifndef KGDB_DEVNAME 1039 #define KGDB_DEVNAME "ffuart" 1040 #endif 1041 const char kgdb_devname[] = KGDB_DEVNAME; 1042 1043 #ifndef KGDB_DEVRATE 1044 #define KGDB_DEVRATE CONSPEED 1045 #endif 1046 int kgdb_devrate = KGDB_DEVRATE; 1047 1048 #if (NCOM > 0) 1049 #ifndef KGDB_DEVMODE 1050 #define KGDB_DEVMODE CONMODE 1051 #endif 1052 int comkgdbmode = KGDB_DEVMODE; 1053 #endif /* NCOM */ 1054 1055 #endif /* KGDB */ 1056 1057 1058 void 1059 consinit(void) 1060 { 1061 static int consinit_called = 0; 1062 1063 if (consinit_called != 0) 1064 return; 1065 1066 consinit_called = 1; 1067 1068 #if NCOM > 0 1069 1070 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 1071 /* Maybe passed Linux's bootargs 'console=ttyS?,<speed>...' */ 1072 if (strncmp(console, "ttyS", 4) == 0 && console[5] == ',') { 1073 int i; 1074 1075 comcnspeed = 0; 1076 for (i = 6; i < strlen(console) && isdigit(console[i]); i++) 1077 comcnspeed = comcnspeed * 10 + (console[i] - '0'); 1078 } 1079 #endif 1080 1081 #if defined(GUMSTIX) 1082 1083 #ifdef FFUARTCONSOLE 1084 #ifdef KGDB 1085 if (strcmp(kgdb_devname, "ffuart") == 0){ 1086 /* port is reserved for kgdb */ 1087 } else 1088 #endif 1089 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1090 if (console[0] == '\0' || strcasecmp(console, "ffuart") == 0 || 1091 strncmp(console, "ttyS0,", 6) == 0) 1092 #endif 1093 { 1094 int rv; 1095 1096 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_FFUART_BASE, 1097 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1098 if (rv == 0) { 1099 pxa2x0_clkman_config(CKEN_FFUART, 1); 1100 return; 1101 } 1102 } 1103 #endif /* FFUARTCONSOLE */ 1104 1105 #ifdef STUARTCONSOLE 1106 #ifdef KGDB 1107 if (strcmp(kgdb_devname, "stuart") == 0) { 1108 /* port is reserved for kgdb */ 1109 } else 1110 #endif 1111 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1112 if (console[0] == '\0' || strcasecmp(console, "stuart") == 0) 1113 #endif 1114 { 1115 int rv; 1116 1117 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_STUART_BASE, 1118 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1119 if (rv == 0) { 1120 pxa2x0_clkman_config(CKEN_STUART, 1); 1121 return; 1122 } 1123 } 1124 #endif /* STUARTCONSOLE */ 1125 1126 #ifdef BTUARTCONSOLE 1127 #ifdef KGDB 1128 if (strcmp(kgdb_devname, "btuart") == 0) { 1129 /* port is reserved for kgdb */ 1130 } else 1131 #endif 1132 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1133 if (console[0] == '\0' || strcasecmp(console, "btuart") == 0) 1134 #endif 1135 { 1136 int rv; 1137 1138 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_BTUART_BASE, 1139 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1140 if (rv == 0) { 1141 pxa2x0_clkman_config(CKEN_BTUART, 1); 1142 return; 1143 } 1144 } 1145 #endif /* BTUARTCONSOLE */ 1146 1147 #ifdef HWUARTCONSOLE 1148 #ifdef KGDB 1149 if (strcmp(kgdb_devname, "hwuart") == 0) { 1150 /* port is reserved for kgdb */ 1151 } else 1152 #endif 1153 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1154 if (console[0] == '\0' || strcasecmp(console, "hwuart") == 0) 1155 #endif 1156 { 1157 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_HWUART_BASE, 1158 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1159 if (rv == 0) { 1160 pxa2x0_clkman_config(CKEN_HWUART, 1); 1161 return; 1162 } 1163 } 1164 #endif /* HWUARTCONSOLE */ 1165 1166 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1167 1168 if (comcnattach(&omap_a4x_bs_tag, CONSADDR, comcnspeed, 1169 OMAP_COM_FREQ, COM_TYPE_NORMAL, comcnmode) == 0) 1170 return; 1171 1172 #endif /* GUMSTIX or OVERO */ 1173 1174 #endif /* NCOM */ 1175 1176 #if NLCD > 0 1177 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1178 if (console[0] == '\0' || strcasecmp(console, "lcd") == 0) 1179 #endif 1180 { 1181 gxlcd_cnattach(); 1182 } 1183 #endif 1184 } 1185 1186 #ifdef KGDB 1187 static void 1188 kgdb_port_init(void) 1189 { 1190 #if (NCOM > 0) && defined(COM_PXA2X0) 1191 paddr_t paddr = 0; 1192 int cken = 0; 1193 1194 if (0 == strcmp(kgdb_devname, "ffuart")) { 1195 paddr = PXA2X0_FFUART_BASE; 1196 cken = CKEN_FFUART; 1197 } else if (0 == strcmp(kgdb_devname, "stuart")) { 1198 paddr = PXA2X0_STUART_BASE; 1199 cken = CKEN_STUART; 1200 } else if (0 == strcmp(kgdb_devname, "btuart")) { 1201 paddr = PXA2X0_BTUART_BASE; 1202 cken = CKEN_BTUART; 1203 } else if (0 == strcmp(kgdb_devname, "hwuart")) { 1204 paddr = PXA2X0_HWUART_BASE; 1205 cken = CKEN_HWUART; 1206 } 1207 1208 if (paddr && 1209 0 == com_kgdb_attach(&pxa2x0_a4x_bs_tag, paddr, 1210 kgdb_devrate, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comkgdbmode)) { 1211 1212 pxa2x0_clkman_config(cken, 1); 1213 } 1214 1215 #endif 1216 } 1217 #endif 1218 1219 static void 1220 gumstix_device_register(device_t dev, void *aux) 1221 { 1222 prop_dictionary_t dict = device_properties(dev); 1223 1224 if (device_is_a(dev, "arma9tmr") || 1225 device_is_a(dev, "a9wdt")) { 1226 /* 1227 * We need to tell the A9 Global/Watchdog Timer 1228 * what frequency it runs at. 1229 */ 1230 1231 /* 1232 * This clock always runs at (arm_clk div 2) and only goes 1233 * to timers that are part of the A9 MP core subsystem. 1234 */ 1235 prop_dictionary_set_uint32(dict, "frequency", 1236 curcpu()->ci_data.cpu_cc_freq / 2); 1237 } 1238 if (device_is_a(dev, "armperiph")) { 1239 if (device_is_a(device_parent(dev), "mainbus")) { 1240 #if defined(OMAP2) 1241 /* 1242 * XXX KLUDGE ALERT XXX 1243 * The iot mainbus supplies is completely wrong since 1244 * it scales addresses by 2. The simpliest remedy is 1245 * to replace with our bus space used for the armcore 1246 * registers (which armperiph uses). 1247 */ 1248 struct mainbus_attach_args * const mb = aux; 1249 mb->mb_iot = &omap_bs_tag; 1250 #endif 1251 } 1252 } 1253 if (device_is_a(dev, "ehci")) { 1254 #if defined(OVERO) 1255 prop_dictionary_set_uint16(dict, "nports", 2); 1256 prop_dictionary_set_bool(dict, "phy-reset", true); 1257 prop_dictionary_set_cstring(dict, "port0-mode", "none"); 1258 prop_dictionary_set_int16(dict, "port0-gpio", -1); 1259 prop_dictionary_set_cstring(dict, "port1-mode", "phy"); 1260 prop_dictionary_set_int16(dict, "port1-gpio", 183); 1261 prop_dictionary_set_bool(dict, "port1-gpioval", true); 1262 #elif defined(DUOVERO) 1263 prop_dictionary_set_uint16(dict, "nports", 1); 1264 prop_dictionary_set_bool(dict, "phy-reset", true); 1265 prop_dictionary_set_cstring(dict, "port0-mode", "phy"); 1266 prop_dictionary_set_int16(dict, "port0-gpio", 62); 1267 prop_dictionary_set_bool(dict, "port0-gpioval", false); 1268 prop_dictionary_set_bool(dict, "port0-extclk", true); 1269 #endif 1270 prop_dictionary_set_uint16(dict, "dpll5-m", 443); 1271 prop_dictionary_set_uint16(dict, "dpll5-n", 11); 1272 prop_dictionary_set_uint16(dict, "dpll5-m2", 4); 1273 } 1274 if (device_is_a(dev, "ohci")) { 1275 if (prop_dictionary_set_bool(dict, 1276 "Ganged-power-mask-on-port1", 1) == false) { 1277 printf("WARNING: unable to set power-mask for port1" 1278 " property for %s\n", device_xname(dev)); 1279 } 1280 if (prop_dictionary_set_bool(dict, 1281 "Ganged-power-mask-on-port2", 1) == false) { 1282 printf("WARNING: unable to set power-mask for port2" 1283 " property for %s\n", device_xname(dev)); 1284 } 1285 if (prop_dictionary_set_bool(dict, 1286 "Ganged-power-mask-on-port3", 1) == false) { 1287 printf("WARNING: unable to set power-mask for port3" 1288 " property for %s\n", device_xname(dev)); 1289 } 1290 } 1291 if (device_is_a(dev, "omapmputmr")) { 1292 struct obio_attach_args *obio = aux; 1293 1294 switch (obio->obio_addr) { 1295 case 0x49032000: /* GPTIMER2 */ 1296 case 0x49034000: /* GPTIMER3 */ 1297 case 0x49036000: /* GPTIMER4 */ 1298 case 0x49038000: /* GPTIMER5 */ 1299 case 0x4903a000: /* GPTIMER6 */ 1300 case 0x4903c000: /* GPTIMER7 */ 1301 case 0x4903e000: /* GPTIMER8 */ 1302 case 0x49040000: /* GPTIMER9 */ 1303 #if defined(OVERO) 1304 { 1305 /* Ensure enable PRCM.CM_[FI]CLKEN_PER[3:10]. */ 1306 const int en = 1307 1 << (((obio->obio_addr >> 13) & 0x3f) - 0x16); 1308 1309 ioreg_write(OVERO_L4_CORE_VBASE + 0x5000, 1310 ioreg_read(OVERO_L4_CORE_VBASE + 0x5000) | en); 1311 ioreg_write(OVERO_L4_CORE_VBASE + 0x5010, 1312 ioreg_read(OVERO_L4_CORE_VBASE + 0x5010) | en); 1313 } 1314 #endif 1315 break; 1316 } 1317 } 1318 if (device_is_a(dev, "sdhc")) { 1319 bool dualvolt = false; 1320 1321 #if defined(OVERO) || defined(DUOVERO) 1322 if (device_is_a(device_parent(dev), "obio")) { 1323 struct obio_attach_args *obio = aux; 1324 1325 #if defined(OVERO) 1326 if (obio->obio_addr == SDMMC2_BASE_3530) 1327 dualvolt = true; 1328 #elif defined(DUOVERO) 1329 if (obio->obio_addr == SDMMC5_BASE_4430) 1330 dualvolt = true; 1331 #endif 1332 } 1333 #endif 1334 #if defined(PEPPER) 1335 if (device_is_a(device_parent(dev), "mainbus")) { 1336 struct mainbus_attach_args * const mb = aux; 1337 1338 if (mb->mb_iobase == SDMMC3_BASE_TIAM335X) 1339 dualvolt = true; 1340 } 1341 #endif 1342 prop_dictionary_set_bool(dict, "dual-volt", dualvolt); 1343 } 1344 if (device_is_a(dev, "tifb")) { 1345 prop_data_t panel_info; 1346 1347 panel_info = prop_data_create_data_nocopy(tifb_panel_info, 1348 sizeof(struct tifb_panel_info)); 1349 KASSERT(panel_info != NULL); 1350 prop_dictionary_set(dict, "panel-info", panel_info); 1351 prop_object_release(panel_info); 1352 1353 #if defined(OMAP2) 1354 /* enable LCD */ 1355 omap2_gpio_ctl(59, GPIO_PIN_OUTPUT); 1356 omap2_gpio_write(59, 0); /* reset */ 1357 delay(100); 1358 omap2_gpio_write(59, 1); 1359 #endif 1360 } 1361 if (device_is_a(dev, "tps65217pmic")) { 1362 #if defined(TI_AM335X) 1363 extern const char *mpu_supply; 1364 1365 mpu_supply = "DCDC3"; 1366 #endif 1367 1368 if (use_tps65217_wled) { 1369 prop_dictionary_set_int32(dict, "isel", 1); 1370 prop_dictionary_set_int32(dict, "fdim", 200); 1371 prop_dictionary_set_int32(dict, "brightness", 80); 1372 } 1373 } 1374 } 1375
Indexes created Thu Oct 30 16:09:53 GMT 2025