gumstix_machdep.c revision 1.67
1 /* $NetBSD: gumstix_machdep.c,v 1.67 2020/09/29 19:58:50 jmcneill Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2002, 2003, 2004, 2005 Genetec Corporation. 35 * All rights reserved. 36 * 37 * Written by Hiroyuki Bessho for Genetec Corporation. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. The name of Genetec Corporation may not be used to endorse or 48 * promote products derived from this software without specific prior 49 * written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 53 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 54 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 55 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 * 63 * Machine dependent functions for kernel setup for Genetec G4250EBX 64 * evaluation board. 65 * 66 * Based on iq80310_machhdep.c 67 */ 68 /* 69 * Copyright (c) 2001 Wasabi Systems, Inc. 70 * All rights reserved. 71 * 72 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 3. All advertising materials mentioning features or use of this software 83 * must display the following acknowledgement: 84 * This product includes software developed for the NetBSD Project by 85 * Wasabi Systems, Inc. 86 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 87 * or promote products derived from this software without specific prior 88 * written permission. 89 * 90 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 91 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 92 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 93 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 94 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 95 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 96 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 97 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 98 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 99 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 100 * POSSIBILITY OF SUCH DAMAGE. 101 */ 102 103 /* 104 * Copyright (c) 1997,1998 Mark Brinicombe. 105 * Copyright (c) 1997,1998 Causality Limited. 106 * All rights reserved. 107 * 108 * Redistribution and use in source and binary forms, with or without 109 * modification, are permitted provided that the following conditions 110 * are met: 111 * 1. Redistributions of source code must retain the above copyright 112 * notice, this list of conditions and the following disclaimer. 113 * 2. Redistributions in binary form must reproduce the above copyright 114 * notice, this list of conditions and the following disclaimer in the 115 * documentation and/or other materials provided with the distribution. 116 * 3. All advertising materials mentioning features or use of this software 117 * must display the following acknowledgement: 118 * This product includes software developed by Mark Brinicombe 119 * for the NetBSD Project. 120 * 4. The name of the company nor the name of the author may be used to 121 * endorse or promote products derived from this software without specific 122 * prior written permission. 123 * 124 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 125 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 126 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 127 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 128 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 129 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 130 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 131 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 132 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 133 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 134 * SUCH DAMAGE. 135 * 136 * Machine dependent functions for kernel setup for Intel IQ80310 evaluation 137 * boards using RedBoot firmware. 138 */ 139 140 #include "opt_arm_debug.h" 141 #include "opt_com.h" 142 #include "opt_console.h" 143 #include "opt_cputypes.h" 144 #include "opt_evbarm_boardtype.h" 145 #include "opt_gumstix.h" 146 #include "opt_kgdb.h" 147 #include "opt_multiprocessor.h" 148 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 149 #include "opt_omap.h" 150 151 #if defined(DUOVERO) 152 #include "arml2cc.h" 153 #endif 154 #include "prcm.h" 155 #endif 156 157 #include "arma9tmr.h" 158 #include "armgtmr.h" 159 160 #include <sys/param.h> 161 #include <sys/conf.h> 162 #include <sys/device.h> 163 #include <sys/exec.h> 164 #include <sys/kernel.h> 165 #include <sys/proc.h> 166 #include <sys/reboot.h> 167 #include <sys/systm.h> 168 #include <sys/termios.h> 169 #include <sys/bus.h> 170 #include <sys/cpu.h> 171 #include <sys/gpio.h> 172 173 #include <prop/proplib.h> 174 175 #include <uvm/uvm_extern.h> 176 177 #include <arm/mainbus/mainbus.h> /* don't reorder */ 178 179 #include <machine/autoconf.h> /* don't reorder */ 180 #include <machine/bootconfig.h> 181 #include <arm/locore.h> 182 183 #include <arm/arm32/machdep.h> 184 185 #include <arm/omap/omap2_obiovar.h> 186 #include <arm/omap/am335x_prcm.h> 187 #include <arm/omap/omap2_gpio.h> 188 #include <arm/omap/omap2_gpmcreg.h> 189 #include <arm/omap/omap2_prcm.h> 190 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 191 #include <arm/omap/omap2_reg.h> /* Must required "opt_omap.h" */ 192 #endif 193 #include <arm/omap/omap3_sdmmcreg.h> 194 #include <arm/omap/omap_var.h> 195 #include <arm/omap/omap_com.h> 196 #include <arm/omap/tifbvar.h> 197 198 #include <arm/xscale/pxa2x0reg.h> 199 #include <arm/xscale/pxa2x0var.h> 200 #include <arm/xscale/pxa2x0_gpio.h> 201 #include <evbarm/gumstix/gumstixreg.h> 202 #include <evbarm/gumstix/gumstixvar.h> 203 204 #include <arm/cortex/pl310_var.h> 205 #include <arm/cortex/pl310_reg.h> 206 #include <arm/cortex/scu_reg.h> 207 208 #include <arm/cortex/a9tmr_var.h> 209 210 #include <arm/cortex/gtmr_var.h> 211 212 #include <dev/cons.h> 213 214 #ifdef KGDB 215 #include <sys/kgdb.h> 216 #endif 217 218 #ifdef VERBOSE_INIT_ARM 219 #define VPRINTF(...) printf(__VA_ARGS__) 220 #else 221 #define VPRINTF(...) __nothing 222 #endif 223 224 /* 225 * The range 0xc1000000 - 0xfd000000 is available for kernel VM space 226 * Core-logic registers and I/O mappings occupy 227 * 228 * 0xfd000000 - 0xfd800000 on gumstix 229 * 0xc0000000 - 0xc0400000 on overo, duovero and pepper 230 */ 231 #ifndef KERNEL_VM_BASE 232 #define KERNEL_VM_BASE 0xc8000000 233 #endif 234 #define KERNEL_VM_SIZE 0x35000000 235 236 BootConfig bootconfig; /* Boot config storage */ 237 static char bootargs[MAX_BOOT_STRING]; 238 const size_t bootargs_len = sizeof(bootargs) - 1; /* without nul */ 239 char *boot_args = NULL; 240 241 uint32_t system_serial_high; 242 uint32_t system_serial_low; 243 244 /* Prototypes */ 245 #if defined(GUMSTIX) 246 static void read_system_serial(void); 247 #endif 248 #if defined(OMAP2) 249 static void omap_reset(void); 250 static void find_cpu_clock(void); 251 #endif 252 static void process_kernel_args(int, char *[]); 253 static void process_kernel_args_liner(char *); 254 #ifdef KGDB 255 static void kgdb_port_init(void); 256 #endif 257 static void gumstix_device_register(device_t, void *); 258 259 bs_protos(bs_notimpl); 260 261 #include "com.h" 262 #if NCOM > 0 263 #include <dev/ic/comreg.h> 264 #include <dev/ic/comvar.h> 265 #endif 266 267 #if defined(CPU_XSCALE) 268 #include "lcd.h" 269 #endif 270 271 #ifndef CONSPEED 272 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 273 #endif 274 #ifndef CONMODE 275 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 276 #endif 277 278 int comcnspeed = CONSPEED; 279 int comcnmode = CONMODE; 280 281 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 282 static char console[16]; 283 #endif 284 285 const struct tifb_panel_info *tifb_panel_info = NULL; 286 /* Use TPS65217 White LED Driver */ 287 bool use_tps65217_wled = false; 288 289 extern void gxio_config(void); 290 extern void gxio_config_expansion(char *); 291 292 293 static inline pd_entry_t * 294 read_ttb(void) 295 { 296 long ttb; 297 298 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); 299 300 return (pd_entry_t *)(ttb & ~((1<<14)-1)); 301 } 302 303 /* 304 * Static device mappings. These peripheral registers are mapped at 305 * fixed virtual addresses very early in initarm() so that we can use 306 * them while booting the kernel, and stay at the same address 307 * throughout whole kernel's life time. 308 * 309 * We use this table twice; once with bootstrap page table, and once 310 * with kernel's page table which we build up in initarm(). 311 * 312 * Since we map these registers into the bootstrap page table using 313 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 314 * registers segment-aligned and segment-rounded in order to avoid 315 * using the 2nd page tables. 316 */ 317 318 #define _A(a) ((a) & ~L1_S_OFFSET) 319 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 320 321 static const struct pmap_devmap gumstix_devmap[] = { 322 #if defined(GUMSTIX) 323 { 324 GUMSTIX_GPIO_VBASE, 325 _A(PXA2X0_GPIO_BASE), 326 _S(PXA250_GPIO_SIZE), 327 VM_PROT_READ | VM_PROT_WRITE, 328 PTE_NOCACHE, 329 }, 330 { 331 GUMSTIX_CLKMAN_VBASE, 332 _A(PXA2X0_CLKMAN_BASE), 333 _S(PXA2X0_CLKMAN_SIZE), 334 VM_PROT_READ | VM_PROT_WRITE, 335 PTE_NOCACHE, 336 }, 337 { 338 GUMSTIX_INTCTL_VBASE, 339 _A(PXA2X0_INTCTL_BASE), 340 _S(PXA2X0_INTCTL_SIZE), 341 VM_PROT_READ | VM_PROT_WRITE, 342 PTE_NOCACHE, 343 }, 344 { 345 GUMSTIX_FFUART_VBASE, 346 _A(PXA2X0_FFUART_BASE), 347 _S(4 * COM_NPORTS), 348 VM_PROT_READ | VM_PROT_WRITE, 349 PTE_NOCACHE, 350 }, 351 { 352 GUMSTIX_STUART_VBASE, 353 _A(PXA2X0_STUART_BASE), 354 _S(4 * COM_NPORTS), 355 VM_PROT_READ | VM_PROT_WRITE, 356 PTE_NOCACHE, 357 }, 358 { 359 GUMSTIX_BTUART_VBASE, 360 _A(PXA2X0_BTUART_BASE), 361 _S(4 * COM_NPORTS), 362 VM_PROT_READ | VM_PROT_WRITE, 363 PTE_NOCACHE, 364 }, 365 { 366 GUMSTIX_HWUART_VBASE, 367 _A(PXA2X0_HWUART_BASE), 368 _S(4 * COM_NPORTS), 369 VM_PROT_READ | VM_PROT_WRITE, 370 PTE_NOCACHE, 371 }, 372 { 373 GUMSTIX_LCDC_VBASE, 374 _A(PXA2X0_LCDC_BASE), 375 _S(4 * COM_NPORTS), 376 VM_PROT_READ | VM_PROT_WRITE, 377 PTE_NOCACHE, 378 }, 379 #elif defined(OVERO) 380 { /* SCM, PRCM */ 381 OVERO_L4_CORE_VBASE, 382 _A(OMAP3530_L4_CORE_BASE), 383 _S(L1_S_SIZE), /* No need 16MB. Use only first 1MB */ 384 VM_PROT_READ | VM_PROT_WRITE, 385 PTE_NOCACHE 386 }, 387 { /* Console, GPIO[2-6] */ 388 OVERO_L4_PERIPHERAL_VBASE, 389 _A(OMAP3530_L4_PERIPHERAL_BASE), 390 _S(OMAP3530_L4_PERIPHERAL_SIZE), 391 VM_PROT_READ | VM_PROT_WRITE, 392 PTE_NOCACHE 393 }, 394 { /* GPIO1 */ 395 OVERO_L4_WAKEUP_VBASE, 396 _A(OMAP3530_L4_WAKEUP_BASE), 397 _S(OMAP3530_L4_WAKEUP_SIZE), 398 VM_PROT_READ | VM_PROT_WRITE, 399 PTE_NOCACHE 400 }, 401 { 402 OVERO_GPMC_VBASE, 403 _A(GPMC_BASE), 404 _S(GPMC_SIZE), 405 VM_PROT_READ | VM_PROT_WRITE, 406 PTE_NOCACHE 407 }, 408 { 409 OVERO_SRDC_VBASE, 410 _A(OMAP3530_SDRC_BASE), 411 _S(OMAP3530_SDRC_SIZE), 412 VM_PROT_READ | VM_PROT_WRITE, 413 PTE_NOCACHE 414 }, 415 #elif defined(DUOVERO) 416 { 417 DUOVERO_L4_CM_VBASE, 418 _A(OMAP4430_L4_CORE_BASE + 0x100000), 419 _S(L1_S_SIZE), 420 VM_PROT_READ | VM_PROT_WRITE, 421 PTE_NOCACHE 422 }, 423 { /* Console, SCU, L2CC, GPIO[2-6] */ 424 DUOVERO_L4_PERIPHERAL_VBASE, 425 _A(OMAP4430_L4_PERIPHERAL_BASE), 426 _S(L1_S_SIZE * 3), 427 VM_PROT_READ | VM_PROT_WRITE, 428 PTE_NOCACHE 429 }, 430 { /* PRCM, GPIO1 */ 431 DUOVERO_L4_WAKEUP_VBASE, 432 _A(OMAP4430_L4_WAKEUP_BASE), 433 _S(OMAP4430_L4_WAKEUP_SIZE), 434 VM_PROT_READ | VM_PROT_WRITE, 435 PTE_NOCACHE 436 }, 437 { 438 DUOVERO_GPMC_VBASE, 439 _A(GPMC_BASE), 440 _S(GPMC_SIZE), 441 VM_PROT_READ | VM_PROT_WRITE, 442 PTE_NOCACHE 443 }, 444 { 445 DUOVERO_DMM_VBASE, 446 _A(OMAP4430_DMM_BASE), 447 _S(OMAP4430_DMM_SIZE), 448 VM_PROT_READ | VM_PROT_WRITE, 449 PTE_NOCACHE 450 }, 451 #elif defined(PEPPER) 452 { 453 /* CM, Control Module, GPIO0, Console */ 454 PEPPER_PRCM_VBASE, 455 _A(OMAP2_CM_BASE), 456 _S(L1_S_SIZE), 457 VM_PROT_READ | VM_PROT_WRITE, 458 PTE_NOCACHE 459 }, 460 { 461 /* GPIO[1-3] */ 462 PEPPER_L4_PERIPHERAL_VBASE, 463 _A(TI_AM335X_L4_PERIPHERAL_BASE), 464 _S(L1_S_SIZE), 465 VM_PROT_READ | VM_PROT_WRITE, 466 PTE_NOCACHE 467 }, 468 #endif 469 { 0, 0, 0, 0, 0 } 470 }; 471 472 #undef _A 473 #undef _S 474 475 #ifdef MULTIPROCESSOR 476 void gumstix_cpu_hatch(struct cpu_info *); 477 478 void 479 gumstix_cpu_hatch(struct cpu_info *ci) 480 { 481 #if NARMA9TMR > 0 482 if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) { 483 a9tmr_init_cpu_clock(ci); 484 } 485 #endif 486 #if NARMGTMR > 0 487 if (CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid) || 488 CPU_ID_CORTEX_A15_P(curcpu()->ci_arm_cpuid)) { 489 gtmr_init_cpu_clock(ci); 490 } 491 #endif 492 } 493 #endif 494 495 496 static void 497 gumstix_mpstart(void) 498 { 499 #if defined(MULTIPROCESSOR) 500 const bus_space_tag_t iot = &omap_bs_tag; 501 int error; 502 503 if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) { 504 bus_space_handle_t scu_ioh; 505 error = bus_space_map(iot, OMAP4_SCU_BASE, OMAP4_SCU_SIZE, 0, &scu_ioh); 506 if (error) 507 panic("Could't map OMAP4_SCU_BASE"); 508 509 /* 510 * Invalidate all SCU cache tags. That is, for all cores (0-3) 511 */ 512 bus_space_write_4(iot, scu_ioh, SCU_INV_ALL_REG, 0xffff); 513 514 uint32_t diagctl = bus_space_read_4(iot, scu_ioh, SCU_DIAG_CONTROL); 515 diagctl |= SCU_DIAG_DISABLE_MIGBIT; 516 bus_space_write_4(iot, scu_ioh, SCU_DIAG_CONTROL, diagctl); 517 518 uint32_t scu_ctl = bus_space_read_4(iot, scu_ioh, SCU_CTL); 519 scu_ctl |= SCU_CTL_SCU_ENA; 520 bus_space_write_4(iot, scu_ioh, SCU_CTL, scu_ctl); 521 522 armv7_dcache_wbinv_all(); 523 } 524 525 bus_space_handle_t wugen_ioh; 526 error = bus_space_map(iot, OMAP4_WUGEN_BASE, OMAP4_WUGEN_SIZE, 0, 527 &wugen_ioh); 528 if (error) 529 panic("Couldn't map OMAP4_WUGEN_BASE"); 530 const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart); 531 532 bus_space_write_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT1, mpstart); 533 534 for (size_t i = 1; i < arm_cpu_max; i++) { 535 uint32_t boot = bus_space_read_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT0); 536 boot |= __SHIFTIN(0xf, i * 4); 537 bus_space_write_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT0, boot); 538 } 539 540 arm_dsb(); 541 __asm __volatile("sev" ::: "memory"); 542 543 for (int loop = 0; loop < 16; loop++) { 544 VPRINTF("%u hatched %#x\n", loop, arm_cpu_hatched); 545 if (arm_cpu_hatched == __BITS(arm_cpu_max - 1, 1)) 546 break; 547 int timo = 1500000; 548 while (arm_cpu_hatched != __BITS(arm_cpu_max - 1, 1)) 549 if (--timo == 0) 550 break; 551 } 552 for (size_t i = 1; i < arm_cpu_max; i++) { 553 if (cpu_hatched_p(i)) { 554 printf("%s: warning: cpu%zu failed to hatch\n", 555 __func__, i); 556 } 557 } 558 559 VPRINTF(" (%u cpu%s, hatched %#x)", 560 arm_cpu_max, arm_cpu_max ? "s" : "", 561 arm_cpu_hatched); 562 #endif 563 } 564 565 #if defined(CPU_CORTEX) 566 /* filled in before cleaning bss. keep in .data */ 567 u_int uboot_args[4] __attribute__((__section__(".data"))); 568 #else 569 extern uint32_t *uboot_args; 570 #endif 571 572 /* 573 * vaddr_t initarm(...) 574 * 575 * Initial entry point on startup. This gets called before main() is 576 * entered. 577 * It should be responsible for setting up everything that must be 578 * in place when main is called. 579 * This includes 580 * Taking a copy of the boot configuration structure. 581 * Initialising the physical console so characters can be printed. 582 * Setting up page tables for the kernel 583 * Relocating the kernel to the bottom of physical memory 584 */ 585 vaddr_t 586 initarm(void *arg) 587 { 588 extern char KERNEL_BASE_phys[]; 589 uint32_t ram_size = 0x400000; 590 enum { r0 = 0, r1 = 1, r2 = 2, r3 = 3 }; /* args from u-boot */ 591 592 #if defined(OVERO) || defined(DUOVERO) /* || defined(PEPPER) */ 593 const bus_space_tag_t iot = &omap_bs_tag; 594 #endif 595 596 #if defined(CPU_XSCALE) 597 598 /* 599 * We mapped PA == VA in gumstix_start.S. 600 * Also mapped SDRAM to KERNEL_BASE first 64Mbyte only with cachable. 601 * 602 * Gumstix (basix, connex, verdex, verdex-pro): 603 * Physical Address Range Description 604 * ----------------------- ---------------------------------- 605 * 0x00000000 - 0x00ffffff flash Memory (16MB or 4MB) 606 * 0x40000000 - 0x480fffff Processor Registers 607 * 0xa0000000 - 0xa3ffffff SDRAM Bank 0 (64MB or 128MB) 608 * 0xc0000000 - 0xc3ffffff KERNEL_BASE 609 */ 610 extern vaddr_t xscale_cache_clean_addr; 611 xscale_cache_clean_addr = 0xff000000U; 612 613 cpu_reset_address = NULL; 614 #elif defined(OMAP2) 615 cpu_reset_address = omap_reset; 616 617 find_cpu_clock(); 618 #endif 619 620 /* 621 * Heads up ... Setup the CPU / MMU / TLB functions 622 */ 623 if (set_cpufuncs()) 624 panic("cpu not recognized!"); 625 626 /* map some peripheral registers at static I/O area */ 627 pmap_devmap_bootstrap((vaddr_t)read_ttb(), gumstix_devmap); 628 629 #if defined(CPU_XSCALE) 630 /* start 32.768kHz OSC */ 631 ioreg_write(GUMSTIX_CLKMAN_VBASE + CLKMAN_OSCC, OSCC_OON); 632 633 /* Get ready for splfoo() */ 634 pxa2x0_intr_bootstrap(GUMSTIX_INTCTL_VBASE); 635 636 /* setup GPIO for {FF,ST,HW}UART. */ 637 pxa2x0_gpio_bootstrap(GUMSTIX_GPIO_VBASE); 638 639 pxa2x0_clkman_bootstrap(GUMSTIX_CLKMAN_VBASE); 640 #endif 641 642 643 #if defined(OVERO) 644 645 #define OMAP3530_SRDC_MCFG_p(p) (0x80 + ((p) * 0x30)) 646 #define OMAP3530_SRDC_MCFG_RAMSIZE __BITS(17,8) 647 648 bus_space_handle_t sdrcioh; 649 if (bus_space_map(iot, OMAP3530_SDRC_BASE, OMAP3530_SDRC_SIZE, 650 0, &sdrcioh) != 0) 651 panic("OMAP_SDRC_BASE map failed\n"); 652 653 ram_size = 0; 654 for (u_int p = 0; p < 2; p++) { 655 uint32_t mcfg = bus_space_read_4(iot, sdrcioh, 656 OMAP3530_SRDC_MCFG_p(p)); 657 ram_size += __SHIFTOUT(mcfg, OMAP3530_SRDC_MCFG_RAMSIZE) * 658 (2 * 1024 * 1024); 659 } 660 661 #elif defined(DUOVERO) 662 663 #define OMAP4_DMM_LISA_MAP_i(i) (0x40 + ((i) * 0x4)) 664 #define OMAP4_DMM_LISA_SYS_ADDR __BITS(31,24) 665 #define OMAP4_DMM_LISA_SYS_SIZE __BITS(22,20) 666 #define OMAP4_DMM_LISA_SDRC_ADDRSPC __BITS(17,16) 667 668 bus_space_handle_t dmmioh; 669 if (bus_space_map(iot, OMAP4430_DMM_BASE, OMAP4430_DMM_SIZE, 0, 670 &dmmioh) != 0) 671 panic("OMAP4_DMM_BASE map failed\n"); 672 673 ram_size = 0; 674 for (u_int i = 0; i < 4; i++) { 675 const uint32_t lisa = bus_space_read_4(iot, dmmioh, 676 OMAP4_DMM_LISA_MAP_i(i)); 677 678 const uint32_t sys_addr = 679 __SHIFTOUT(lisa, OMAP4_DMM_LISA_SYS_ADDR); 680 /* skip non-physical */ 681 if ((sys_addr & 0x80) != 0) 682 continue; 683 684 const uint32_t sdrc_addrspc = 685 __SHIFTOUT(lisa, OMAP4_DMM_LISA_SDRC_ADDRSPC); 686 /* Skip reserced areas */ 687 if (sdrc_addrspc == 2) 688 continue; 689 690 const uint32_t sys_size = 691 __SHIFTOUT(lisa, OMAP4_DMM_LISA_SYS_SIZE); 692 ram_size += (16 * 1024 * 1024) << sys_size; 693 } 694 695 696 #endif 697 698 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 699 700 /* configure MUX, GPIO and CLK. */ 701 gxio_config(); 702 703 #ifndef GUMSTIX_NETBSD_ARGS_CONSOLE 704 consinit(); 705 #endif 706 #ifdef KGDB 707 kgdb_port_init(); 708 #endif 709 710 /* 711 * Examine the boot args string for options we need to know about 712 * now. 713 */ 714 #if defined(GUMSTIX) 715 #define SDRAM_START 0xa0000000UL 716 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 717 #define SDRAM_START 0x80000000UL 718 #endif 719 if (uboot_args[r0] < SDRAM_START || 720 uboot_args[r0] >= SDRAM_START + ram_size) 721 /* Maybe r0 is 'argc'. We are booted by command 'go'. */ 722 process_kernel_args(uboot_args[r0], (char **)uboot_args[r1]); 723 else 724 /* 725 * Maybe r3 is 'boot args string' of 'bootm'. This string is 726 * linely. 727 */ 728 process_kernel_args_liner((char *)uboot_args[r3]); 729 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 730 consinit(); 731 #endif 732 733 /* Talk to the user */ 734 #define BDSTR(s) _BDSTR(s) 735 #define _BDSTR(s) #s 736 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 737 738 /* Read system serial */ 739 #if defined(GUMSTIX) 740 read_system_serial(); 741 #endif 742 743 VPRINTF("initarm: Configuring system ...\n"); 744 745 #if defined(OMAP_4430) 746 bus_space_handle_t ioh; 747 748 #if NARML2CC > 0 749 /* 750 * Initialize L2-Cache parameters 751 */ 752 753 if (bus_space_map(iot, OMAP4_L2CC_BASE, OMAP4_L2CC_SIZE, 0, &ioh) != 0) 754 panic("OMAP4_L2CC_BASE map failed\n"); 755 arml2cc_init(iot, ioh, 0); 756 #endif 757 758 #ifdef MULTIPROCESSOR 759 if (bus_space_map(iot, OMAP4_SCU_BASE, SCU_SIZE, 0, &ioh) != 0) 760 panic("OMAP4_SCU_BASE map failed\n"); 761 arm_cpu_max = 762 1 + (bus_space_read_4(iot, ioh, SCU_CFG) & SCU_CFG_CPUMAX); 763 #endif 764 #endif 765 766 /* Fake bootconfig structure for the benefit of pmap.c */ 767 /* XXX must make the memory description h/w independent */ 768 bootconfig.dramblocks = 1; 769 bootconfig.dram[0].address = SDRAM_START; 770 bootconfig.dram[0].pages = ram_size / PAGE_SIZE; 771 772 KASSERT(ram_size <= KERNEL_VM_BASE - KERNEL_BASE); 773 774 arm32_bootmem_init(bootconfig.dram[0].address, ram_size, 775 (uintptr_t) KERNEL_BASE_phys); 776 arm32_kernel_vm_init(KERNEL_VM_BASE, 777 #if defined(CPU_XSCALE) 778 ARM_VECTORS_LOW, 779 #elif defined(CPU_CORTEX) 780 ARM_VECTORS_HIGH, 781 #endif 782 0, gumstix_devmap, true); 783 784 evbarm_device_register = gumstix_device_register; 785 786 vaddr_t sp = initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 787 788 /* 789 * initarm_common flushes cache if required before AP start 790 */ 791 gumstix_mpstart(); 792 793 return sp; 794 } 795 796 #if defined(GUMSTIX) 797 static void 798 read_system_serial(void) 799 { 800 #define GUMSTIX_SYSTEM_SERIAL_ADDR 0 801 #define GUMSTIX_SYSTEM_SERIAL_SIZE 8 802 #define FLASH_OFFSET_INTEL_PROTECTION 0x81 803 #define FLASH_OFFSET_USER_PROTECTION 0x85 804 #define FLASH_CMD_READ_ID 0x90 805 #define FLASH_CMD_RESET 0xff 806 int i; 807 char system_serial[GUMSTIX_SYSTEM_SERIAL_SIZE], *src; 808 char x; 809 810 src = (char *)(FLASH_OFFSET_USER_PROTECTION * 2 /*word*/); 811 *(volatile uint16_t *)0 = FLASH_CMD_READ_ID; 812 memcpy(system_serial, 813 src + GUMSTIX_SYSTEM_SERIAL_ADDR, sizeof (system_serial)); 814 *(volatile uint16_t *)0 = FLASH_CMD_RESET; 815 816 for (i = 1, x = system_serial[0]; i < sizeof (system_serial); i++) 817 x &= system_serial[i]; 818 if (x == 0xff) { 819 src = (char *)(FLASH_OFFSET_INTEL_PROTECTION * 2 /*word*/); 820 *(volatile uint16_t *)0 = FLASH_CMD_READ_ID; 821 memcpy(system_serial, 822 src + GUMSTIX_SYSTEM_SERIAL_ADDR, sizeof (system_serial)); 823 *(volatile uint16_t *)0 = FLASH_CMD_RESET; 824 825 /* 826 * XXXX: Don't need ??? 827 * gumstix_serial_hash(system_serial); 828 */ 829 } 830 system_serial_high = system_serial[0] << 24 | system_serial[1] << 16 | 831 system_serial[2] << 8 | system_serial[3]; 832 system_serial_low = system_serial[4] << 24 | system_serial[5] << 16 | 833 system_serial[6] << 8 | system_serial[7]; 834 835 printf("system serial: 0x"); 836 for (i = 0; i < sizeof (system_serial); i++) 837 printf("%02x", system_serial[i]); 838 printf("\n"); 839 } 840 #endif 841 842 #if defined(OMAP2) 843 static void 844 omap_reset(void) 845 { 846 847 #if defined(TI_AM335X) 848 vaddr_t prm_base = (PEPPER_PRCM_VBASE + AM335X_PRCM_PRM_DEVICE); 849 850 *(volatile uint32_t *)(prm_base + PRM_RSTCTRL) = RST_GLOBAL_WARM_SW; 851 #elif defined(OMAP_4430) 852 *(volatile uint32_t *)(DUOVERO_L4_WAKEUP_VBASE + OMAP4_PRM_RSTCTRL) = 853 OMAP4_PRM_RSTCTRL_WARM; 854 #endif 855 856 #if NPRCM > 0 857 prcm_cold_reset(); 858 #endif 859 } 860 861 static void 862 find_cpu_clock(void) 863 { 864 const vaddr_t prm_base __unused = OMAP2_PRM_BASE; 865 const vaddr_t cm_base = OMAP2_CM_BASE; 866 867 #if defined(OMAP_3530) 868 869 const uint32_t prm_clksel = 870 *(volatile uint32_t *)(prm_base + PLL_MOD + OMAP3_PRM_CLKSEL); 871 static const uint32_t prm_clksel_freqs[] = OMAP3_PRM_CLKSEL_FREQS; 872 const uint32_t sys_clk = 873 prm_clksel_freqs[__SHIFTOUT(prm_clksel, OMAP3_PRM_CLKSEL_CLKIN)]; 874 const uint32_t dpll1 = 875 *(volatile uint32_t *)(cm_base + OMAP3_CM_CLKSEL1_PLL_MPU); 876 const uint32_t dpll2 = 877 *(volatile uint32_t *)(cm_base + OMAP3_CM_CLKSEL2_PLL_MPU); 878 const uint32_t m = 879 __SHIFTOUT(dpll1, OMAP3_CM_CLKSEL1_PLL_MPU_DPLL_MULT); 880 const uint32_t n = __SHIFTOUT(dpll1, OMAP3_CM_CLKSEL1_PLL_MPU_DPLL_DIV); 881 const uint32_t m2 = 882 __SHIFTOUT(dpll2, OMAP3_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV); 883 884 /* 885 * MPU_CLK supplies ARM_FCLK which is twice the CPU frequency. 886 */ 887 curcpu()->ci_data.cpu_cc_freq = 888 ((sys_clk * m) / ((n + 1) * m2 * 2)) * OMAP3_PRM_CLKSEL_MULT; 889 omap_sys_clk = sys_clk * OMAP3_PRM_CLKSEL_MULT; 890 891 #elif defined(OMAP_4430) 892 893 const uint32_t prm_clksel = 894 *(volatile uint32_t *)(prm_base + OMAP4_CM_SYS_CLKSEL); 895 static const uint32_t cm_clksel_freqs[] = OMAP4_CM_CLKSEL_FREQS; 896 const uint32_t sys_clk = 897 cm_clksel_freqs[__SHIFTOUT(prm_clksel, OMAP4_CM_SYS_CLKSEL_CLKIN)]; 898 const uint32_t dpll1 = 899 *(volatile uint32_t *)(cm_base + OMAP4_CM_CLKSEL_DPLL_MPU); 900 const uint32_t dpll2 = 901 *(volatile uint32_t *)(cm_base + OMAP4_CM_DIV_M2_DPLL_MPU); 902 const uint32_t m = 903 __SHIFTOUT(dpll1, OMAP4_CM_CLKSEL_DPLL_MPU_DPLL_MULT); 904 const uint32_t n = __SHIFTOUT(dpll1, OMAP4_CM_CLKSEL_DPLL_MPU_DPLL_DIV); 905 const uint32_t m2 = 906 __SHIFTOUT(dpll2, OMAP4_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIV); 907 908 /* 909 * MPU_CLK supplies ARM_FCLK which is twice the CPU frequency. 910 */ 911 curcpu()->ci_data.cpu_cc_freq = 912 ((sys_clk * 2 * m) / ((n + 1) * m2)) * OMAP4_CM_CLKSEL_MULT / 2; 913 omap_sys_clk = sys_clk * OMAP4_CM_CLKSEL_MULT; 914 915 #elif defined(TI_AM335X) 916 917 prcm_bootstrap(cm_base); 918 am335x_sys_clk(TI_AM335X_CTLMOD_BASE); 919 am335x_cpu_clk(); 920 921 #endif 922 } 923 #endif 924 925 #ifdef GUMSTIX_NETBSD_ARGS_BUSHEADER 926 static const char busheader_name[] = "busheader="; 927 #endif 928 #if defined(GUMSTIX_NETBSD_ARGS_BUSHEADER) || \ 929 defined(GUMSTIX_NETBSD_ARGS_EXPANSION) 930 static const char expansion_name[] = "expansion="; 931 #endif 932 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 933 static const char console_name[] = "console="; 934 #endif 935 static void 936 process_kernel_args(int argc, char *argv[]) 937 { 938 int gxio_configured = 0, i, j; 939 940 boothowto = 0; 941 942 for (i = 1, j = 0; i < argc; i++) { 943 #ifdef GUMSTIX_NETBSD_ARGS_BUSHEADER 944 if (!strncmp(argv[i], busheader_name, strlen(busheader_name))) { 945 /* Configure for GPIOs of busheader side */ 946 gxio_config_expansion(argv[i] + strlen(busheader_name)); 947 gxio_configured = 1; 948 continue; 949 } 950 #endif 951 #if defined(GUMSTIX_NETBSD_ARGS_BUSHEADER) || \ 952 defined(GUMSTIX_NETBSD_ARGS_EXPANSION) 953 if (!strncmp(argv[i], expansion_name, strlen(expansion_name))) { 954 /* Configure expansion */ 955 gxio_config_expansion(argv[i] + strlen(expansion_name)); 956 gxio_configured = 1; 957 continue; 958 } 959 #endif 960 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 961 if (!strncmp(argv[i], console_name, strlen(console_name))) { 962 strncpy(console, argv[i] + strlen(console_name), 963 sizeof(console)); 964 consinit(); 965 } 966 #endif 967 if (j == bootargs_len) { 968 *(bootargs + j) = '\0'; 969 continue; 970 } 971 if (j != 0) 972 *(bootargs + j++) = ' '; 973 strncpy(bootargs + j, argv[i], bootargs_len - j); 974 bootargs[bootargs_len] = '\0'; 975 j += strlen(argv[i]); 976 } 977 boot_args = bootargs; 978 979 parse_mi_bootargs(boot_args); 980 981 if (!gxio_configured) 982 gxio_config_expansion(NULL); 983 } 984 985 static void 986 process_kernel_args_liner(char *args) 987 { 988 int i = 0; 989 char *p = NULL; 990 991 boothowto = 0; 992 993 strncpy(bootargs, args, sizeof(bootargs)); 994 #if defined(GUMSTIX_NETBSD_ARGS_BUSHEADER) || \ 995 defined(GUMSTIX_NETBSD_ARGS_EXPANSION) 996 { 997 char *q; 998 999 if ((p = strstr(bootargs, expansion_name))) 1000 q = p + strlen(expansion_name); 1001 #ifdef GUMSTIX_NETBSD_ARGS_BUSHEADER 1002 else if ((p = strstr(bootargs, busheader_name))) 1003 q = p + strlen(busheader_name); 1004 #endif 1005 if (p) { 1006 char expansion[256], c; 1007 1008 i = 0; 1009 do { 1010 c = *(q + i); 1011 if (c == ' ') 1012 c = '\0'; 1013 expansion[i++] = c; 1014 } while (c != '\0' && i < sizeof(expansion)); 1015 gxio_config_expansion(expansion); 1016 strcpy(p, q + i); 1017 } 1018 } 1019 #endif 1020 if (p == NULL) 1021 gxio_config_expansion(NULL); 1022 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 1023 p = strstr(bootargs, console_name); 1024 if (p != NULL) { 1025 char c; 1026 1027 i = 0; 1028 do { 1029 c = *(p + strlen(console_name) + i); 1030 if (c == ' ') 1031 c = '\0'; 1032 console[i++] = c; 1033 } while (c != '\0' && i < sizeof(console)); 1034 consinit(); 1035 strcpy(p, p + strlen(console_name) + i); 1036 } 1037 #endif 1038 boot_args = bootargs; 1039 1040 parse_mi_bootargs(boot_args); 1041 } 1042 1043 #ifdef KGDB 1044 #ifndef KGDB_DEVNAME 1045 #define KGDB_DEVNAME "ffuart" 1046 #endif 1047 const char kgdb_devname[] = KGDB_DEVNAME; 1048 1049 #ifndef KGDB_DEVRATE 1050 #define KGDB_DEVRATE CONSPEED 1051 #endif 1052 int kgdb_devrate = KGDB_DEVRATE; 1053 1054 #if (NCOM > 0) 1055 #ifndef KGDB_DEVMODE 1056 #define KGDB_DEVMODE CONMODE 1057 #endif 1058 int comkgdbmode = KGDB_DEVMODE; 1059 #endif /* NCOM */ 1060 1061 #endif /* KGDB */ 1062 1063 1064 void 1065 consinit(void) 1066 { 1067 static int consinit_called = 0; 1068 1069 if (consinit_called != 0) 1070 return; 1071 1072 consinit_called = 1; 1073 1074 #if NCOM > 0 1075 1076 #ifdef GUMSTIX_NETBSD_ARGS_CONSOLE 1077 /* Maybe passed Linux's bootargs 'console=ttyS?,<speed>...' */ 1078 if (strncmp(console, "ttyS", 4) == 0 && console[5] == ',') { 1079 int i; 1080 1081 comcnspeed = 0; 1082 for (i = 6; i < strlen(console) && isdigit(console[i]); i++) 1083 comcnspeed = comcnspeed * 10 + (console[i] - '0'); 1084 } 1085 #endif 1086 1087 #if defined(GUMSTIX) 1088 1089 #ifdef FFUARTCONSOLE 1090 #ifdef KGDB 1091 if (strcmp(kgdb_devname, "ffuart") == 0){ 1092 /* port is reserved for kgdb */ 1093 } else 1094 #endif 1095 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1096 if (console[0] == '\0' || strcasecmp(console, "ffuart") == 0 || 1097 strncmp(console, "ttyS0,", 6) == 0) 1098 #endif 1099 { 1100 int rv; 1101 1102 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_FFUART_BASE, 1103 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1104 if (rv == 0) { 1105 pxa2x0_clkman_config(CKEN_FFUART, 1); 1106 return; 1107 } 1108 } 1109 #endif /* FFUARTCONSOLE */ 1110 1111 #ifdef STUARTCONSOLE 1112 #ifdef KGDB 1113 if (strcmp(kgdb_devname, "stuart") == 0) { 1114 /* port is reserved for kgdb */ 1115 } else 1116 #endif 1117 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1118 if (console[0] == '\0' || strcasecmp(console, "stuart") == 0) 1119 #endif 1120 { 1121 int rv; 1122 1123 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_STUART_BASE, 1124 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1125 if (rv == 0) { 1126 pxa2x0_clkman_config(CKEN_STUART, 1); 1127 return; 1128 } 1129 } 1130 #endif /* STUARTCONSOLE */ 1131 1132 #ifdef BTUARTCONSOLE 1133 #ifdef KGDB 1134 if (strcmp(kgdb_devname, "btuart") == 0) { 1135 /* port is reserved for kgdb */ 1136 } else 1137 #endif 1138 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1139 if (console[0] == '\0' || strcasecmp(console, "btuart") == 0) 1140 #endif 1141 { 1142 int rv; 1143 1144 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_BTUART_BASE, 1145 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1146 if (rv == 0) { 1147 pxa2x0_clkman_config(CKEN_BTUART, 1); 1148 return; 1149 } 1150 } 1151 #endif /* BTUARTCONSOLE */ 1152 1153 #ifdef HWUARTCONSOLE 1154 #ifdef KGDB 1155 if (strcmp(kgdb_devname, "hwuart") == 0) { 1156 /* port is reserved for kgdb */ 1157 } else 1158 #endif 1159 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1160 if (console[0] == '\0' || strcasecmp(console, "hwuart") == 0) 1161 #endif 1162 { 1163 rv = comcnattach(&pxa2x0_a4x_bs_tag, PXA2X0_HWUART_BASE, 1164 comcnspeed, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode); 1165 if (rv == 0) { 1166 pxa2x0_clkman_config(CKEN_HWUART, 1); 1167 return; 1168 } 1169 } 1170 #endif /* HWUARTCONSOLE */ 1171 1172 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1173 1174 if (comcnattach(&omap_a4x_bs_tag, CONSADDR, comcnspeed, 1175 OMAP_COM_FREQ, COM_TYPE_NORMAL, comcnmode) == 0) 1176 return; 1177 1178 #endif /* GUMSTIX or OVERO */ 1179 1180 #endif /* NCOM */ 1181 1182 #if NLCD > 0 1183 #if defined(GUMSTIX_NETBSD_ARGS_CONSOLE) 1184 if (console[0] == '\0' || strcasecmp(console, "lcd") == 0) 1185 #endif 1186 { 1187 gxlcd_cnattach(); 1188 } 1189 #endif 1190 } 1191 1192 #ifdef KGDB 1193 static void 1194 kgdb_port_init(void) 1195 { 1196 #if (NCOM > 0) && defined(COM_PXA2X0) 1197 paddr_t paddr = 0; 1198 int cken = 0; 1199 1200 if (0 == strcmp(kgdb_devname, "ffuart")) { 1201 paddr = PXA2X0_FFUART_BASE; 1202 cken = CKEN_FFUART; 1203 } else if (0 == strcmp(kgdb_devname, "stuart")) { 1204 paddr = PXA2X0_STUART_BASE; 1205 cken = CKEN_STUART; 1206 } else if (0 == strcmp(kgdb_devname, "btuart")) { 1207 paddr = PXA2X0_BTUART_BASE; 1208 cken = CKEN_BTUART; 1209 } else if (0 == strcmp(kgdb_devname, "hwuart")) { 1210 paddr = PXA2X0_HWUART_BASE; 1211 cken = CKEN_HWUART; 1212 } 1213 1214 if (paddr && 1215 0 == com_kgdb_attach(&pxa2x0_a4x_bs_tag, paddr, 1216 kgdb_devrate, PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comkgdbmode)) { 1217 1218 pxa2x0_clkman_config(cken, 1); 1219 } 1220 1221 #endif 1222 } 1223 #endif 1224 1225 static void 1226 gumstix_device_register(device_t dev, void *aux) 1227 { 1228 prop_dictionary_t dict = device_properties(dev); 1229 1230 if (device_is_a(dev, "arma9tmr") || 1231 device_is_a(dev, "a9wdt")) { 1232 /* 1233 * We need to tell the A9 Global/Watchdog Timer 1234 * what frequency it runs at. 1235 */ 1236 1237 /* 1238 * This clock always runs at (arm_clk div 2) and only goes 1239 * to timers that are part of the A9 MP core subsystem. 1240 */ 1241 prop_dictionary_set_uint32(dict, "frequency", 1242 curcpu()->ci_data.cpu_cc_freq / 2); 1243 } 1244 if (device_is_a(dev, "armperiph")) { 1245 if (device_is_a(device_parent(dev), "mainbus")) { 1246 #if defined(OMAP2) 1247 /* 1248 * XXX KLUDGE ALERT XXX 1249 * The iot mainbus supplies is completely wrong since 1250 * it scales addresses by 2. The simpliest remedy is 1251 * to replace with our bus space used for the armcore 1252 * registers (which armperiph uses). 1253 */ 1254 struct mainbus_attach_args * const mb = aux; 1255 mb->mb_iot = &omap_bs_tag; 1256 #endif 1257 } 1258 } 1259 if (device_is_a(dev, "ehci")) { 1260 #if defined(OVERO) 1261 prop_dictionary_set_uint16(dict, "nports", 2); 1262 prop_dictionary_set_bool(dict, "phy-reset", true); 1263 prop_dictionary_set_cstring(dict, "port0-mode", "none"); 1264 prop_dictionary_set_int16(dict, "port0-gpio", -1); 1265 prop_dictionary_set_cstring(dict, "port1-mode", "phy"); 1266 prop_dictionary_set_int16(dict, "port1-gpio", 183); 1267 prop_dictionary_set_bool(dict, "port1-gpioval", true); 1268 #elif defined(DUOVERO) 1269 prop_dictionary_set_uint16(dict, "nports", 1); 1270 prop_dictionary_set_bool(dict, "phy-reset", true); 1271 prop_dictionary_set_cstring(dict, "port0-mode", "phy"); 1272 prop_dictionary_set_int16(dict, "port0-gpio", 62); 1273 prop_dictionary_set_bool(dict, "port0-gpioval", false); 1274 prop_dictionary_set_bool(dict, "port0-extclk", true); 1275 #endif 1276 prop_dictionary_set_uint16(dict, "dpll5-m", 443); 1277 prop_dictionary_set_uint16(dict, "dpll5-n", 11); 1278 prop_dictionary_set_uint16(dict, "dpll5-m2", 4); 1279 } 1280 if (device_is_a(dev, "ohci")) { 1281 if (prop_dictionary_set_bool(dict, 1282 "Ganged-power-mask-on-port1", 1) == false) { 1283 printf("WARNING: unable to set power-mask for port1" 1284 " property for %s\n", device_xname(dev)); 1285 } 1286 if (prop_dictionary_set_bool(dict, 1287 "Ganged-power-mask-on-port2", 1) == false) { 1288 printf("WARNING: unable to set power-mask for port2" 1289 " property for %s\n", device_xname(dev)); 1290 } 1291 if (prop_dictionary_set_bool(dict, 1292 "Ganged-power-mask-on-port3", 1) == false) { 1293 printf("WARNING: unable to set power-mask for port3" 1294 " property for %s\n", device_xname(dev)); 1295 } 1296 } 1297 if (device_is_a(dev, "omapmputmr")) { 1298 struct obio_attach_args *obio = aux; 1299 1300 switch (obio->obio_addr) { 1301 case 0x49032000: /* GPTIMER2 */ 1302 case 0x49034000: /* GPTIMER3 */ 1303 case 0x49036000: /* GPTIMER4 */ 1304 case 0x49038000: /* GPTIMER5 */ 1305 case 0x4903a000: /* GPTIMER6 */ 1306 case 0x4903c000: /* GPTIMER7 */ 1307 case 0x4903e000: /* GPTIMER8 */ 1308 case 0x49040000: /* GPTIMER9 */ 1309 #if defined(OVERO) 1310 { 1311 /* Ensure enable PRCM.CM_[FI]CLKEN_PER[3:10]. */ 1312 const int en = 1313 1 << (((obio->obio_addr >> 13) & 0x3f) - 0x16); 1314 1315 ioreg_write(OVERO_L4_CORE_VBASE + 0x5000, 1316 ioreg_read(OVERO_L4_CORE_VBASE + 0x5000) | en); 1317 ioreg_write(OVERO_L4_CORE_VBASE + 0x5010, 1318 ioreg_read(OVERO_L4_CORE_VBASE + 0x5010) | en); 1319 } 1320 #endif 1321 break; 1322 } 1323 } 1324 if (device_is_a(dev, "sdhc")) { 1325 bool dualvolt = false; 1326 1327 #if defined(OVERO) || defined(DUOVERO) 1328 if (device_is_a(device_parent(dev), "obio")) { 1329 struct obio_attach_args *obio = aux; 1330 1331 #if defined(OVERO) 1332 if (obio->obio_addr == SDMMC2_BASE_3530) 1333 dualvolt = true; 1334 #elif defined(DUOVERO) 1335 if (obio->obio_addr == SDMMC5_BASE_4430) 1336 dualvolt = true; 1337 #endif 1338 } 1339 #endif 1340 #if defined(PEPPER) 1341 if (device_is_a(device_parent(dev), "mainbus")) { 1342 struct mainbus_attach_args * const mb = aux; 1343 1344 if (mb->mb_iobase == SDMMC3_BASE_TIAM335X) 1345 dualvolt = true; 1346 } 1347 #endif 1348 prop_dictionary_set_bool(dict, "dual-volt", dualvolt); 1349 } 1350 if (device_is_a(dev, "tifb")) { 1351 prop_data_t panel_info; 1352 1353 panel_info = prop_data_create_data_nocopy(tifb_panel_info, 1354 sizeof(struct tifb_panel_info)); 1355 KASSERT(panel_info != NULL); 1356 prop_dictionary_set(dict, "panel-info", panel_info); 1357 prop_object_release(panel_info); 1358 1359 #if defined(OMAP2) 1360 /* enable LCD */ 1361 omap2_gpio_ctl(59, GPIO_PIN_OUTPUT); 1362 omap2_gpio_write(59, 0); /* reset */ 1363 delay(100); 1364 omap2_gpio_write(59, 1); 1365 #endif 1366 } 1367 if (device_is_a(dev, "tps65217pmic")) { 1368 #if defined(TI_AM335X) 1369 extern const char *mpu_supply; 1370 1371 mpu_supply = "DCDC3"; 1372 #endif 1373 1374 if (use_tps65217_wled) { 1375 prop_dictionary_set_int32(dict, "isel", 1); 1376 prop_dictionary_set_int32(dict, "fdim", 200); 1377 prop_dictionary_set_int32(dict, "brightness", 80); 1378 } 1379 } 1380 } 1381
Indexes created Fri Oct 03 02:09:57 GMT 2025