gxiic.c revision 1.1
1 /* $NetBSD: gxiic.c,v 1.1 2007/08/21 12:36:18 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: gxiic.c,v 1.1 2007/08/21 12:36:18 kiyohara Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/device.h> 32 #include <sys/errno.h> 33 #include <sys/lock.h> 34 35 #include <arm/xscale/pxa2x0_i2c.h> 36 37 #include <evbarm/gumstix/gumstixvar.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 42 struct gxiic_softc { 43 struct pxa2x0_i2c_softc sc_pxa_i2c; 44 45 struct i2c_controller sc_i2c; 46 struct lock sc_lock; 47 }; 48 49 50 static int gxiicmatch(struct device *, struct cfdata *, void *); 51 static void gxiicattach(struct device *, struct device *, void *); 52 53 /* fuctions for i2c_controller */ 54 static int gxiic_acquire_bus(void *, int); 55 static void gxiic_release_bus(void *, int); 56 static int gxiic_exec(void *cookie, i2c_op_t, i2c_addr_t, const void *, size_t, 57 void *, size_t, int); 58 59 60 CFATTACH_DECL(gxiic, sizeof(struct gxiic_softc), 61 gxiicmatch, gxiicattach, NULL, NULL); 62 63 64 /* ARGSUSED */ 65 static int 66 gxiicmatch(struct device *parent, struct cfdata *match, void *aux) 67 { 68 69 return 1; 70 } 71 72 /* ARGSUSED */ 73 static void 74 gxiicattach(struct device *parent, struct device *self, void *aux) 75 { 76 struct gxiic_softc *sc = device_private(self); 77 struct gxio_attach_args *gxa = aux; 78 struct i2cbus_attach_args iba; 79 80 aprint_normal("\n"); 81 aprint_naive("\n"); 82 83 sc->sc_pxa_i2c.sc_iot = gxa->gxa_iot; 84 sc->sc_pxa_i2c.sc_size = PXA2X0_I2C_SIZE; 85 if (pxa2x0_i2c_attach_sub(&sc->sc_pxa_i2c)) { 86 aprint_error(": unable to attach PXA I2C\n"); 87 return; 88 } 89 90 lockinit(&sc->sc_lock, PZERO, "gxiic", 0, 0); 91 92 /* Initialize i2c_controller */ 93 sc->sc_i2c.ic_cookie = sc; 94 sc->sc_i2c.ic_acquire_bus = gxiic_acquire_bus; 95 sc->sc_i2c.ic_release_bus = gxiic_release_bus; 96 sc->sc_i2c.ic_send_start = NULL; 97 sc->sc_i2c.ic_send_stop = NULL; 98 sc->sc_i2c.ic_initiate_xfer = NULL; 99 sc->sc_i2c.ic_read_byte = NULL; 100 sc->sc_i2c.ic_write_byte = NULL; 101 sc->sc_i2c.ic_exec = gxiic_exec; 102 103 iba.iba_tag = &sc->sc_i2c; 104 pxa2x0_i2c_open(&sc->sc_pxa_i2c); 105 config_found_ia(&sc->sc_pxa_i2c.sc_dev, "i2cbus", &iba, iicbus_print); 106 pxa2x0_i2c_close(&sc->sc_pxa_i2c); 107 } 108 109 static int 110 gxiic_acquire_bus(void *cookie, int flags) 111 { 112 struct gxiic_softc *sc = cookie; 113 int err; 114 115 if ((err = lockmgr(&sc->sc_lock, LK_EXCLUSIVE, NULL)) == 0) 116 pxa2x0_i2c_open(&sc->sc_pxa_i2c); 117 118 return err; 119 } 120 121 static void 122 gxiic_release_bus(void *cookie, int flags) 123 { 124 struct gxiic_softc *sc = cookie; 125 126 lockmgr(&sc->sc_lock, LK_RELEASE, NULL); 127 pxa2x0_i2c_close(&sc->sc_pxa_i2c); 128 return; 129 } 130 131 static int 132 gxiic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd, 133 size_t cmdlen, void *vbuf, size_t buflen, int flags) 134 { 135 struct gxiic_softc *sc = cookie; 136 int rv = -1; 137 138 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) 139 rv = pxa2x0_i2c_read(&sc->sc_pxa_i2c, addr, (u_char *)vbuf); 140 141 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 142 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c, addr, *(u_char *)vbuf); 143 if (rv == 0) 144 rv = pxa2x0_i2c_read(&sc->sc_pxa_i2c, 145 addr, (u_char *)vbuf); 146 } 147 148 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 2)) { 149 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c, addr, *(u_char *)vbuf); 150 if (rv == 0) 151 rv = pxa2x0_i2c_read(&sc->sc_pxa_i2c, 152 addr, (u_char *)vbuf); 153 if (rv == 0) 154 rv = pxa2x0_i2c_read(&sc->sc_pxa_i2c, 155 addr, (u_char *)(vbuf) + 1); 156 } 157 158 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) 159 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c, addr, *(u_char *)vbuf); 160 161 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) { 162 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c, 163 addr, *(const u_char *)vcmd); 164 if (rv == 0) 165 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c, 166 addr, *(u_char *)vbuf); 167 } 168 169 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 2)) { 170 rv = pxa2x0_i2c_write(&sc->sc_pxa_i2c, 171 addr, *(const u_char *)vcmd); 172 if (rv == 0) 173 rv = pxa2x0_i2c_write_2(&sc->sc_pxa_i2c, 174 addr, *(u_short *)vbuf); 175 } 176 177 return rv; 178 } 179
Indexes created Mon Oct 20 08:09:54 GMT 2025