gxio.c revision 1.20.18.2
1 /* $NetBSD: gxio.c,v 1.20.18.2 2017/03/20 06:57:13 pgoyette Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: gxio.c,v 1.20.18.2 2017/03/20 06:57:13 pgoyette Exp $"); 35 36 #include "opt_cputypes.h" 37 #include "opt_gumstix.h" 38 #include "opt_gxio.h" 39 #if defined(OVERO) 40 #include "opt_omap.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/device.h> 45 #include <sys/errno.h> 46 #include <sys/kernel.h> 47 48 #include <sys/systm.h> 49 50 #include <machine/bootconfig.h> 51 52 #include <arm/omap/omap2_gpmcreg.h> 53 #if defined(OMAP2) 54 #include <arm/omap/omap2_reg.h> 55 #if defined(OMAP3530) 56 #include <arm/omap/omap2_intr.h> 57 #endif 58 #endif 59 #include <arm/omap/omap_var.h> 60 #include <arm/omap/ti_iicreg.h> 61 #include <arm/omap/tifbvar.h> 62 #if defined(CPU_XSCALE) 63 #include <arm/xscale/pxa2x0cpu.h> 64 #endif 65 #include <arm/xscale/pxa2x0reg.h> 66 #include <arm/xscale/pxa2x0var.h> 67 #include <arm/xscale/pxa2x0_gpio.h> 68 #include <evbarm/gumstix/gumstixreg.h> 69 #include <evbarm/gumstix/gumstixvar.h> 70 71 #include "ioconf.h" 72 #include "locators.h" 73 74 75 struct gxioconf { 76 const char *name; 77 void (*config)(void); 78 }; 79 80 #if defined(GUMSTIX) 81 static int gxiomatch(device_t, cfdata_t, void *); 82 static void gxioattach(device_t, device_t, void *); 83 static int gxiosearch(device_t, cfdata_t, const int *, void *); 84 static int gxioprint(void *, const char *); 85 86 CFATTACH_DECL_NEW(gxio, sizeof(struct gxio_softc), 87 gxiomatch, gxioattach, NULL, NULL); 88 #endif 89 90 void gxio_config(void); 91 void gxio_config_expansion(const char *); 92 #if defined(GUMSTIX) 93 static void basix_config(void); 94 static void cfstix_config(void); 95 static void etherstix_config(void); 96 static void netcf_config(void); 97 static void netcf_vx_config(void); 98 static void netduommc_config(void); 99 static void netduo_config(void); 100 static void netmicrosd_config(void); 101 static void netwifimicrosd_config(void); 102 static void netmmc_config(void); 103 static void wifistix_config(void); 104 static void wifistix_cf_config(void); 105 #elif defined(OVERO) 106 static void eth0_config(void); 107 static void eth1_config(void); 108 static void dvi_config(void); 109 static void lcd_config(char); 110 static void header_40pin_config(int); 111 112 static void chestnut_config(void); 113 static void gallop_config(void); 114 static void summit_config(void); 115 static void tobi_config(void); 116 static void tobiduo_config(void); 117 #elif defined(DUOVERO) 118 static void ehci_config(void); 119 120 static void parlor_config(void); 121 #elif defined(PEPPER) 122 static void lcd_config(void); 123 static void pepper43_config(void); 124 125 static void pepper_config(void); 126 static void c_config(void); 127 static void dvi_config(void); 128 static void r_config(void); 129 #endif 130 #if defined(OVERO) || defined(DUOVERO) 131 struct omap_mux_conf; 132 static void smsh_config(struct omap_mux_conf *, int, int); 133 #endif 134 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 135 static void __udelay(unsigned int); 136 #endif 137 #if defined(PEPPER) 138 static int read_i2c_device(const vaddr_t, uint16_t, uint8_t, int, uint8_t *); 139 #endif 140 141 #if defined(CPU_XSCALE_PXA250) 142 143 static struct pxa2x0_gpioconf pxa255dep_gpioconf[] = { 144 /* Bluetooth module configuration */ 145 { 7, GPIO_OUT | GPIO_SET }, /* power on */ 146 { 12, GPIO_ALT_FN_1_OUT }, /* 32kHz out. required by SingleStone */ 147 148 /* AC97 configuration */ 149 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 150 151 /* FFUART configuration */ 152 { 35, GPIO_ALT_FN_1_IN }, /* CTS */ 153 { 41, GPIO_ALT_FN_2_OUT }, /* RTS */ 154 155 #ifndef GXIO_BLUETOOTH_ON_HWUART 156 /* BTUART configuration */ 157 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 158 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 159 #else 160 /* HWUART configuration */ 161 { 42, GPIO_ALT_FN_3_IN }, /* HWRXD */ 162 { 43, GPIO_ALT_FN_3_OUT }, /* HWTXD */ 163 { 44, GPIO_ALT_FN_3_IN }, /* HWCTS */ 164 { 45, GPIO_ALT_FN_3_OUT }, /* HWRTS */ 165 #endif 166 167 #ifndef GXIO_BLUETOOTH_ON_HWUART 168 /* HWUART configuration */ 169 { 48, GPIO_ALT_FN_1_OUT }, /* HWTXD */ 170 { 49, GPIO_ALT_FN_1_IN }, /* HWRXD */ 171 { 50, GPIO_ALT_FN_1_IN }, /* HWCTS */ 172 { 51, GPIO_ALT_FN_1_OUT }, /* HWRTS */ 173 #endif 174 175 { -1 } 176 }; 177 #endif 178 #if defined(CPU_XSCALE_PXA270) 179 static struct pxa2x0_gpioconf verdexdep_gpioconf[] = { 180 /* Bluetooth module configuration */ 181 { 9, GPIO_ALT_FN_3_OUT }, /* CHOUT<0> */ 182 { 12, GPIO_OUT | GPIO_SET }, 183 184 /* LCD configuration */ 185 { 17, GPIO_IN }, /* backlight on */ 186 187 /* FFUART configuration */ 188 { 34, GPIO_ALT_FN_1_IN }, /* FFRXD */ 189 { 39, GPIO_ALT_FN_2_OUT }, /* FFTXD */ 190 191 /* BTUART configuration */ 192 { 42, GPIO_ALT_FN_1_IN }, /* BTRXD */ 193 { 43, GPIO_ALT_FN_2_OUT }, /* BTTXD */ 194 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 195 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 196 197 /* AC97 configuration */ 198 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 199 200 { -1 } 201 }; 202 203 #elif defined(OMAP2) 204 205 struct omap_mux_conf { 206 int offset; 207 uint32_t value; 208 /* OMAP3/4 register values */ 209 #define WAKEUPEVENT (1 << 15) 210 #define WAKEUPENABLE (1 << 14) 211 #define OFFMODEPULLTYPESELECT (1 << 13) 212 #define OFFMODEPULLUDENABLE (1 << 12) 213 #define OFFMODEOUTVALUE (1 << 11) 214 #define OFFMODEOUTENABLE (1 << 10) 215 #define OFFMODEENABLE (1 << 9) 216 #define INPUTENABLE (1 << 8) 217 #define PULLTYPESELECT (1 << 4) 218 #define PULLUDENABLE (1 << 3) 219 #define MUXMODE(n) ((n) & 0x7) 220 221 /* Sitara AM3xxx register values */ 222 #define SLEWCTRL (1 << 6) 223 #define RXACTIVE (1 << 5) 224 #define PUTYPESEL (1 << 4) 225 #define PUDEN (1 << 3) 226 #define MMODE(n) ((n) & 0x7) 227 }; 228 struct omap_gpio_conf { 229 int pin; 230 enum { 231 conf_input = -1, 232 conf_output_0, 233 conf_output_1, 234 } conf; 235 }; 236 237 static void gxio_omap_mux_config(const struct omap_mux_conf []); 238 static int gxio_omap_mux_config_address(const char *, unsigned long, 239 const struct omap_mux_conf[], 240 const struct omap_mux_conf[]); 241 static void gxio_omap_gpio_config(const struct omap_gpio_conf[]); 242 void gxio_omap_gpio_write(int, int); 243 244 static const struct omap_mux_conf overo_mux_i2c3_conf[] = { 245 { 0x1c2, MUXMODE(0) | INPUTENABLE }, /* i2c3_scl */ 246 { 0x1c4, MUXMODE(0) | INPUTENABLE }, /* i2c3_sda */ 247 { -1 } 248 }; 249 static const struct omap_mux_conf overo_mux_mmchs2_conf[] = { 250 { 0x158, /* mmc2_clk */ 251 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 252 { 0x15a, /* mmc2_cmd */ 253 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 254 { 0x15c, /* mmc2_dat0 */ 255 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 256 { 0x15e, /* mmc2_dat1 */ 257 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 258 { 0x160, /* mmc2_dat2 */ 259 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 260 { 0x162, /* mmc2_dat3 */ 261 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 262 { -1 } 263 }; 264 #if defined(OVERO) 265 static const struct omap_mux_conf overo_mux_wireless_conf[] = { 266 { 0x0b4, MUXMODE(4) }, /* gpio_54:BT_nPOWERON*/ 267 { 0x0bc, MUXMODE(4) | INPUTENABLE }, /* gpio_58: WIFI_IRQ */ 268 { 0x19c, MUXMODE(4) }, /* gpio_164:BT_nRESET */ 269 { 0x5e0, MUXMODE(4) }, /* gpio_16: W2W_nRESET*/ 270 { -1 } 271 }; 272 273 #elif defined(DUOVERO) 274 static const struct omap_mux_conf duovero_mux_led_conf[] = { 275 { 0x116, MUXMODE(3) }, /* GPIO 122 */ 276 { -1 } 277 }; 278 static const struct omap_mux_conf duovero_mux_button_conf[] = { 279 { 0x114, /* GPIO 121 */ 280 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 281 { -1 } 282 }; 283 284 #elif defined(PEPPER) 285 static const struct omap_mux_conf pepper_mux_led_conf[] = { 286 { 0x850, MMODE(7) | PUDEN }, /* GPIO 52: Blue */ 287 { 0x854, MMODE(7) | PUDEN }, /* GPIO 53: Red */ 288 { -1 } 289 }; 290 static const struct omap_mux_conf pepper_mux_button_conf[] = { 291 { 0x858, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 54 */ 292 { -1 } 293 }; 294 static const struct omap_mux_conf pepper_mux_mmchs3_conf[] = { 295 { 0x844, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT0 */ 296 { 0x848, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT1 */ 297 { 0x84c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT2 */ 298 { 0x878, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT3 */ 299 { 0x888, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CMD */ 300 { 0x88c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CLK */ 301 { -1 } 302 }; 303 static const struct omap_mux_conf pepper_mux_audio_codec_conf[] = { 304 { 0x840, MMODE(7) | PUDEN }, /* GPIO 48: #Reset */ 305 { -1 } 306 }; 307 #endif 308 309 #endif 310 311 static const struct gxioconf gxioconflist[] = { 312 #if defined(GUMSTIX) 313 { "basix", basix_config }, 314 { "cfstix", cfstix_config }, 315 { "etherstix", etherstix_config }, 316 { "netcf", netcf_config }, 317 { "netcf-vx", netcf_vx_config }, 318 { "netduo-mmc", netduommc_config }, 319 { "netduo", netduo_config }, 320 { "netmicrosd", netmicrosd_config }, 321 { "netmicrosd-vx", netmicrosd_config }, 322 { "netwifimicrosd", netwifimicrosd_config }, 323 { "netmmc", netmmc_config }, 324 { "netpro-vx", netwifimicrosd_config }, 325 { "wifistix-cf", wifistix_cf_config }, 326 { "wifistix", wifistix_config }, 327 #elif defined(OVERO) 328 { "chestnut43", chestnut_config }, 329 { "gallop43", gallop_config }, 330 { "summit", summit_config }, 331 { "tobi", tobi_config }, 332 { "tobi-duo", tobiduo_config }, 333 #elif defined(DUOVERO) 334 { "parlor", parlor_config }, 335 #elif defined(PEPPER) 336 { "43c", c_config }, 337 { "43r", r_config }, 338 { "dvi", dvi_config }, 339 #endif 340 { NULL } 341 }; 342 343 int gxpcic_gpio_reset; 344 struct gxpcic_slot_irqs gxpcic_slot_irqs[2] = { { 0, -1, -1 }, { 0, -1, -1 } }; 345 346 347 #if defined(GUMSTIX) 348 /* ARGSUSED */ 349 static int 350 gxiomatch(device_t parent, cfdata_t match, void *aux) 351 { 352 353 struct pxaip_attach_args *pxa = aux; 354 bus_space_tag_t iot = &pxa2x0_bs_tag; 355 bus_space_handle_t ioh; 356 357 if (strcmp(pxa->pxa_name, match->cf_name) != 0 || 358 pxa->pxa_addr != PXAIPCF_ADDR_DEFAULT) 359 return 0; 360 361 if (bus_space_map(iot, 362 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &ioh)) 363 return 0; 364 bus_space_unmap(iot, ioh, PXA2X0_MEMCTL_SIZE); 365 366 /* nothing */ 367 return 1; 368 } 369 370 /* ARGSUSED */ 371 static void 372 gxioattach(device_t parent, device_t self, void *aux) 373 { 374 struct gxio_softc *sc = device_private(self); 375 376 aprint_normal("\n"); 377 aprint_naive("\n"); 378 379 sc->sc_dev = self; 380 sc->sc_iot = &pxa2x0_bs_tag; 381 382 if (bus_space_map(sc->sc_iot, 383 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &sc->sc_ioh)) 384 return; 385 386 /* 387 * Attach each gumstix(busheader)/overo expansion board devices. 388 */ 389 config_search_ia(gxiosearch, self, "gxio", NULL); 390 } 391 392 /* ARGSUSED */ 393 static int 394 gxiosearch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 395 { 396 struct gxio_softc *sc = device_private(parent); 397 struct gxio_attach_args gxa; 398 399 gxa.gxa_sc = sc; 400 gxa.gxa_iot = sc->sc_iot; 401 gxa.gxa_addr = cf->cf_loc[GXIOCF_ADDR]; 402 gxa.gxa_gpirq = cf->cf_loc[GXIOCF_GPIRQ]; 403 404 if (config_match(parent, cf, &gxa)) 405 config_attach(parent, cf, &gxa, gxioprint); 406 407 return 0; 408 } 409 410 /* ARGSUSED */ 411 static int 412 gxioprint(void *aux, const char *name) 413 { 414 struct gxio_attach_args *gxa = (struct gxio_attach_args *)aux; 415 416 if (gxa->gxa_addr != GXIOCF_ADDR_DEFAULT) 417 printf(" addr 0x%lx", gxa->gxa_addr); 418 if (gxa->gxa_gpirq > 0) 419 printf(" gpirq %d", gxa->gxa_gpirq); 420 return UNCONF; 421 } 422 #endif 423 424 425 #if defined(GUMSTIX) 426 /* 427 * configure for GPIO pin and expansion boards. 428 */ 429 void 430 gxio_config(void) 431 { 432 #if defined(CPU_XSCALE_PXA250) 433 struct pxa2x0_gpioconf *gumstix_gpioconf[] = { 434 pxa25x_com_ffuart_gpioconf, 435 pxa25x_com_stuart_gpioconf, 436 #ifndef GXIO_BLUETOOTH_ON_HWUART 437 pxa25x_com_btuart_gpioconf, 438 #endif 439 pxa25x_com_hwuart_gpioconf, 440 pxa25x_i2c_gpioconf, 441 pxa25x_pxaacu_gpioconf, 442 pxa255dep_gpioconf, 443 NULL 444 }; 445 #endif 446 #if defined(CPU_XSCALE_PXA270) 447 struct pxa2x0_gpioconf *verdex_gpioconf[] = { 448 pxa27x_com_ffuart_gpioconf, 449 pxa27x_com_stuart_gpioconf, 450 pxa27x_com_btuart_gpioconf, 451 pxa27x_i2c_gpioconf, 452 pxa27x_pxaacu_gpioconf, 453 pxa27x_pxamci_gpioconf, 454 pxa27x_ohci_gpioconf, 455 verdexdep_gpioconf, 456 NULL 457 }; 458 #endif 459 460 /* XXX: turn off for power of bluetooth module */ 461 #if defined(CPU_XSCALE_PXA250) 462 pxa2x0_gpio_set_function(7, GPIO_OUT | GPIO_CLR); 463 #elif defined(CPU_XSCALE_PXA270) 464 pxa2x0_gpio_set_function(12, GPIO_OUT | GPIO_CLR); 465 #endif 466 delay(100); 467 468 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 469 pxa2x0_gpio_config( 470 (CPU_IS_PXA250) ? gumstix_gpioconf : verdex_gpioconf); 471 #elif defined(CPU_XSCALE_PXA270) || defined(CPU_XSCALE_PXA250) 472 #if defined(CPU_XSCALE_PXA270) 473 pxa2x0_gpio_config(verdex_gpioconf); 474 #else 475 pxa2x0_gpio_config(gumstix_gpioconf); 476 #endif 477 #endif 478 } 479 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 480 static void 481 gxio_omap_mux_config(const struct omap_mux_conf mux_conf[]) 482 { 483 #if defined(OVERO) 484 const vaddr_t ctrlmod_base = OVERO_L4_CORE_VBASE + 0x2000; 485 #elif defined(DUOVERO) 486 const vaddr_t ctrlmod_base = DUOVERO_L4_CM_VBASE; 487 #elif defined(PEPPER) 488 const vaddr_t ctrlmod_base = PEPPER_PRCM_VBASE + 0x10000; 489 #endif 490 int i; 491 492 for (i = 0; mux_conf[i].offset != -1; i++) 493 #if !defined(TI_AM335X) 494 ioreg16_write(ctrlmod_base + mux_conf[i].offset, 495 mux_conf[i].value); 496 #else 497 ioreg_write(ctrlmod_base + mux_conf[i].offset, 498 mux_conf[i].value); 499 #endif 500 } 501 502 static int 503 gxio_omap_mux_config_address(const char *name, unsigned long address, 504 const struct omap_mux_conf mux_conf[], 505 const struct omap_mux_conf not_mux_conf[]) 506 { 507 extern struct cfdata cfdata[]; 508 cfdata_t cf = &cfdata[0]; 509 510 while (cf->cf_name != NULL) { 511 if (strcmp(name, cf->cf_name) == 0 && 512 address == cf->cf_loc[OBIOCF_ADDR]) { 513 gxio_omap_mux_config(mux_conf); 514 return 0; 515 } 516 cf++; 517 } 518 519 if (not_mux_conf == NULL) 520 return -1; 521 522 gxio_omap_mux_config(not_mux_conf); 523 return 0; 524 } 525 526 #if defined(OVERO) 527 #define gpio_reg_read ioreg_read 528 #define gpio_reg_write ioreg_write 529 #elif defined(DUOVERO) || defined(PEPPER) 530 #define gpio_reg_read(a) ioreg_read((a) + GPIO_SIZE2) 531 #define gpio_reg_write(a, v) ioreg_write((a) + GPIO_SIZE2, (v)) 532 #endif 533 534 static const vaddr_t gpio_bases[] = { 535 #if defined(OVERO) 536 #define OVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 537 #define GPIO(n) GPIO ## n ## _BASE_3530 538 #define BASE(a, n) \ 539 (OVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP3530_L4_ ## a ## _BASE)) 540 541 GPIO1_BASE_3530, 542 GPIO2_BASE_3530, 543 GPIO3_BASE_3530, 544 GPIO4_BASE_3530, 545 GPIO5_BASE_3530, 546 GPIO6_BASE_3530, 547 548 #elif defined(DUOVERO) 549 #define DUOVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 550 #define GPIO(n) GPIO ## n ## _BASE_4430 551 #define BASE(a, n) \ 552 (DUOVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP4430_L4_ ## a ## _BASE)) 553 554 DUOVERO_GPIO_VBASE(1), 555 DUOVERO_GPIO_VBASE(2), 556 DUOVERO_GPIO_VBASE(3), 557 DUOVERO_GPIO_VBASE(4), 558 DUOVERO_GPIO_VBASE(5), 559 560 #elif defined(PEPPER) 561 #define PEPPER_GPIO_VBASE(n) ((n) == 0 ? WAKEUP(n) : PERIPHERAL(n)) 562 #define GPIO(n) GPIO ## n ## _BASE_TI_AM335X 563 #define WAKEUP(n) (PEPPER_PRCM_VBASE + (GPIO(n) - OMAP2_CM_BASE)) 564 #define PERIPHERAL(n) \ 565 (PEPPER_L4_PERIPHERAL_VBASE + (GPIO(n) - TI_AM335X_L4_PERIPHERAL_BASE)) 566 567 PEPPER_GPIO_VBASE(0), 568 PEPPER_GPIO_VBASE(1), 569 PEPPER_GPIO_VBASE(2), 570 PEPPER_GPIO_VBASE(3), 571 #endif 572 }; 573 574 static void 575 gxio_omap_gpio_config(const struct omap_gpio_conf gpio_conf[]) 576 { 577 vaddr_t gpio_base; 578 int mask, i; 579 580 for (i = 0; gpio_conf[i].pin != -1; i++) { 581 gpio_base = gpio_bases[gpio_conf[i].pin / 32]; 582 mask = 1 << (gpio_conf[i].pin % 32); 583 switch (gpio_conf[i].conf) { 584 case conf_input: 585 ioreg_write(gpio_base + GPIO_OE, 586 ioreg_read(gpio_base + GPIO_OE) | mask); 587 break; 588 case conf_output_0: 589 ioreg_write(gpio_base + GPIO_OE, 590 ioreg_read(gpio_base + GPIO_OE) | ~mask); 591 #if 0 592 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 593 #else 594 ioreg_write(gpio_base + GPIO_DATAOUT, 595 ioreg_read(gpio_base + GPIO_DATAOUT) & ~mask); 596 #endif 597 break; 598 case conf_output_1: 599 ioreg_write(gpio_base + GPIO_OE, 600 ioreg_read(gpio_base + GPIO_OE) | ~mask); 601 #if 0 602 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 603 #else 604 ioreg_write(gpio_base + GPIO_DATAOUT, 605 ioreg_read(gpio_base + GPIO_DATAOUT) | mask); 606 #endif 607 break; 608 } 609 } 610 } 611 612 void 613 gxio_omap_gpio_write(int pin, int val) 614 { 615 vaddr_t gpio_base; 616 int mask; 617 618 KASSERT(pin / 32 < __arraycount(gpio_bases)); 619 620 gpio_base = gpio_bases[pin / 32]; 621 mask = 1 << (pin % 32); 622 if (val == 0) 623 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 624 else 625 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 626 } 627 628 /* 629 * configure for MUX, GPIO. 630 */ 631 void 632 gxio_config(void) 633 { 634 const struct omap_mux_conf *mux_conf[] = { 635 #if defined(OVERO) 636 overo_mux_i2c3_conf, 637 overo_mux_mmchs2_conf, 638 overo_mux_wireless_conf, 639 #elif defined(DUOVERO) 640 duovero_mux_led_conf, 641 duovero_mux_button_conf, 642 #elif defined(PEPPER) 643 pepper_mux_led_conf, 644 pepper_mux_button_conf, 645 pepper_mux_mmchs3_conf, 646 pepper_mux_audio_codec_conf, 647 #endif 648 }; 649 const struct omap_gpio_conf gpio_conf[] = { 650 #if defined(OVERO) 651 { 16, conf_output_0 }, /* Wireless: #Reset */ 652 #elif defined(PEPPER) 653 { 48, conf_output_0 }, /* Audio Codec: #Reset */ 654 #endif 655 { -1 } 656 }; 657 int i; 658 659 for (i = 0; i < __arraycount(mux_conf); i++) 660 gxio_omap_mux_config(mux_conf[i]); 661 gxio_omap_gpio_config(gpio_conf); 662 } 663 #endif 664 665 static int 666 gxio_find_default_expansion(void) 667 { 668 #ifdef GXIO_DEFAULT_EXPANSION 669 int i; 670 671 /* Find out the default expansion */ 672 for (i = 0; gxioconflist[i].name != NULL; i++) 673 if (strncasecmp(gxioconflist[i].name, GXIO_DEFAULT_EXPANSION, 674 strlen(gxioconflist[i].name) + 1) == 0) 675 break; 676 return gxioconflist[i].name == NULL ? -1 : i; 677 #else 678 return -1; 679 #endif 680 } 681 682 void 683 gxio_config_expansion(const char *expansion) 684 { 685 int i, d; 686 687 d = gxio_find_default_expansion(); 688 689 /* Print information about expansions */ 690 printf("supported expansions:\n"); 691 for (i = 0; gxioconflist[i].name != NULL; i++) 692 printf(" %s%s\n", gxioconflist[i].name, 693 i == d ? " (DEFAULT)" : ""); 694 695 696 if (expansion == NULL) { 697 printf("not specified 'expansion=' in the boot args.\n"); 698 i = -1; 699 } else { 700 for (i = 0; gxioconflist[i].name != NULL; i++) 701 if (strncasecmp(gxioconflist[i].name, expansion, 702 strlen(gxioconflist[i].name) + 1) == 0) 703 break; 704 if (gxioconflist[i].name == NULL) { 705 printf("unknown expansion specified: %s\n", expansion); 706 i = -1; 707 } 708 } 709 710 /* Do some magic stuff for PEPPER */ 711 #if defined(PEPPER) 712 if (i < 0) { 713 struct pepper_board_id { 714 unsigned int device_vendor; 715 #define GUMSTIX_PEPPER 0x30000200 /* 1st gen */ 716 #define GUMSTIX_PEPPER_DVI 0x31000200 /* DVI and newer */ 717 unsigned char revision; 718 unsigned char content; 719 char fab_revision[8]; 720 char env_var[16]; 721 char env_setting[64]; 722 } id; 723 const vaddr_t i2c_base = PEPPER_PRCM_VBASE + 0xb000; 724 const uint8_t eeprom = 0x50; 725 const uint8_t len = sizeof(id); 726 int rv; 727 728 rv = read_i2c_device(i2c_base, eeprom, 0x00, len, (void *)&id); 729 if (rv == 0) 730 if (id.device_vendor == GUMSTIX_PEPPER) { 731 printf("configure auto detected expansion" 732 " (pepper)\n"); 733 pepper_config(); 734 return; 735 } 736 } 737 #endif 738 739 /* 740 * Now proceed to configure the default expansion if one was 741 * specified (and found) or return. 742 */ 743 const char *toconfigure; 744 if (i < 0) { 745 #ifdef GXIO_DEFAULT_EXPANSION 746 if (d == -1) { 747 printf("default expansion (%s) not found\n", 748 GXIO_DEFAULT_EXPANSION); 749 return; 750 } 751 expansion = GXIO_DEFAULT_EXPANSION; 752 i = d; 753 toconfigure = "default"; 754 #else 755 return; 756 #endif 757 } else 758 toconfigure = "specified"; 759 760 printf("configure %s expansion (%s)\n", toconfigure, expansion); 761 gxioconflist[i].config(); 762 } 763 764 765 #if defined(GUMSTIX) 766 767 static void 768 basix_config(void) 769 { 770 771 pxa2x0_gpio_set_function(8, GPIO_ALT_FN_1_OUT); /* MMCCS0 */ 772 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_1_OUT); /* MMCCLK */ 773 #if 0 774 /* this configuration set by gxmci.c::pxamci_attach() */ 775 pxa2x0_gpio_set_function(11, GPIO_IN); /* nSD_DETECT */ 776 pxa2x0_gpio_set_function(22, GPIO_IN); /* nSD_WP */ 777 #endif 778 } 779 780 static void 781 cfstix_config(void) 782 { 783 u_int gpio, npoe_fn; 784 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 785 int bvd = (CPU_IS_PXA250) ? 4 : 111; 786 #else 787 #if defined(CPU_XSCALE_PXA270) 788 const int bvd = 111; 789 #else 790 const int bvd = 4; 791 #endif 792 #endif 793 794 if (CPU_IS_PXA250) { 795 gxpcic_slot_irqs[0].valid = 1; 796 gxpcic_slot_irqs[0].cd = 11; 797 gxpcic_slot_irqs[0].prdy = 26; 798 gxpcic_gpio_reset = 8; 799 } else { 800 gxpcic_slot_irqs[0].valid = 1; 801 gxpcic_slot_irqs[0].cd = 104; 802 gxpcic_slot_irqs[0].prdy = 96; 803 gxpcic_gpio_reset = 97; 804 } 805 806 #if 1 807 /* PCD/PRDY set by pxa2x0_pcic.c::pxapcic_attach_common() */ 808 #else 809 pxa2x0_gpio_set_function(11, GPIO_IN); /* PCD1 */ 810 pxa2x0_gpio_set_function(26, GPIO_IN); /* PRDY1/~IRQ1 */ 811 #endif 812 pxa2x0_gpio_set_function(bvd, GPIO_IN); /* BVD1/~STSCHG1 */ 813 814 for (gpio = 48, npoe_fn = 0; gpio <= 53 ; gpio++) 815 npoe_fn |= pxa2x0_gpio_get_function(gpio); 816 npoe_fn &= GPIO_SET; 817 818 pxa2x0_gpio_set_function(48, GPIO_ALT_FN_2_OUT | npoe_fn); /* nPOE */ 819 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 820 pxa2x0_gpio_set_function(50, GPIO_ALT_FN_2_OUT); /* nPIOR */ 821 pxa2x0_gpio_set_function(51, GPIO_ALT_FN_2_OUT); /* nPIOW */ 822 if (CPU_IS_PXA250) { 823 pxa2x0_gpio_set_function(52, GPIO_ALT_FN_2_OUT); /* nPCE1 */ 824 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_2_OUT); /* nPCE2 */ 825 pxa2x0_gpio_set_function(54, GPIO_ALT_FN_2_OUT); /* pSKTSEL */ 826 } else { 827 pxa2x0_gpio_set_function(102, GPIO_ALT_FN_1_OUT); /* nPCE1 */ 828 pxa2x0_gpio_set_function(105, GPIO_ALT_FN_1_OUT); /* nPCE2 */ 829 pxa2x0_gpio_set_function(79, GPIO_ALT_FN_1_OUT); /* pSKTSEL */ 830 } 831 pxa2x0_gpio_set_function(55, GPIO_ALT_FN_2_OUT); /* nPREG */ 832 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); /* nPWAIT */ 833 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); /* nIOIS16 */ 834 } 835 836 static void 837 etherstix_config(void) 838 { 839 extern struct cfdata cfdata[]; 840 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 841 int rst = (CPU_IS_PXA250) ? 80 : 32; 842 int irq = (CPU_IS_PXA250) ? 36 : 99; 843 #else 844 #if defined(CPU_XSCALE_PXA270) 845 const int rst = 32, irq = 99; 846 #else 847 const int rst = 80, irq = 36; 848 #endif 849 #endif 850 int i; 851 852 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 853 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 854 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_SET); /* RESET 1 */ 855 delay(1); 856 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_CLR); 857 delay(50000); 858 859 for (i = 0; cfdata[i].cf_name != NULL; i++) 860 if (strcmp(cfdata[i].cf_name, "sm") == 0 && 861 strcmp(cfdata[i].cf_atname, "sm_gxio") == 0 && 862 cfdata[i].cf_loc[GXIOCF_ADDR] == 0x04000300 && 863 cfdata[i].cf_loc[GXIOCF_GPIRQ] == GXIOCF_GPIRQ_DEFAULT) 864 cfdata[i].cf_loc[GXIOCF_GPIRQ] = irq; 865 } 866 867 static void 868 netcf_config(void) 869 { 870 871 etherstix_config(); 872 cfstix_config(); 873 } 874 875 static void 876 netcf_vx_config(void) 877 { 878 879 /* 880 * XXXX: More power is necessary for NIC and USB??? 881 * (no document. from Linux) 882 */ 883 884 pxa2x0_gpio_set_function(27, GPIO_IN); 885 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); 886 pxa2x0_gpio_set_function(118, GPIO_ALT_FN_1_IN | GPIO_CLR); 887 888 etherstix_config(); 889 cfstix_config(); 890 if (CPU_IS_PXA270) { 891 /* Overwrite */ 892 gxpcic_slot_irqs[0].cd = 104; 893 gxpcic_slot_irqs[0].prdy = 109; 894 gxpcic_gpio_reset = 110; 895 }; 896 } 897 898 static void 899 netduommc_config(void) 900 { 901 902 netduo_config(); 903 basix_config(); 904 } 905 906 static void 907 netduo_config(void) 908 { 909 910 etherstix_config(); 911 912 pxa2x0_gpio_set_function(78, GPIO_ALT_FN_2_OUT); /* nCS 2 */ 913 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_SET); /* RESET 2 */ 914 delay(1); 915 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_CLR); 916 delay(50000); 917 } 918 919 static void 920 netmicrosd_config(void) 921 { 922 923 /* MicroSD(mci) always configure on PXA270 */ 924 925 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 926 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 927 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); /* RESET 1 */ 928 delay(hz / 2); 929 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_SET); 930 delay(50000); 931 } 932 933 static void 934 netwifimicrosd_config(void) 935 { 936 937 netmicrosd_config(); 938 939 cfstix_config(); 940 /* However use pxamci. */ 941 pxa2x0_gpio_set_function(111, GPIO_CLR | GPIO_ALT_FN_1_IN); 942 /* Power to Marvell 88W8385 */ 943 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 944 } 945 946 static void 947 netmmc_config(void) 948 { 949 950 etherstix_config(); 951 basix_config(); 952 } 953 954 static void 955 wifistix_config(void) 956 { 957 958 cfstix_config(); 959 960 /* Power to Marvell 88W8385 */ 961 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 962 } 963 964 static void 965 wifistix_cf_config(void) 966 { 967 968 gxpcic_slot_irqs[1].valid = 1; 969 gxpcic_slot_irqs[1].cd = 36; 970 gxpcic_slot_irqs[1].prdy = 27; 971 972 #if 1 973 /* this configuration set by pxa2x0_pcic.c::pxapcic_attach_common() */ 974 #else 975 pxa2x0_gpio_set_function(36, GPIO_IN); /* PCD2 */ 976 pxa2x0_gpio_set_function(27, GPIO_IN); /* PRDY2/~IRQ2 */ 977 #endif 978 pxa2x0_gpio_set_function(18, GPIO_IN); /* BVD2/~STSCHG2 */ 979 980 cfstix_config(); 981 982 /* Power to Marvell 88W8385 */ 983 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 984 } 985 986 #elif defined(OVERO) 987 988 static void 989 eth0_config(void) 990 { 991 /* 992 * ETH0 connects via CS5. It use GPIO 176 for IRQ. 993 * Also GPIO 64 is NRESET. 994 */ 995 996 smsh_config(NULL, 176, 64); 997 } 998 999 static void 1000 eth1_config(void) 1001 { 1002 struct omap_mux_conf eth1_mux_conf[] = { 1003 { 0x0d2, MUXMODE(4) | INPUTENABLE }, 1004 { -1 } 1005 }; 1006 1007 /* 1008 * ETH1 connects via CS4. It use GPIO 65 for IRQ. 1009 */ 1010 1011 smsh_config(eth1_mux_conf, 65, 64); 1012 } 1013 1014 static void 1015 dvi_config(void) 1016 { 1017 static const struct omap_mux_conf overo_mux_dvi_conf[] = { 1018 { 0x0d4, MUXMODE(0) }, /* dss_pclk */ 1019 { 0x0d6, MUXMODE(0) }, /* dss_pclk */ 1020 { 0x0d8, MUXMODE(0) }, /* dss_pclk */ 1021 { 0x0da, MUXMODE(0) }, /* dss_pclk */ 1022 { 0x0dc, MUXMODE(0) }, /* dss_pclk */ 1023 { 0x0de, MUXMODE(0) }, /* dss_pclk */ 1024 { 0x0e0, MUXMODE(0) }, /* dss_pclk */ 1025 { 0x0e2, MUXMODE(0) }, /* dss_pclk */ 1026 { 0x0e4, MUXMODE(0) }, /* dss_pclk */ 1027 { 0x0e6, MUXMODE(0) }, /* dss_pclk */ 1028 { 0x0e8, MUXMODE(0) }, /* dss_pclk */ 1029 { 0x0ea, MUXMODE(0) }, /* dss_pclk */ 1030 { 0x0ec, MUXMODE(0) }, /* dss_pclk */ 1031 { 0x0ee, MUXMODE(0) }, /* dss_pclk */ 1032 { 0x0f0, MUXMODE(0) }, /* dss_pclk */ 1033 { 0x0f2, MUXMODE(0) }, /* dss_pclk */ 1034 { 0x0f4, MUXMODE(0) }, /* dss_pclk */ 1035 { 0x0f6, MUXMODE(0) }, /* dss_pclk */ 1036 { 0x0f8, MUXMODE(0) }, /* dss_pclk */ 1037 { 0x0fa, MUXMODE(0) }, /* dss_pclk */ 1038 { 0x0fc, MUXMODE(0) }, /* dss_pclk */ 1039 { 0x0fe, MUXMODE(0) }, /* dss_pclk */ 1040 { 0x100, MUXMODE(0) }, /* dss_pclk */ 1041 { 0x102, MUXMODE(0) }, /* dss_pclk */ 1042 { 0x104, MUXMODE(0) }, /* dss_pclk */ 1043 { 0x106, MUXMODE(0) }, /* dss_pclk */ 1044 { 0x108, MUXMODE(0) }, /* dss_pclk */ 1045 { 0x10a, MUXMODE(0) }, /* dss_pclk */ 1046 { -1 } 1047 }; 1048 1049 gxio_omap_mux_config(overo_mux_dvi_conf); 1050 } 1051 1052 static void 1053 lcd_config(char type) 1054 { 1055 static const struct omap_mux_conf overo_mux_mcspi1_conf[] = { 1056 { 0x1c8, MUXMODE(0) | INPUTENABLE }, /* mcspi1_clk */ 1057 { 0x1ca, MUXMODE(0) | INPUTENABLE }, /* mcspi1_simo*/ 1058 { 0x1cc, MUXMODE(0) | INPUTENABLE }, /* mcspi1_somi*/ 1059 { 0x1ce, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs0 */ 1060 { 0x1d0, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs1 */ 1061 { -1 } 1062 }; 1063 static const struct omap_mux_conf overo_mux_ads7846_conf[] = { 1064 { 0x138, /* gpio_114: NPENIRQ */ 1065 MUXMODE(4) | PULLUDENABLE | INPUTENABLE }, 1066 { -1 } 1067 }; 1068 static const struct omap_mux_conf overo_mux_lcd_conf[] = { 1069 { 0x174, MUXMODE(4) }, /* gpio_144: DISPLAY_EN */ 1070 { 0x176, MUXMODE(4) }, /* gpio_145: Brightness */ 1071 { -1 } 1072 }; 1073 1074 static const struct omap_gpio_conf overo_gpio_lcd_conf[] = { 1075 { 144, conf_output_0 }, /* DISPLAY_EN */ 1076 { 145, conf_output_0 }, /* Brightness */ 1077 { -1 } 1078 }; 1079 1080 dvi_config(); 1081 if (type != 'C') { 1082 gxio_omap_mux_config(overo_mux_mcspi1_conf); 1083 gxio_omap_mux_config(overo_mux_ads7846_conf); 1084 } 1085 gxio_omap_mux_config(overo_mux_lcd_conf); 1086 1087 gxio_omap_gpio_config(overo_gpio_lcd_conf); 1088 } 1089 1090 enum { 1091 uart1_if_exists = 0, 1092 force_uart1 1093 }; 1094 static void 1095 header_40pin_config(int uart1) 1096 { 1097 static const struct omap_mux_conf overo_mux_40pin_header_conf[] = { 1098 /* 1099 * 1: GND 1100 * 2: VCC_3.3 1101 * 3: GPIO171_SPI1_CLK 1102 * 4: GPIO114_SPI1_NIRQ 1103 * 5: GPIO172_SPI1_MOSI 1104 * 6: GPIO174_SPI1_CS0 1105 * 7: GPIO173_SPI1_MISO 1106 * 8: GPIO175_SPI1_CS1 1107 * 9: GPIO151_RXD1 1108 * 10: GPIO148_TXD1 1109 * 11: SYS_EN 1110 * 12: VBACKUP 1111 * 13: GPIO0_WAKEUP 1112 * 14: POWERON 1113 * 15: GND 1114 * 16: VCC_1.8 1115 * 17: GPIO128_GPS_PPS 1116 * 18: GPIO127_TS_IRQ 1117 * 19: GPIO170_HDQ_1WIRE 1118 * 20: GPIO163_IR_CTS3 1119 * 21: GPIO165_IR_RXD3 (console) 1120 * 22: GPIO166_IR_TXD3 (console) 1121 * 23: GPIO184_SCL3 (system eeprom) 1122 * 24: GPIO185_SDA3 (system eeprom) 1123 * 25: GND 1124 * 26: VCC_1.8 1125 * 27: GPIO146_PWM11 1126 * 28: GPIO145_PWM10 1127 * 29: GPIO147_PWM8 1128 * 30: GPIO144_PWM9 1129 * 31: PWM0 (TPS65950) 1130 * 32: PWM1 (TPS65950) 1131 * 33: ADCIN7 (TPS65950) 1132 * 34: ADCIN2 (TPS65950) 1133 * 35: ADCIN6 (TPS65950) 1134 * 36: ADCIN5 (TPS65950) 1135 * 37: AGND (TPS65950) 1136 * 38: ADCIN3 (TPS65950) 1137 * 39: ADCIN4 (TPS65950) 1138 * 40: VIN (TPS65950) 1139 */ 1140 1141 { 0x152, MUXMODE(4) | INPUTENABLE }, /* gpio_127 */ 1142 { 0x154, MUXMODE(4) | INPUTENABLE }, /* gpio_128 */ 1143 { 0x174, MUXMODE(4) | INPUTENABLE }, /* gpio_144 */ 1144 { 0x176, MUXMODE(4) | INPUTENABLE }, /* gpio_145 */ 1145 { 0x178, MUXMODE(4) | INPUTENABLE }, /* gpio_146 */ 1146 { 0x17a, MUXMODE(4) | INPUTENABLE }, /* gpio_147 */ 1147 { 0x19a, MUXMODE(4) | INPUTENABLE }, /* gpio_163 */ 1148 { -1 } 1149 }; 1150 static const struct omap_mux_conf overo_mux_uart1_conf[] = { 1151 { 0x17c, MUXMODE(0) }, /* uart1_tx */ 1152 { 0x182, MUXMODE(0) | INPUTENABLE }, /* uart1_rx */ 1153 { -1 } 1154 }; 1155 static const struct omap_mux_conf overo_mux_no_uart1_conf[] = { 1156 { 0x17c, MUXMODE(4) | INPUTENABLE }, /* gpio_148 */ 1157 { 0x182, MUXMODE(4) | INPUTENABLE }, /* gpio_151 */ 1158 { -1 } 1159 }; 1160 static const struct omap_mux_conf overo_mux_hdq_conf[] = { 1161 #if 0 1162 { 0x1c4, MUXMODE(0) | ??? | INPUTENABLE }, /* hdq_sio */ 1163 #endif 1164 { -1 } 1165 }; 1166 static const struct omap_mux_conf overo_mux_no_hdq_conf[] = { 1167 { 0x1c4, MUXMODE(4) | INPUTENABLE }, /* gpio_170 */ 1168 { -1 } 1169 }; 1170 1171 gxio_omap_mux_config(overo_mux_40pin_header_conf); 1172 if (uart1 == force_uart1) 1173 gxio_omap_mux_config(overo_mux_uart1_conf); 1174 else 1175 gxio_omap_mux_config_address("com", 0x4806a000, 1176 overo_mux_uart1_conf, overo_mux_no_uart1_conf); 1177 gxio_omap_mux_config_address("hdq", 0x480b2000, 1178 overo_mux_hdq_conf, overo_mux_no_hdq_conf); 1179 } 1180 1181 static void 1182 chestnut_config(void) 1183 { 1184 static const struct omap_mux_conf chestnut_mux_conf[] = { 1185 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1186 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1187 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1188 { -1 } 1189 }; 1190 1191 eth0_config(); 1192 lcd_config('R'); 1193 1194 header_40pin_config(uart1_if_exists); 1195 gxio_omap_mux_config(chestnut_mux_conf); 1196 } 1197 1198 static void 1199 gallop_config(void) 1200 { 1201 static const struct omap_mux_conf gallop43_mux_conf[] = { 1202 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1203 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1204 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1205 { -1 } 1206 }; 1207 1208 lcd_config('R'); 1209 1210 header_40pin_config(force_uart1); 1211 gxio_omap_mux_config(gallop43_mux_conf); 1212 } 1213 1214 static void 1215 summit_config(void) 1216 { 1217 1218 dvi_config(); 1219 1220 header_40pin_config(uart1_if_exists); 1221 } 1222 1223 static void 1224 tobi_config(void) 1225 { 1226 1227 eth0_config(); 1228 dvi_config(); 1229 1230 header_40pin_config(uart1_if_exists); 1231 } 1232 1233 static void 1234 tobiduo_config(void) 1235 { 1236 1237 eth0_config(); 1238 eth1_config(); 1239 } 1240 1241 #elif defined(DUOVERO) 1242 1243 static void 1244 ehci_config(void) 1245 { 1246 uint32_t val; 1247 1248 #define SCRM_ALTCLKSRC 0xa110 1249 #define ALTCLKSRC_ENABLE_EXT (1 << 3) 1250 #define ALTCLKSRC_ENABLE_INT (1 << 2) 1251 #define ALTCLKSRC_MODE_MASK (3 << 0) 1252 #define ALTCLKSRC_MODE_POWERDOWN (0 << 0) 1253 #define ALTCLKSRC_MODE_ACTIVE (1 << 0) 1254 #define ALTCLKSRC_MODE_BYPASS (2 << 0) 1255 #define SCRM_AUXCLK3 0xa31c 1256 #define AUXCLK3_CLKDIV(n) (((n) - 1) << 16) 1257 #define AUXCLK3_CLKDIV_MASK (0xf << 16) 1258 #define AUXCLK3_ENABLE (1 << 8) 1259 #define AUXCLK3_SRCSELECT_MASK (3 << 1) 1260 #define AUXCLK3_SRCSELECT_SYSCLK (0 << 1) 1261 #define AUXCLK3_SRCSELECT_CORE (1 << 1) 1262 #define AUXCLK3_SRCSELECT_PERDPLL (2 << 1) 1263 #define AUXCLK3_SRCSELECT_ALTCLK (3 << 1) 1264 #define AUXCLK3_POLARITY_LOW (0 << 0) 1265 #define AUXCLK3_POLARITY_HIGH (1 << 0) 1266 1267 /* Use the 1/2 auxiliary clock #3 of system clock. */ 1268 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3); 1269 val &= ~(AUXCLK3_CLKDIV_MASK | AUXCLK3_SRCSELECT_MASK); 1270 val |= (AUXCLK3_CLKDIV(2) | AUXCLK3_ENABLE | AUXCLK3_SRCSELECT_SYSCLK); 1271 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3, val); 1272 1273 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC); 1274 val &= ~ALTCLKSRC_MODE_MASK; 1275 val |= ALTCLKSRC_MODE_ACTIVE; 1276 val |= (ALTCLKSRC_ENABLE_EXT | ALTCLKSRC_ENABLE_INT); 1277 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC, val); 1278 } 1279 1280 static void 1281 parlor_config(void) 1282 { 1283 #if 0 1284 static const struct omap_mux_conf parlor_mux_40pin_header_conf[] = { 1285 /* 1286 * 1: GND 1287 * 2: GND 1288 * 3: MCSPI1_CLK or GPIO 134 1289 * 4: MCSPI1_CS0 or GPIO 137 1290 * 5: MCSPI1_SIMO or GPIO 136 1291 * 6: MCSPI1_CS1 or GPIO 138 1292 * 7: MCSPI1_SOMI or GPIO 135 1293 * 8: MCSPI1_CS2 or GPIO 139 1294 * 9: HDQ_SIO or GPIO 127 1295 * 10: MCSPI1_CS3 or GPIO 140 1296 * 11: SDMMC3_CMD or GPIO ??? 1297 * 12: I2C2_SCL or GPIO 128 1298 * 13: SDMMC3_CLK or GPIO ??? 1299 * 14: I2C2_SDA or GPIO 129 1300 * 15: UART2_TX or SDMMC3_DAT1 or GPIO 126 1301 * 16: PMIC_PWM2 (TWL6030) 1302 * 17: UART2_RX or SDMMC3_DAT0 or GPIO 125 1303 * 18: PMIC_PWM1 (TWL6030) 1304 * 19: BSP2_CLKX or GPIO 110 1305 * 20: BSP2_FSX or GPIO 113 1306 * 21: BSP2_DX or GPIO 112 1307 * 22: BSP2_DR or GPIO 111 1308 * 23: BSP2_CLKS or GPIO 118 1309 * 24: FREF1 1310 * 25: MCSPI4_SOMI or GPIO 153 1311 * 26: PMIC_NRESWARN 1312 * 27: MCSPI4_SIMO or GPIO 152 1313 * 28: SYSEN 1314 * 29: MCSPI4_CLK or GPIO 151 1315 * 30: PWRON 1316 * 31: MCSPI4_CS0 or GPIO 154 1317 * 32: REGEN1 1318 * 33: ADCIN3 (TWL6030) 1319 * 34: VCC_1.0 1320 * 35: ADCIN4_VREF (TWL6030) 1321 * 36: VDD_VAUX2 1322 * 37: ADCIN4 (TWL6030) 1323 * 38: VCC_3.3 1324 * 39: ADCIN5 (TWL6030) 1325 * 40: V_BATT_5 1326 */ 1327 { -1 } 1328 }; 1329 #endif 1330 static const struct omap_mux_conf parlor_mux_mcspi1_conf[] = { 1331 #if 0 1332 { 0x132, /* 3: MCSPI1_CLK */ 1333 MUXMODE(0) | ??? }, 1334 { 0x138, /* 4: MCSPI1_CS0 */ 1335 MUXMODE(0) | ??? }, 1336 { 0x136, /* 5: MCSPI1_SIMO */ 1337 MUXMODE(0) | ??? }, 1338 { 0x13a, /* 6: MCSPI1_CS1 */ 1339 MUXMODE(0) | ??? }, 1340 { 0x134, /* 7: MCSPI1_SOMI */ 1341 MUXMODE(0) | ??? | INPUTENABLE }, 1342 { 0x13c, /* 8: MCSPI1_CS2 */ 1343 MUXMODE(0) | ??? }, 1344 { 0x13e, /* 10: MCSPI1_CS3 */ 1345 MUXMODE(0) | ??? }, 1346 #endif 1347 { -1 } 1348 }; 1349 static const struct omap_mux_conf parlor_mux_no_mcspi1_conf[] = { 1350 { 0x132, /* 3: GPIO 134 */ 1351 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1352 { 0x138, /* 4: GPIO 137 */ 1353 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1354 { 0x136, /* 5: GPIO 136 */ 1355 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1356 { 0x13a, /* 6: GPIO 138 */ 1357 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1358 { 0x134, /* 7: GPIO 135 */ 1359 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1360 { 0x13c, /* 8: GPIO 139 */ 1361 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1362 { 0x13e, /* 10: GPIO 140 */ 1363 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1364 { -1 } 1365 }; 1366 static const struct omap_mux_conf parlor_mux_hdq_conf[] = { 1367 #if 0 1368 { 0x120, /* 9: HDQ_SIO */ 1369 MUXMODE(0) | ??? | INPUTENABLE }, 1370 #endif 1371 { -1 } 1372 }; 1373 static const struct omap_mux_conf parlor_mux_no_hdq_conf[] = { 1374 { 0x120, /* 9: GPIO_127 */ 1375 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1376 { -1 } 1377 }; 1378 static const struct omap_mux_conf parlor_mux_i2c2_conf[] = { 1379 { 0x126, /* 12: I2C2_SCL */ 1380 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1381 { 0x128, /* 14: I2C2_SDA */ 1382 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1383 { -1 } 1384 }; 1385 static const struct omap_mux_conf parlor_mux_no_i2c2_conf[] = { 1386 { 0x126, /* 12: GPIO 128 */ 1387 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1388 { 0x128, /* 14: GPIO 129 */ 1389 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1390 { -1 } 1391 }; 1392 static const struct omap_mux_conf parlor_mux_sdmmc3_conf[] = { 1393 #if 0 1394 11 SDMMC3_CMD DuoVero J2 A15 <- omap pin AG10 1395 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1396 13 SDMMC3_CLK DuoVero J2 A16 <- omap pin AE9 1397 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1398 #endif 1399 { 0x11c, /* 17: SDMMC3_DAT0 */ 1400 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1401 { 0x11e, /* 15: SDMMC3_DAT1 */ 1402 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1403 { -1 } 1404 }; 1405 static const struct omap_mux_conf parlor_mux_uart2_conf[] = { 1406 { 0x11c, /* 17: UART2_RX */ 1407 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1408 { 0x11e, 1409 MUXMODE(0) | PULLUDENABLE }, /* 15: UART2_TX */ 1410 { -1 } 1411 }; 1412 static const struct omap_mux_conf parlor_mux_no_uart2_conf[] = { 1413 { 0x11c, /* 17: GPIO 125 */ 1414 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1415 { 0x11e, /* 15: GPIO 126 */ 1416 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1417 { -1 } 1418 }; 1419 static const struct omap_mux_conf parlor_mux_bsp2_conf[] = { 1420 { 0x0f6, /* 19: BSP2_CLKX */ 1421 MUXMODE(0) | INPUTENABLE }, 1422 { 0x0fc, /* 20: BSP2_FSX */ 1423 MUXMODE(0) | INPUTENABLE }, 1424 { 0x0fa, /* 21: BSP2_DX */ 1425 MUXMODE(0) | PULLUDENABLE }, 1426 { 0x0f8, /* 22: BSP2_DR */ 1427 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1428 { 0x10e, /* 23: BSP2_CLKS */ 1429 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1430 { -1 } 1431 }; 1432 static const struct omap_mux_conf parlor_mux_no_bsp2_conf[] = { 1433 { 0x0f6, /* 19: GPIO 110 */ 1434 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1435 { 0x0fc, /* 20: GPIO 113 */ 1436 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1437 { 0x0fa, /* 21: GPIO 112 */ 1438 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1439 { 0x0f8, /* 22: GPIO 111 */ 1440 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1441 { 0x10e, /* 23: GPIO 118 */ 1442 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1443 { -1 } 1444 }; 1445 static const struct omap_mux_conf parlor_mux_mcspi4_conf[] = { 1446 #if 0 1447 { 0x158, /* 25: MCSPI4_SOMI */ 1448 MUXMODE(0) | ??? | INPUTENABLE }, 1449 { 0x156, /* 27: MCSPI4_SIMO */ 1450 MUXMODE(0) | ??? }, 1451 { 0x154, /* 29: MCSPI4_CLK */ 1452 MUXMODE(0) | ??? }, 1453 { 0x15a, /* 31: MCSPI4_CS0 */ 1454 MUXMODE(0) | ??? }, 1455 #endif 1456 { -1 } 1457 }; 1458 static const struct omap_mux_conf parlor_mux_no_mcspi4_conf[] = { 1459 { 0x158, /* 25: GPIO 153 */ 1460 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1461 { 0x156, /* 27: GPIO 152 */ 1462 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1463 { 0x154, /* 29: GPIO 151 */ 1464 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1465 { 0x15a, /* 31: GPIO 154 */ 1466 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1467 { -1 } 1468 }; 1469 1470 /* 1471 * ETH0 connects via CS5. It use GPIO 44 for IRQ. 1472 * Also GPIO 45 is NRESET. 1473 */ 1474 smsh_config(NULL, 44, 45); 1475 1476 ehci_config(); 1477 1478 gxio_omap_mux_config_address("mcspi", 0x48098000, 1479 parlor_mux_mcspi1_conf, parlor_mux_no_mcspi1_conf); 1480 gxio_omap_mux_config_address("hdq", 0x480b2000, 1481 parlor_mux_hdq_conf, parlor_mux_no_hdq_conf); 1482 gxio_omap_mux_config_address("tiiic", 0x48072000, 1483 parlor_mux_i2c2_conf, parlor_mux_no_i2c2_conf); 1484 if (gxio_omap_mux_config_address("sdhc", 0x480ad000, 1485 parlor_mux_sdmmc3_conf, NULL) != 0) 1486 gxio_omap_mux_config_address("com", 0x4806c000, 1487 parlor_mux_uart2_conf, parlor_mux_no_uart2_conf); 1488 gxio_omap_mux_config_address("mcbsp", 0x49024000, 1489 parlor_mux_bsp2_conf, parlor_mux_no_bsp2_conf); 1490 gxio_omap_mux_config_address("mcspi", 0x480ba000, 1491 parlor_mux_mcspi4_conf, parlor_mux_no_mcspi4_conf); 1492 } 1493 1494 #elif defined(PEPPER) 1495 1496 static void 1497 lcd_config(void) 1498 { 1499 static const struct tifb_panel_info panel_lcd = { 1500 .panel_tft = 1, 1501 .panel_mono = false, 1502 .panel_bpp = 24, 1503 1504 .panel_pxl_clk = 18400000, 1505 .panel_width = 480, 1506 .panel_height = 272, 1507 .panel_hfp = 8, 1508 .panel_hbp = 4, 1509 .panel_hsw = 41, 1510 .panel_vfp = 4, 1511 .panel_vbp = 2, 1512 .panel_vsw = 10, 1513 .panel_invert_hsync = 0, 1514 .panel_invert_vsync = 0, 1515 1516 .panel_ac_bias = 255, 1517 .panel_ac_bias_intrpt = 0, 1518 .panel_dma_burst_sz = 16, 1519 .panel_fdd = 0x80, 1520 .panel_sync_edge = 0, 1521 .panel_sync_ctrl = 1, 1522 .panel_tft_alt_mode = 0, 1523 .panel_invert_pxl_clk = 0, 1524 }; 1525 static const struct omap_mux_conf pepper_mux_lcd_conf[] = { 1526 /* 1527 * LCD_DATA[0-23] configures in tifb.c 1528 */ 1529 1530 { 0x8e0, MMODE(0) | PUDEN }, /* LCD_VSYNC */ 1531 { 0x8e4, MMODE(0) | PUDEN }, /* LCD_HSYNC */ 1532 { 0x8e8, MMODE(0) | PUDEN }, /* LCD_PCLK */ 1533 { 0x8ec, MMODE(0) | PUDEN }, /* LCD_AC_BIAS_EN */ 1534 1535 { 0x86c, MMODE(7) | PUTYPESEL }, /* GPIO 59: Enable */ 1536 { -1 } 1537 }; 1538 1539 if (gxio_omap_mux_config_address("tifb", 0x4830e000, 1540 pepper_mux_lcd_conf, NULL) == 0) { 1541 extern const struct tifb_panel_info *tifb_panel_info; 1542 extern bool use_tps65217_wled; 1543 1544 tifb_panel_info = &panel_lcd; 1545 use_tps65217_wled = true; 1546 } 1547 } 1548 1549 static void 1550 pepper43_config(void) 1551 { 1552 static const struct omap_mux_conf pepper43_mux_wilink8_conf[] = { 1553 /* TI WiLink 8 */ 1554 { 0x800, MMODE(7) | PUTYPESEL }, /* GPIO 32: Bluetooth */ 1555 { 0x804, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 33: irq */ 1556 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: WiFi */ 1557 { -1 } 1558 }; 1559 static const struct omap_mux_conf pepper43_mux_i2c1_conf[] = { 1560 { 0x968, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1561 { 0x96c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1562 { -1 } 1563 }; 1564 static const struct omap_mux_conf pepper43_mpu9150_conf[] = { 1565 /* MPU9150 at I2C1 */ 1566 { 0x808, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 34: IRQ */ 1567 { 0x898, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 68 */ 1568 { 0x870, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 30 */ 1569 { -1 } 1570 }; 1571 static const struct omap_mux_conf pepper43_mux_20pin_header_conf[] = { 1572 { 0x85c, MMODE(7) | PUDEN | RXACTIVE }, /* 1: GPIO 55 */ 1573 { 0x80c, MMODE(7) | PUDEN | RXACTIVE }, /* 2: GPIO 35 */ 1574 { 0x810, MMODE(7) | PUDEN | RXACTIVE }, /* 3: GPIO 36 */ 1575 { 0x814, MMODE(7) | PUDEN | RXACTIVE }, /* 4: GPIO 37 */ 1576 { 0x818, MMODE(7) | PUDEN | RXACTIVE }, /* 5: GPIO 38 */ 1577 { 0x81c, MMODE(7) | PUDEN | RXACTIVE }, /* 6: GPIO 39 */ 1578 { 0x87c, MMODE(7) | PUDEN | RXACTIVE }, /* 7: GPIO 61 */ 1579 { 0x880, MMODE(7) | PUDEN | RXACTIVE }, /* 8: GPIO 62 */ 1580 { 0x884, MMODE(7) | PUDEN | RXACTIVE }, /* 9: GPIO 63 */ 1581 { 0x9e4, MMODE(7) | PUDEN | RXACTIVE }, /* 10: GPIO 103 */ 1582 { 0x9e8, MMODE(7) | PUDEN | RXACTIVE }, /* 11: GPIO 104 */ 1583 { 0x9b0, MMODE(7) | PUDEN | RXACTIVE }, /* 12: GPIO 19 */ 1584 #if 0 /* UART3 or GPIO */ 1585 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* 13: GPIO 7 */ 1586 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* 14: GPIO 6 */ 1587 #endif 1588 #if 0 /* UART2 or GPIO */ 1589 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* 15: GPIO 98 */ 1590 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* 16: GPIO 97 */ 1591 #endif 1592 /* 17: VCC 5v */ 1593 /* 18: VCC 3.3v */ 1594 /* 19: GND */ 1595 /* 20: GND */ 1596 { -1 } 1597 }; 1598 static const struct omap_mux_conf pepper43_mux_uart2_conf[] = { 1599 { 0x90c, MMODE(6) | PUTYPESEL | RXACTIVE }, /* UART2_RXD */ 1600 { 0x910, MMODE(6) | PUDEN }, /* UART2_TXD */ 1601 { -1 } 1602 }; 1603 static const struct omap_mux_conf pepper43_mux_no_uart2_conf[] = { 1604 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 97 */ 1605 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 98 */ 1606 { -1 } 1607 }; 1608 static const struct omap_mux_conf pepper43_mux_uart3_conf[] = { 1609 { 0x960, MMODE(1) | PUTYPESEL | RXACTIVE }, /* UART3_RXD */ 1610 { 0x964, MMODE(1) | PUDEN }, /* UART3_TXD */ 1611 { -1 } 1612 }; 1613 static const struct omap_mux_conf pepper43_mux_no_uart3_conf[] = { 1614 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 6 */ 1615 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 7 */ 1616 { -1 } 1617 }; 1618 1619 static const struct omap_mux_conf *pepper43_mux_conf[] = { 1620 pepper43_mux_wilink8_conf, 1621 pepper43_mux_i2c1_conf, 1622 pepper43_mpu9150_conf, 1623 pepper43_mux_20pin_header_conf, 1624 }; 1625 1626 static const struct omap_gpio_conf pepper43_gpio_wl18xx_conf[] = { 1627 { 32, conf_output_0 }, /* #Reset: Bluetooth */ 1628 { 56, conf_output_0 }, /* #Reset: WiFi */ 1629 { -1 } 1630 }; 1631 int i; 1632 1633 lcd_config(); 1634 1635 for (i = 0; i < __arraycount(pepper43_mux_conf); i++) 1636 gxio_omap_mux_config(pepper43_mux_conf[i]); 1637 gxio_omap_gpio_config(pepper43_gpio_wl18xx_conf); 1638 1639 #if 0 1640 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 52 (Blue) */ 1641 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 20)); 1642 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1643 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 20)); 1644 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 53 (Red) */ 1645 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 21)); 1646 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1647 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 21)); 1648 #endif 1649 1650 gxio_omap_mux_config_address("com", 0x48024000, 1651 pepper43_mux_uart2_conf, pepper43_mux_no_uart2_conf); 1652 gxio_omap_mux_config_address("com", 0x481a6000, 1653 pepper43_mux_uart3_conf, pepper43_mux_no_uart3_conf); 1654 } 1655 1656 static void 1657 pepper_config(void) 1658 { 1659 static const struct omap_mux_conf pepper_mux_button2_conf[] = { 1660 { 0x85c, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 55 */ 1661 { -1 } 1662 }; 1663 static const struct omap_mux_conf pepper_mux_i2c1_conf[] = { 1664 { 0x90c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1665 { 0x910, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1666 { -1 } 1667 }; 1668 static const struct omap_mux_conf pepper_mux_wi2wi_conf[] = { 1669 { 0x9b4, MMODE(3) | PUDEN }, /* CLKOUT2 */ 1670 /* Wi2Wi */ 1671 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: nReset */ 1672 { 0x870, MMODE(7) | PUTYPESEL }, /* GPIO 30: nPower */ 1673 { -1 } 1674 }; 1675 static const struct omap_mux_conf pepper_mux_uart1_conf[] = { 1676 { 0x978, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_CTSn */ 1677 { 0x97c, MMODE(0) }, /* UART1_RTSn */ 1678 { 0x980, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_RXD */ 1679 { 0x984, MMODE(0) }, /* UART1_TXD */ 1680 { -1 } 1681 }; 1682 static const struct omap_mux_conf pepper_mux_no_uart1_conf[] = { 1683 { 0x978, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 12 */ 1684 { 0x97c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 13 */ 1685 { 0x980, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 14 */ 1686 { 0x984, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 15 */ 1687 { -1 } 1688 }; 1689 static const struct omap_mux_conf *pepper_mux_conf[] = { 1690 pepper_mux_button2_conf, 1691 pepper_mux_i2c1_conf, 1692 pepper_mux_wi2wi_conf, 1693 }; 1694 1695 int i; 1696 1697 lcd_config(); 1698 1699 for (i = 0; i < __arraycount(pepper_mux_conf); i++) 1700 gxio_omap_mux_config(pepper_mux_conf[i]); 1701 gxio_omap_mux_config_address("com", 0x48022000, 1702 pepper_mux_uart1_conf, pepper_mux_no_uart1_conf); 1703 } 1704 1705 static void 1706 c_config(void) 1707 { 1708 static const struct omap_mux_conf pepper43c_mux_ft5306_conf[] = { 1709 /* FT5306 at I2C2 */ 1710 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20 */ 1711 { 0x95c, MMODE(7) | PUDEN }, /* GPIO 5 */ 1712 { -1 } 1713 }; 1714 static const struct omap_mux_conf pepper43c_mux_i2c2_conf[] = { 1715 { 0x950, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SDA */ 1716 { 0x954, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SCL */ 1717 { -1 } 1718 }; 1719 static const struct omap_mux_conf *pepper43c_mux_conf[] = { 1720 pepper43c_mux_ft5306_conf, 1721 pepper43c_mux_i2c2_conf, 1722 }; 1723 1724 static const struct omap_gpio_conf pepper43c_gpio_ft5306_conf[] = { 1725 { 5, conf_output_0 }, /* #Reset */ 1726 { -1 } 1727 }; 1728 int i; 1729 1730 pepper43_config(); 1731 1732 for (i = 0; i < __arraycount(pepper43c_mux_conf); i++) 1733 gxio_omap_mux_config(pepper43c_mux_conf[i]); 1734 gxio_omap_gpio_config(pepper43c_gpio_ft5306_conf); 1735 } 1736 1737 static void 1738 dvi_config(void) 1739 { 1740 /* XXXX: hmm... mismatch found in Linux's dts and pubs.gumstix.org... */ 1741 1742 extern struct cfdata cfdata[]; 1743 extern const struct tifb_panel_info *tifb_panel_info; 1744 1745 static const struct tifb_panel_info panel_dvi = { 1746 .panel_tft = 1, 1747 .panel_mono = false, 1748 .panel_bpp = 16, 1749 1750 .panel_pxl_clk = 63500000, 1751 .panel_width = 1024, 1752 .panel_height = 768, 1753 .panel_hfp = 8, 1754 .panel_hbp = 4, 1755 .panel_hsw = 41, 1756 .panel_vfp = 4, 1757 .panel_vbp = 2, 1758 .panel_vsw = 10, 1759 .panel_invert_hsync = 0, 1760 .panel_invert_vsync = 0, 1761 1762 .panel_ac_bias = 255, 1763 .panel_ac_bias_intrpt = 0, 1764 .panel_dma_burst_sz = 16, 1765 .panel_fdd = 0x80, 1766 .panel_sync_edge = 0, 1767 .panel_sync_ctrl = 1, 1768 .panel_invert_pxl_clk = 0, 1769 }; 1770 cfdata_t cf = &cfdata[0]; 1771 1772 /* Disable wireless module. */ 1773 while (cf->cf_name != NULL) { 1774 if (strcmp(cf->cf_name, "sdhc") == 0 && 1775 strcmp(cf->cf_atname, "mainbus") == 0 && 1776 cf->cf_loc[MAINBUSCF_BASE] == 0x47810000) { 1777 if (cf->cf_fstate == FSTATE_NOTFOUND) 1778 cf->cf_fstate = FSTATE_DNOTFOUND; 1779 else if (cf->cf_fstate == FSTATE_STAR) 1780 cf->cf_fstate = FSTATE_DSTAR; 1781 } 1782 cf++; 1783 } 1784 1785 tifb_panel_info = &panel_dvi; 1786 } 1787 1788 static void 1789 r_config(void) 1790 { 1791 static const struct omap_mux_conf pepper43r_mux_ads7846_conf[] = { 1792 /* ADS7846 at McSPI0 */ 1793 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20: IRQ */ 1794 { -1 } 1795 }; 1796 static const struct omap_mux_conf pepper43r_mux_spi0_conf[] = { 1797 { 0x950, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_SCLK */ 1798 { 0x954, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D0 */ 1799 { 0x958, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D1 */ 1800 { 0x95c, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_CS0 */ 1801 { -1 } 1802 }; 1803 static const struct omap_mux_conf *pepper43r_mux_conf[] = { 1804 pepper43r_mux_ads7846_conf, 1805 pepper43r_mux_spi0_conf, 1806 }; 1807 int i; 1808 1809 pepper43_config(); 1810 1811 for (i = 0; i < __arraycount(pepper43r_mux_conf); i++) 1812 gxio_omap_mux_config(pepper43r_mux_conf[i]); 1813 } 1814 1815 #endif 1816 1817 #if defined(OVERO) || defined(DUOVERO) 1818 static void 1819 smsh_config(struct omap_mux_conf *smsh_mux_conf, int intr, int nreset) 1820 { 1821 struct omap_gpio_conf smsh_gpio_conf[] = { 1822 { intr, conf_input }, 1823 { nreset, conf_output_0 }, 1824 { -1 } 1825 }; 1826 1827 /* 1828 * Basically use current settings by U-Boot. 1829 * However remap physical address to configured address. 1830 */ 1831 1832 if (smsh_mux_conf != NULL) 1833 gxio_omap_mux_config(smsh_mux_conf); 1834 gxio_omap_gpio_config(smsh_gpio_conf); 1835 __udelay(100000); 1836 gxio_omap_gpio_write(nreset, 1); 1837 } 1838 #endif 1839 1840 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1841 /* 1842 * The delay for configuration time. 1843 * This function use initialized timer by U-Boot. 1844 */ 1845 static void 1846 __udelay(unsigned int usec) 1847 { 1848 #if defined(OVERO) || defined(DUOVERO) 1849 #define V_SCLK (26000000 >> 1) 1850 #define TCRR 0x28 1851 #elif defined(PEPPER) 1852 #define V_SCLK 24000000 1853 #define TCRR 0x3c 1854 #endif 1855 #define SYS_PTV 2 1856 #define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV)) 1857 1858 const vaddr_t timer_base = 1859 #if defined(OVERO) 1860 OVERO_L4_PERIPHERAL_VBASE + 0x32000; 1861 #elif defined(DUOVERO) 1862 DUOVERO_L4_PERIPHERAL_VBASE + 0x32000; 1863 #elif defined(PEPPER) 1864 PEPPER_L4_PERIPHERAL_VBASE + 0x40000; 1865 #endif 1866 long timo = usec * (TIMER_CLOCK / 1000) / 1000; 1867 uint32_t now, last; 1868 1869 last = ioreg_read(timer_base + TCRR); 1870 while (timo > 0) { 1871 now = ioreg_read(timer_base + TCRR); 1872 if (last > now) 1873 timo -= __BITS(0, 31) - last + now + 1; 1874 else 1875 timo -= now - last; 1876 last = now; 1877 } 1878 } 1879 #endif 1880 1881 #if defined(PEPPER) 1882 static int 1883 read_i2c_device(const vaddr_t i2c_base, uint16_t sa, uint8_t addr, int len, 1884 uint8_t *buf) 1885 { 1886 uint16_t v; 1887 int aok = 0, cnt = 0; 1888 1889 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1890 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1891 while (v & I2C_IRQSTATUS_BB) { 1892 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, v); 1893 __udelay(20); 1894 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1895 } 1896 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1897 1898 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1899 ioreg16_write(i2c_base + OMAP2_I2C_CNT, sizeof(addr)); 1900 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1901 I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STP | I2C_CON_STT); 1902 while (1 /*CONSTCOND*/) { 1903 __udelay(20); 1904 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1905 if ((v & I2C_IRQSTATUS_XRDY) && aok == 0) { 1906 aok = 1; 1907 ioreg16_write(i2c_base + OMAP2_I2C_DATA, addr); 1908 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1909 I2C_IRQSTATUS_XRDY); 1910 } 1911 if (v & I2C_IRQSTATUS_ARDY) { 1912 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1913 I2C_IRQSTATUS_ARDY); 1914 break; 1915 } 1916 } 1917 1918 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1919 ioreg16_write(i2c_base + OMAP2_I2C_CNT, len); 1920 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1921 I2C_CON_EN | I2C_CON_MST | I2C_CON_STP | I2C_CON_STT); 1922 while (1 /*CONSTCOND*/) { 1923 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1924 if (v & I2C_IRQSTATUS_RRDY && 1925 cnt < len) { 1926 buf[cnt++] = ioreg16_read(i2c_base + OMAP2_I2C_DATA); 1927 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1928 I2C_IRQSTATUS_RRDY); 1929 } 1930 if (v & I2C_IRQSTATUS_ARDY) { 1931 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1932 I2C_IRQSTATUS_ARDY); 1933 break; 1934 } 1935 } 1936 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1937 return 0; 1938 } 1939 #endif 1940
Indexes created Mon Oct 27 08:10:08 GMT 2025