gxio.c revision 1.21
1 /* $NetBSD: gxio.c,v 1.21 2016/10/15 15:27:18 kiyohara Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: gxio.c,v 1.21 2016/10/15 15:27:18 kiyohara Exp $"); 35 36 #include "opt_cputypes.h" 37 #include "opt_gumstix.h" 38 #include "opt_gxio.h" 39 #if defined(OVERO) 40 #include "opt_omap.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/device.h> 45 #include <sys/errno.h> 46 #include <sys/kernel.h> 47 48 #include <sys/systm.h> 49 50 #include <machine/bootconfig.h> 51 52 #include <arm/omap/omap2_gpmcreg.h> 53 #if defined(OMAP2) 54 #include <arm/omap/omap2_reg.h> 55 #if defined(OMAP3530) 56 #include <arm/omap/omap2_intr.h> 57 #endif 58 #endif 59 #include <arm/omap/omap_var.h> 60 #include <arm/omap/tifbvar.h> 61 #include <arm/omap/ti_iicreg.h> 62 #if defined(CPU_XSCALE) 63 #include <arm/xscale/pxa2x0cpu.h> 64 #endif 65 #include <arm/xscale/pxa2x0reg.h> 66 #include <arm/xscale/pxa2x0var.h> 67 #include <arm/xscale/pxa2x0_gpio.h> 68 #include <evbarm/gumstix/gumstixreg.h> 69 #include <evbarm/gumstix/gumstixvar.h> 70 71 #include "ioconf.h" 72 #include "locators.h" 73 74 75 struct gxioconf { 76 const char *name; 77 void (*config)(void); 78 }; 79 80 #if defined(GUMSTIX) 81 static int gxiomatch(device_t, cfdata_t, void *); 82 static void gxioattach(device_t, device_t, void *); 83 static int gxiosearch(device_t, cfdata_t, const int *, void *); 84 static int gxioprint(void *, const char *); 85 86 CFATTACH_DECL_NEW(gxio, sizeof(struct gxio_softc), 87 gxiomatch, gxioattach, NULL, NULL); 88 #endif 89 90 void gxio_config(void); 91 void gxio_config_expansion(char *); 92 #if defined(GUMSTIX) 93 static void basix_config(void); 94 static void cfstix_config(void); 95 static void etherstix_config(void); 96 static void netcf_config(void); 97 static void netcf_vx_config(void); 98 static void netduommc_config(void); 99 static void netduo_config(void); 100 static void netmicrosd_config(void); 101 static void netwifimicrosd_config(void); 102 static void netmmc_config(void); 103 static void wifistix_config(void); 104 static void wifistix_cf_config(void); 105 #elif defined(OVERO) 106 static void eth0_config(void); 107 static void eth1_config(void); 108 static void dvi_config(void); 109 static void lcd_config(char); 110 static void header_40pin_config(int); 111 112 static void chestnut_config(void); 113 static void gallop_config(void); 114 static void summit_config(void); 115 static void tobi_config(void); 116 static void tobiduo_config(void); 117 #elif defined(DUOVERO) 118 static void ehci_config(void); 119 120 static void parlor_config(void); 121 #elif defined(PEPPER) 122 static void lcd_config(void); 123 static void pepper43_config(void); 124 125 static void pepper_config(void); 126 static void c_config(void); 127 static void dvi_config(void); 128 static void r_config(void); 129 #endif 130 #if defined(OVERO) || defined(DUOVERO) 131 struct omap_mux_conf; 132 static void smsh_config(struct omap_mux_conf *, int, int); 133 #endif 134 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 135 static void __udelay(unsigned int); 136 #endif 137 #if defined(PEPPER) 138 static int read_i2c_device(const vaddr_t, uint16_t, uint8_t, int, uint8_t *); 139 #endif 140 141 #if defined(CPU_XSCALE_PXA250) 142 143 static struct pxa2x0_gpioconf pxa255dep_gpioconf[] = { 144 /* Bluetooth module configuration */ 145 { 7, GPIO_OUT | GPIO_SET }, /* power on */ 146 { 12, GPIO_ALT_FN_1_OUT }, /* 32kHz out. required by SingleStone */ 147 148 /* AC97 configuration */ 149 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 150 151 /* FFUART configuration */ 152 { 35, GPIO_ALT_FN_1_IN }, /* CTS */ 153 { 41, GPIO_ALT_FN_2_OUT }, /* RTS */ 154 155 #ifndef GXIO_BLUETOOTH_ON_HWUART 156 /* BTUART configuration */ 157 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 158 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 159 #else 160 /* HWUART configuration */ 161 { 42, GPIO_ALT_FN_3_IN }, /* HWRXD */ 162 { 43, GPIO_ALT_FN_3_OUT }, /* HWTXD */ 163 { 44, GPIO_ALT_FN_3_IN }, /* HWCTS */ 164 { 45, GPIO_ALT_FN_3_OUT }, /* HWRTS */ 165 #endif 166 167 #ifndef GXIO_BLUETOOTH_ON_HWUART 168 /* HWUART configuration */ 169 { 48, GPIO_ALT_FN_1_OUT }, /* HWTXD */ 170 { 49, GPIO_ALT_FN_1_IN }, /* HWRXD */ 171 { 50, GPIO_ALT_FN_1_IN }, /* HWCTS */ 172 { 51, GPIO_ALT_FN_1_OUT }, /* HWRTS */ 173 #endif 174 175 { -1 } 176 }; 177 #endif 178 #if defined(CPU_XSCALE_PXA270) 179 static struct pxa2x0_gpioconf verdexdep_gpioconf[] = { 180 /* Bluetooth module configuration */ 181 { 9, GPIO_ALT_FN_3_OUT }, /* CHOUT<0> */ 182 { 12, GPIO_OUT | GPIO_SET }, 183 184 /* LCD configuration */ 185 { 17, GPIO_IN }, /* backlight on */ 186 187 /* FFUART configuration */ 188 { 34, GPIO_ALT_FN_1_IN }, /* FFRXD */ 189 { 39, GPIO_ALT_FN_2_OUT }, /* FFTXD */ 190 191 /* BTUART configuration */ 192 { 42, GPIO_ALT_FN_1_IN }, /* BTRXD */ 193 { 43, GPIO_ALT_FN_2_OUT }, /* BTTXD */ 194 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 195 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 196 197 /* AC97 configuration */ 198 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 199 200 { -1 } 201 }; 202 203 #elif defined(OMAP2) 204 205 struct omap_mux_conf { 206 int offset; 207 uint32_t value; 208 /* OMAP3/4 register values */ 209 #define WAKEUPEVENT (1 << 15) 210 #define WAKEUPENABLE (1 << 14) 211 #define OFFMODEPULLTYPESELECT (1 << 13) 212 #define OFFMODEPULLUDENABLE (1 << 12) 213 #define OFFMODEOUTVALUE (1 << 11) 214 #define OFFMODEOUTENABLE (1 << 10) 215 #define OFFMODEENABLE (1 << 9) 216 #define INPUTENABLE (1 << 8) 217 #define PULLTYPESELECT (1 << 4) 218 #define PULLUDENABLE (1 << 3) 219 #define MUXMODE(n) ((n) & 0x7) 220 221 /* Sitara AM3xxx register values */ 222 #define SLEWCTRL (1 << 6) 223 #define RXACTIVE (1 << 5) 224 #define PUTYPESEL (1 << 4) 225 #define PUDEN (1 << 3) 226 #define MMODE(n) ((n) & 0x7) 227 }; 228 struct omap_gpio_conf { 229 int pin; 230 enum { 231 conf_input = -1, 232 conf_output_0, 233 conf_output_1, 234 } conf; 235 }; 236 237 static void gxio_omap_mux_config(const struct omap_mux_conf []); 238 static int gxio_omap_mux_config_address(const char *, unsigned long, 239 const struct omap_mux_conf[], 240 const struct omap_mux_conf[]); 241 static void gxio_omap_gpio_config(const struct omap_gpio_conf[]); 242 void gxio_omap_gpio_write(int, int); 243 244 static const struct omap_mux_conf overo_mux_i2c3_conf[] = { 245 { 0x1c2, MUXMODE(0) | INPUTENABLE }, /* i2c3_scl */ 246 { 0x1c4, MUXMODE(0) | INPUTENABLE }, /* i2c3_sda */ 247 { -1 } 248 }; 249 static const struct omap_mux_conf overo_mux_mmchs2_conf[] = { 250 { 0x158, /* mmc2_clk */ 251 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 252 { 0x15a, /* mmc2_cmd */ 253 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 254 { 0x15c, /* mmc2_dat0 */ 255 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 256 { 0x15e, /* mmc2_dat1 */ 257 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 258 { 0x160, /* mmc2_dat2 */ 259 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 260 { 0x162, /* mmc2_dat3 */ 261 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 262 { -1 } 263 }; 264 static const struct omap_mux_conf overo_mux_wireless_conf[] = { 265 { 0x0b4, MUXMODE(4) }, /* gpio_54:BT_nPOWERON*/ 266 { 0x0bc, MUXMODE(4) | INPUTENABLE }, /* gpio_58: WIFI_IRQ */ 267 { 0x19c, MUXMODE(4) }, /* gpio_164:BT_nRESET */ 268 { 0x5e0, MUXMODE(4) }, /* gpio_16: W2W_nRESET*/ 269 { -1 } 270 }; 271 272 static const struct omap_mux_conf duovero_mux_led_conf[] = { 273 { 0x116, MUXMODE(3) }, /* GPIO 122 */ 274 { -1 } 275 }; 276 static const struct omap_mux_conf duovero_mux_button_conf[] = { 277 { 0x114, /* GPIO 121 */ 278 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 279 { -1 } 280 }; 281 282 static const struct omap_mux_conf pepper_mux_led_conf[] = { 283 { 0x850, MMODE(7) | PUDEN }, /* GPIO 52: Blue */ 284 { 0x854, MMODE(7) | PUDEN }, /* GPIO 53: Red */ 285 { -1 } 286 }; 287 static const struct omap_mux_conf pepper_mux_button_conf[] = { 288 { 0x858, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 54 */ 289 { -1 } 290 }; 291 static const struct omap_mux_conf pepper_mux_mmchs3_conf[] = { 292 { 0x844, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT0 */ 293 { 0x848, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT1 */ 294 { 0x84c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT2 */ 295 { 0x878, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT3 */ 296 { 0x888, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CMD */ 297 { 0x88c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CLK */ 298 { -1 } 299 }; 300 static const struct omap_mux_conf pepper_mux_audio_codec_conf[] = { 301 { 0x840, MMODE(7) | PUDEN }, /* GPIO 48: #Reset */ 302 { -1 } 303 }; 304 305 #endif 306 307 static const struct gxioconf gxioconflist[] = { 308 #if defined(GUMSTIX) 309 { "basix", basix_config }, 310 { "cfstix", cfstix_config }, 311 { "etherstix", etherstix_config }, 312 { "netcf", netcf_config }, 313 { "netcf-vx", netcf_vx_config }, 314 { "netduo-mmc", netduommc_config }, 315 { "netduo", netduo_config }, 316 { "netmicrosd", netmicrosd_config }, 317 { "netmicrosd-vx", netmicrosd_config }, 318 { "netwifimicrosd", netwifimicrosd_config }, 319 { "netmmc", netmmc_config }, 320 { "netpro-vx", netwifimicrosd_config }, 321 { "wifistix-cf", wifistix_cf_config }, 322 { "wifistix", wifistix_config }, 323 #elif defined(OVERO) 324 { "chestnut43", chestnut_config }, 325 { "gallop43", gallop_config }, 326 { "summit", summit_config }, 327 { "tobi", tobi_config }, 328 { "tobi-duo", tobiduo_config }, 329 #elif defined(DUOVERO) 330 { "parlor", parlor_config }, 331 #elif defined(PEPPER) 332 { "43c", c_config }, 333 { "43r", r_config }, 334 { "dvi", dvi_config }, 335 #endif 336 { NULL } 337 }; 338 339 int gxpcic_gpio_reset; 340 struct gxpcic_slot_irqs gxpcic_slot_irqs[2] = { { 0, -1, -1 }, { 0, -1, -1 } }; 341 342 343 #if defined(GUMSTIX) 344 /* ARGSUSED */ 345 static int 346 gxiomatch(device_t parent, cfdata_t match, void *aux) 347 { 348 349 struct pxaip_attach_args *pxa = aux; 350 bus_space_tag_t iot = &pxa2x0_bs_tag; 351 bus_space_handle_t ioh; 352 353 if (strcmp(pxa->pxa_name, match->cf_name) != 0 || 354 pxa->pxa_addr != PXAIPCF_ADDR_DEFAULT) 355 return 0; 356 357 if (bus_space_map(iot, 358 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &ioh)) 359 return 0; 360 bus_space_unmap(iot, ioh, PXA2X0_MEMCTL_SIZE); 361 362 /* nothing */ 363 return 1; 364 } 365 366 /* ARGSUSED */ 367 static void 368 gxioattach(device_t parent, device_t self, void *aux) 369 { 370 struct gxio_softc *sc = device_private(self); 371 372 aprint_normal("\n"); 373 aprint_naive("\n"); 374 375 sc->sc_dev = self; 376 sc->sc_iot = &pxa2x0_bs_tag; 377 378 if (bus_space_map(sc->sc_iot, 379 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &sc->sc_ioh)) 380 return; 381 382 /* 383 * Attach each gumstix(busheader)/overo expansion board devices. 384 */ 385 config_search_ia(gxiosearch, self, "gxio", NULL); 386 } 387 388 /* ARGSUSED */ 389 static int 390 gxiosearch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 391 { 392 struct gxio_softc *sc = device_private(parent); 393 struct gxio_attach_args gxa; 394 395 gxa.gxa_sc = sc; 396 gxa.gxa_iot = sc->sc_iot; 397 gxa.gxa_addr = cf->cf_loc[GXIOCF_ADDR]; 398 gxa.gxa_gpirq = cf->cf_loc[GXIOCF_GPIRQ]; 399 400 if (config_match(parent, cf, &gxa)) 401 config_attach(parent, cf, &gxa, gxioprint); 402 403 return 0; 404 } 405 406 /* ARGSUSED */ 407 static int 408 gxioprint(void *aux, const char *name) 409 { 410 struct gxio_attach_args *gxa = (struct gxio_attach_args *)aux; 411 412 if (gxa->gxa_addr != GXIOCF_ADDR_DEFAULT) 413 printf(" addr 0x%lx", gxa->gxa_addr); 414 if (gxa->gxa_gpirq > 0) 415 printf(" gpirq %d", gxa->gxa_gpirq); 416 return UNCONF; 417 } 418 #endif 419 420 421 #if defined(GUMSTIX) 422 /* 423 * configure for GPIO pin and expansion boards. 424 */ 425 void 426 gxio_config(void) 427 { 428 #if defined(CPU_XSCALE_PXA250) 429 struct pxa2x0_gpioconf *gumstix_gpioconf[] = { 430 pxa25x_com_ffuart_gpioconf, 431 pxa25x_com_stuart_gpioconf, 432 #ifndef GXIO_BLUETOOTH_ON_HWUART 433 pxa25x_com_btuart_gpioconf, 434 #endif 435 pxa25x_com_hwuart_gpioconf, 436 pxa25x_i2c_gpioconf, 437 pxa25x_pxaacu_gpioconf, 438 pxa255dep_gpioconf, 439 NULL 440 }; 441 #endif 442 #if defined(CPU_XSCALE_PXA270) 443 struct pxa2x0_gpioconf *verdex_gpioconf[] = { 444 pxa27x_com_ffuart_gpioconf, 445 pxa27x_com_stuart_gpioconf, 446 pxa27x_com_btuart_gpioconf, 447 pxa27x_i2c_gpioconf, 448 pxa27x_pxaacu_gpioconf, 449 pxa27x_pxamci_gpioconf, 450 pxa27x_ohci_gpioconf, 451 verdexdep_gpioconf, 452 NULL 453 }; 454 #endif 455 456 /* XXX: turn off for power of bluetooth module */ 457 #if defined(CPU_XSCALE_PXA250) 458 pxa2x0_gpio_set_function(7, GPIO_OUT | GPIO_CLR); 459 #elif defined(CPU_XSCALE_PXA270) 460 pxa2x0_gpio_set_function(12, GPIO_OUT | GPIO_CLR); 461 #endif 462 delay(100); 463 464 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 465 pxa2x0_gpio_config( 466 (CPU_IS_PXA250) ? gumstix_gpioconf : verdex_gpioconf); 467 #elif defined(CPU_XSCALE_PXA270) || defined(CPU_XSCALE_PXA250) 468 #if defined(CPU_XSCALE_PXA270) 469 pxa2x0_gpio_config(verdex_gpioconf); 470 #else 471 pxa2x0_gpio_config(gumstix_gpioconf); 472 #endif 473 #endif 474 } 475 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 476 static void 477 gxio_omap_mux_config(const struct omap_mux_conf mux_conf[]) 478 { 479 #if defined(OVERO) 480 const vaddr_t ctrlmod_base = OVERO_L4_CORE_VBASE + 0x2000; 481 #elif defined(DUOVERO) 482 const vaddr_t ctrlmod_base = DUOVERO_L4_CM_VBASE; 483 #elif defined(PEPPER) 484 const vaddr_t ctrlmod_base = PEPPER_PRCM_VBASE + 0x10000; 485 #endif 486 int i; 487 488 for (i = 0; mux_conf[i].offset != -1; i++) 489 #if !defined(TI_AM335X) 490 ioreg16_write(ctrlmod_base + mux_conf[i].offset, 491 mux_conf[i].value); 492 #else 493 ioreg_write(ctrlmod_base + mux_conf[i].offset, 494 mux_conf[i].value); 495 #endif 496 } 497 498 static int 499 gxio_omap_mux_config_address(const char *name, unsigned long address, 500 const struct omap_mux_conf mux_conf[], 501 const struct omap_mux_conf not_mux_conf[]) 502 { 503 extern struct cfdata cfdata[]; 504 cfdata_t cf = &cfdata[0]; 505 506 while (cf->cf_name != NULL) { 507 if (strcmp(name, cf->cf_name) == 0 && 508 address == cf->cf_loc[OBIOCF_ADDR]) { 509 gxio_omap_mux_config(mux_conf); 510 return 0; 511 } 512 cf++; 513 } 514 515 if (not_mux_conf == NULL) 516 return -1; 517 518 gxio_omap_mux_config(not_mux_conf); 519 return 0; 520 } 521 522 #if defined(OVERO) 523 #define gpio_reg_read ioreg_read 524 #define gpio_reg_write ioreg_write 525 #elif defined(DUOVERO) || defined(PEPPER) 526 #define gpio_reg_read(a) ioreg_read((a) + GPIO_SIZE2) 527 #define gpio_reg_write(a, v) ioreg_write((a) + GPIO_SIZE2, (v)) 528 #endif 529 530 static const vaddr_t gpio_bases[] = { 531 #if defined(OVERO) 532 #define OVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 533 #define GPIO(n) GPIO ## n ## _BASE_3530 534 #define BASE(a, n) \ 535 (OVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP3530_L4_ ## a ## _BASE)) 536 537 GPIO1_BASE_3530, 538 GPIO2_BASE_3530, 539 GPIO3_BASE_3530, 540 GPIO4_BASE_3530, 541 GPIO5_BASE_3530, 542 GPIO6_BASE_3530, 543 544 #elif defined(DUOVERO) 545 #define DUOVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 546 #define GPIO(n) GPIO ## n ## _BASE_4430 547 #define BASE(a, n) \ 548 (DUOVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP4430_L4_ ## a ## _BASE)) 549 550 DUOVERO_GPIO_VBASE(1), 551 DUOVERO_GPIO_VBASE(2), 552 DUOVERO_GPIO_VBASE(3), 553 DUOVERO_GPIO_VBASE(4), 554 DUOVERO_GPIO_VBASE(5), 555 556 #elif defined(PEPPER) 557 #define PEPPER_GPIO_VBASE(n) ((n) == 0 ? WAKEUP(n) : PERIPHERAL(n)) 558 #define GPIO(n) GPIO ## n ## _BASE_TI_AM335X 559 #define WAKEUP(n) (PEPPER_PRCM_VBASE + (GPIO(n) - OMAP2_CM_BASE)) 560 #define PERIPHERAL(n) \ 561 (PEPPER_L4_PERIPHERAL_VBASE + (GPIO(n) - TI_AM335X_L4_PERIPHERAL_BASE)) 562 563 PEPPER_GPIO_VBASE(0), 564 PEPPER_GPIO_VBASE(1), 565 PEPPER_GPIO_VBASE(2), 566 PEPPER_GPIO_VBASE(3), 567 #endif 568 }; 569 570 static void 571 gxio_omap_gpio_config(const struct omap_gpio_conf gpio_conf[]) 572 { 573 vaddr_t gpio_base; 574 int mask, i; 575 576 for (i = 0; gpio_conf[i].pin != -1; i++) { 577 gpio_base = gpio_bases[gpio_conf[i].pin / 32]; 578 mask = 1 << (gpio_conf[i].pin % 32); 579 switch (gpio_conf[i].conf) { 580 case conf_input: 581 ioreg_write(gpio_base + GPIO_OE, 582 ioreg_read(gpio_base + GPIO_OE) | mask); 583 break; 584 case conf_output_0: 585 ioreg_write(gpio_base + GPIO_OE, 586 ioreg_read(gpio_base + GPIO_OE) | ~mask); 587 #if 0 588 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 589 #else 590 ioreg_write(gpio_base + GPIO_DATAOUT, 591 ioreg_read(gpio_base + GPIO_DATAOUT) & ~mask); 592 #endif 593 break; 594 case conf_output_1: 595 ioreg_write(gpio_base + GPIO_OE, 596 ioreg_read(gpio_base + GPIO_OE) | ~mask); 597 #if 0 598 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 599 #else 600 ioreg_write(gpio_base + GPIO_DATAOUT, 601 ioreg_read(gpio_base + GPIO_DATAOUT) | mask); 602 #endif 603 break; 604 } 605 } 606 } 607 608 void 609 gxio_omap_gpio_write(int pin, int val) 610 { 611 vaddr_t gpio_base; 612 int mask; 613 614 KASSERT(pin / 32 < __arraycount(gpio_bases)); 615 616 gpio_base = gpio_bases[pin / 32]; 617 mask = 1 << (pin % 32); 618 if (val == 0) 619 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 620 else 621 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 622 } 623 624 /* 625 * configure for MUX, GPIO. 626 */ 627 void 628 gxio_config(void) 629 { 630 const struct omap_mux_conf *mux_conf[] = { 631 #if defined(OVERO) 632 overo_mux_i2c3_conf, 633 overo_mux_mmchs2_conf, 634 overo_mux_wireless_conf, 635 #elif defined(DUOVERO) 636 duovero_mux_led_conf, 637 duovero_mux_button_conf, 638 #elif defined(PEPPER) 639 pepper_mux_led_conf, 640 pepper_mux_button_conf, 641 pepper_mux_mmchs3_conf, 642 pepper_mux_audio_codec_conf, 643 #endif 644 }; 645 const struct omap_gpio_conf gpio_conf[] = { 646 #if defined(OVERO) 647 { 16, conf_output_0 }, /* Wireless: #Reset */ 648 #elif defined(PEPPER) 649 { 48, conf_output_0 }, /* Audio Codec: #Reset */ 650 #endif 651 { -1 } 652 }; 653 int i; 654 655 for (i = 0; i < __arraycount(mux_conf); i++) 656 gxio_omap_mux_config(mux_conf[i]); 657 gxio_omap_gpio_config(gpio_conf); 658 } 659 #endif 660 661 void 662 gxio_config_expansion(char *expansion) 663 { 664 int i, d, s; 665 666 if (expansion == NULL) { 667 printf("not specified 'expansion=' in the boot args.\n"); 668 s = -1; 669 } else { 670 for (i = 0; gxioconflist[i].name != NULL; i++) 671 if (strncasecmp(gxioconflist[i].name, expansion, 672 strlen(gxioconflist[i].name) + 1) == 0) 673 break; 674 if (gxioconflist[i].name == NULL) 675 printf("unknown expansion specified: %s\n", expansion); 676 s = i; 677 } 678 #ifdef GXIO_DEFAULT_EXPANSION 679 for (i = 0; gxioconflist[i].name != NULL; i++) 680 if (strncasecmp(gxioconflist[i].name, GXIO_DEFAULT_EXPANSION, 681 strlen(gxioconflist[i].name) + 1) == 0) 682 break; 683 d = i; 684 #else 685 d = -1; 686 #endif 687 printf("supported expansions:\n"); 688 for (i = 0; gxioconflist[i].name != NULL; i++) 689 printf(" %s%s\n", 690 gxioconflist[i].name, 691 i == d ? " (DEFAULT)" : ""); 692 693 if (s < 0 || gxioconflist[i].name == NULL) { 694 #ifdef GXIO_DEFAULT_EXPANSION 695 expansion = __UNCONST(GXIO_DEFAULT_EXPANSION); 696 #else 697 return; 698 #endif 699 } 700 701 #if defined(PEPPER) 702 if (s < 0) { 703 struct pepper_board_id { 704 unsigned int device_vendor; 705 #define GUMSTIX_PEPPER 0x30000200 /* 1st gen */ 706 #define GUMSTIX_PEPPER_DVI 0x31000200 /* DVI and newer */ 707 unsigned char revision; 708 unsigned char content; 709 char fab_revision[8]; 710 char env_var[16]; 711 char env_setting[64]; 712 } id; 713 const vaddr_t i2c_base = PEPPER_PRCM_VBASE + 0xb000; 714 const uint8_t eeprom = 0x50; 715 const uint8_t len = sizeof(id); 716 int rv; 717 718 rv = read_i2c_device(i2c_base, eeprom, 0x00, len, (void *)&id); 719 if (rv == 0) 720 if (id.device_vendor == GUMSTIX_PEPPER) { 721 printf("configure auto detected expansion" 722 " (pepper)\n"); 723 pepper_config(); 724 return; 725 } 726 } 727 #endif 728 729 printf("configure %s expansion (%s)\n", 730 (s < 0 || gxioconflist[i].name == NULL) ? "default" : "specified", 731 expansion); 732 gxioconflist[(s < 0 || gxioconflist[i].name == NULL) ? d : s].config(); 733 } 734 735 736 #if defined(GUMSTIX) 737 738 static void 739 basix_config(void) 740 { 741 742 pxa2x0_gpio_set_function(8, GPIO_ALT_FN_1_OUT); /* MMCCS0 */ 743 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_1_OUT); /* MMCCLK */ 744 #if 0 745 /* this configuration set by gxmci.c::pxamci_attach() */ 746 pxa2x0_gpio_set_function(11, GPIO_IN); /* nSD_DETECT */ 747 pxa2x0_gpio_set_function(22, GPIO_IN); /* nSD_WP */ 748 #endif 749 } 750 751 static void 752 cfstix_config(void) 753 { 754 u_int gpio, npoe_fn; 755 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 756 int bvd = (CPU_IS_PXA250) ? 4 : 111; 757 #else 758 #if defined(CPU_XSCALE_PXA270) 759 const int bvd = 111; 760 #else 761 const int bvd = 4; 762 #endif 763 #endif 764 765 if (CPU_IS_PXA250) { 766 gxpcic_slot_irqs[0].valid = 1; 767 gxpcic_slot_irqs[0].cd = 11; 768 gxpcic_slot_irqs[0].prdy = 26; 769 gxpcic_gpio_reset = 8; 770 } else { 771 gxpcic_slot_irqs[0].valid = 1; 772 gxpcic_slot_irqs[0].cd = 104; 773 gxpcic_slot_irqs[0].prdy = 96; 774 gxpcic_gpio_reset = 97; 775 } 776 777 #if 1 778 /* PCD/PRDY set by pxa2x0_pcic.c::pxapcic_attach_common() */ 779 #else 780 pxa2x0_gpio_set_function(11, GPIO_IN); /* PCD1 */ 781 pxa2x0_gpio_set_function(26, GPIO_IN); /* PRDY1/~IRQ1 */ 782 #endif 783 pxa2x0_gpio_set_function(bvd, GPIO_IN); /* BVD1/~STSCHG1 */ 784 785 for (gpio = 48, npoe_fn = 0; gpio <= 53 ; gpio++) 786 npoe_fn |= pxa2x0_gpio_get_function(gpio); 787 npoe_fn &= GPIO_SET; 788 789 pxa2x0_gpio_set_function(48, GPIO_ALT_FN_2_OUT | npoe_fn); /* nPOE */ 790 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 791 pxa2x0_gpio_set_function(50, GPIO_ALT_FN_2_OUT); /* nPIOR */ 792 pxa2x0_gpio_set_function(51, GPIO_ALT_FN_2_OUT); /* nPIOW */ 793 if (CPU_IS_PXA250) { 794 pxa2x0_gpio_set_function(52, GPIO_ALT_FN_2_OUT); /* nPCE1 */ 795 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_2_OUT); /* nPCE2 */ 796 pxa2x0_gpio_set_function(54, GPIO_ALT_FN_2_OUT); /* pSKTSEL */ 797 } else { 798 pxa2x0_gpio_set_function(102, GPIO_ALT_FN_1_OUT); /* nPCE1 */ 799 pxa2x0_gpio_set_function(105, GPIO_ALT_FN_1_OUT); /* nPCE2 */ 800 pxa2x0_gpio_set_function(79, GPIO_ALT_FN_1_OUT); /* pSKTSEL */ 801 } 802 pxa2x0_gpio_set_function(55, GPIO_ALT_FN_2_OUT); /* nPREG */ 803 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); /* nPWAIT */ 804 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); /* nIOIS16 */ 805 } 806 807 static void 808 etherstix_config(void) 809 { 810 extern struct cfdata cfdata[]; 811 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 812 int rst = (CPU_IS_PXA250) ? 80 : 32; 813 int irq = (CPU_IS_PXA250) ? 36 : 99; 814 #else 815 #if defined(CPU_XSCALE_PXA270) 816 const int rst = 32, irq = 99; 817 #else 818 const int rst = 80, irq = 36; 819 #endif 820 #endif 821 int i; 822 823 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 824 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 825 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_SET); /* RESET 1 */ 826 delay(1); 827 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_CLR); 828 delay(50000); 829 830 for (i = 0; cfdata[i].cf_name != NULL; i++) 831 if (strcmp(cfdata[i].cf_name, "sm") == 0 && 832 strcmp(cfdata[i].cf_atname, "sm_gxio") == 0 && 833 cfdata[i].cf_loc[GXIOCF_ADDR] == 0x04000300 && 834 cfdata[i].cf_loc[GXIOCF_GPIRQ] == GXIOCF_GPIRQ_DEFAULT) 835 cfdata[i].cf_loc[GXIOCF_GPIRQ] = irq; 836 } 837 838 static void 839 netcf_config(void) 840 { 841 842 etherstix_config(); 843 cfstix_config(); 844 } 845 846 static void 847 netcf_vx_config(void) 848 { 849 850 /* 851 * XXXX: More power is necessary for NIC and USB??? 852 * (no document. from Linux) 853 */ 854 855 pxa2x0_gpio_set_function(27, GPIO_IN); 856 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); 857 pxa2x0_gpio_set_function(118, GPIO_ALT_FN_1_IN | GPIO_CLR); 858 859 etherstix_config(); 860 cfstix_config(); 861 if (CPU_IS_PXA270) { 862 /* Overwrite */ 863 gxpcic_slot_irqs[0].cd = 104; 864 gxpcic_slot_irqs[0].prdy = 109; 865 gxpcic_gpio_reset = 110; 866 }; 867 } 868 869 static void 870 netduommc_config(void) 871 { 872 873 netduo_config(); 874 basix_config(); 875 } 876 877 static void 878 netduo_config(void) 879 { 880 881 etherstix_config(); 882 883 pxa2x0_gpio_set_function(78, GPIO_ALT_FN_2_OUT); /* nCS 2 */ 884 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_SET); /* RESET 2 */ 885 delay(1); 886 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_CLR); 887 delay(50000); 888 } 889 890 static void 891 netmicrosd_config(void) 892 { 893 894 /* MicroSD(mci) always configure on PXA270 */ 895 896 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 897 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 898 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); /* RESET 1 */ 899 delay(hz / 2); 900 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_SET); 901 delay(50000); 902 } 903 904 static void 905 netwifimicrosd_config(void) 906 { 907 908 netmicrosd_config(); 909 910 cfstix_config(); 911 /* However use pxamci. */ 912 pxa2x0_gpio_set_function(111, GPIO_CLR | GPIO_ALT_FN_1_IN); 913 /* Power to Marvell 88W8385 */ 914 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 915 } 916 917 static void 918 netmmc_config(void) 919 { 920 921 etherstix_config(); 922 basix_config(); 923 } 924 925 static void 926 wifistix_config(void) 927 { 928 929 cfstix_config(); 930 931 /* Power to Marvell 88W8385 */ 932 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 933 } 934 935 static void 936 wifistix_cf_config(void) 937 { 938 939 gxpcic_slot_irqs[1].valid = 1; 940 gxpcic_slot_irqs[1].cd = 36; 941 gxpcic_slot_irqs[1].prdy = 27; 942 943 #if 1 944 /* this configuration set by pxa2x0_pcic.c::pxapcic_attach_common() */ 945 #else 946 pxa2x0_gpio_set_function(36, GPIO_IN); /* PCD2 */ 947 pxa2x0_gpio_set_function(27, GPIO_IN); /* PRDY2/~IRQ2 */ 948 #endif 949 pxa2x0_gpio_set_function(18, GPIO_IN); /* BVD2/~STSCHG2 */ 950 951 cfstix_config(); 952 953 /* Power to Marvell 88W8385 */ 954 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 955 } 956 957 #elif defined(OVERO) 958 959 static void 960 eth0_config(void) 961 { 962 /* 963 * ETH0 connects via CS5. It use GPIO 176 for IRQ. 964 * Also GPIO 64 is NRESET. 965 */ 966 967 smsh_config(NULL, 176, 64); 968 } 969 970 static void 971 eth1_config(void) 972 { 973 struct omap_mux_conf eth1_mux_conf[] = { 974 { 0x0d2, MUXMODE(4) | INPUTENABLE }, 975 { -1 } 976 }; 977 978 /* 979 * ETH1 connects via CS4. It use GPIO 65 for IRQ. 980 */ 981 982 smsh_config(eth1_mux_conf, 65, 64); 983 } 984 985 static void 986 dvi_config(void) 987 { 988 static const struct omap_mux_conf overo_mux_dvi_conf[] = { 989 { 0x0d4, MUXMODE(0) }, /* dss_pclk */ 990 { 0x0d6, MUXMODE(0) }, /* dss_pclk */ 991 { 0x0d8, MUXMODE(0) }, /* dss_pclk */ 992 { 0x0da, MUXMODE(0) }, /* dss_pclk */ 993 { 0x0dc, MUXMODE(0) }, /* dss_pclk */ 994 { 0x0de, MUXMODE(0) }, /* dss_pclk */ 995 { 0x0e0, MUXMODE(0) }, /* dss_pclk */ 996 { 0x0e2, MUXMODE(0) }, /* dss_pclk */ 997 { 0x0e4, MUXMODE(0) }, /* dss_pclk */ 998 { 0x0e6, MUXMODE(0) }, /* dss_pclk */ 999 { 0x0e8, MUXMODE(0) }, /* dss_pclk */ 1000 { 0x0ea, MUXMODE(0) }, /* dss_pclk */ 1001 { 0x0ec, MUXMODE(0) }, /* dss_pclk */ 1002 { 0x0ee, MUXMODE(0) }, /* dss_pclk */ 1003 { 0x0f0, MUXMODE(0) }, /* dss_pclk */ 1004 { 0x0f2, MUXMODE(0) }, /* dss_pclk */ 1005 { 0x0f4, MUXMODE(0) }, /* dss_pclk */ 1006 { 0x0f6, MUXMODE(0) }, /* dss_pclk */ 1007 { 0x0f8, MUXMODE(0) }, /* dss_pclk */ 1008 { 0x0fa, MUXMODE(0) }, /* dss_pclk */ 1009 { 0x0fc, MUXMODE(0) }, /* dss_pclk */ 1010 { 0x0fe, MUXMODE(0) }, /* dss_pclk */ 1011 { 0x100, MUXMODE(0) }, /* dss_pclk */ 1012 { 0x102, MUXMODE(0) }, /* dss_pclk */ 1013 { 0x104, MUXMODE(0) }, /* dss_pclk */ 1014 { 0x106, MUXMODE(0) }, /* dss_pclk */ 1015 { 0x108, MUXMODE(0) }, /* dss_pclk */ 1016 { 0x10a, MUXMODE(0) }, /* dss_pclk */ 1017 { -1 } 1018 }; 1019 1020 gxio_omap_mux_config(overo_mux_dvi_conf); 1021 } 1022 1023 static void 1024 lcd_config(char type) 1025 { 1026 static const struct omap_mux_conf overo_mux_mcspi1_conf[] = { 1027 { 0x1c8, MUXMODE(0) | INPUTENABLE }, /* mcspi1_clk */ 1028 { 0x1ca, MUXMODE(0) | INPUTENABLE }, /* mcspi1_simo*/ 1029 { 0x1cc, MUXMODE(0) | INPUTENABLE }, /* mcspi1_somi*/ 1030 { 0x1ce, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs0 */ 1031 { 0x1d0, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs1 */ 1032 { -1 } 1033 }; 1034 static const struct omap_mux_conf overo_mux_ads7846_conf[] = { 1035 { 0x138, /* gpio_114: NPENIRQ */ 1036 MUXMODE(4) | PULLUDENABLE | INPUTENABLE }, 1037 { -1 } 1038 }; 1039 static const struct omap_mux_conf overo_mux_lcd_conf[] = { 1040 { 0x174, MUXMODE(4) }, /* gpio_144: DISPLAY_EN */ 1041 { 0x176, MUXMODE(4) }, /* gpio_145: Brightness */ 1042 { -1 } 1043 }; 1044 1045 static const struct omap_gpio_conf overo_gpio_lcd_conf[] = { 1046 { 144, conf_output_0 }, /* DISPLAY_EN */ 1047 { 145, conf_output_0 }, /* Brightness */ 1048 { -1 } 1049 }; 1050 1051 dvi_config(); 1052 if (type != 'C') { 1053 gxio_omap_mux_config(overo_mux_mcspi1_conf); 1054 gxio_omap_mux_config(overo_mux_ads7846_conf); 1055 } 1056 gxio_omap_mux_config(overo_mux_lcd_conf); 1057 1058 gxio_omap_gpio_config(overo_gpio_lcd_conf); 1059 } 1060 1061 enum { 1062 uart1_if_exists = 0, 1063 force_uart1 1064 }; 1065 static void 1066 header_40pin_config(int uart1) 1067 { 1068 static const struct omap_mux_conf overo_mux_40pin_header_conf[] = { 1069 /* 1070 * 1: GND 1071 * 2: VCC_3.3 1072 * 3: GPIO171_SPI1_CLK 1073 * 4: GPIO114_SPI1_NIRQ 1074 * 5: GPIO172_SPI1_MOSI 1075 * 6: GPIO174_SPI1_CS0 1076 * 7: GPIO173_SPI1_MISO 1077 * 8: GPIO175_SPI1_CS1 1078 * 9: GPIO151_RXD1 1079 * 10: GPIO148_TXD1 1080 * 11: SYS_EN 1081 * 12: VBACKUP 1082 * 13: GPIO0_WAKEUP 1083 * 14: POWERON 1084 * 15: GND 1085 * 16: VCC_1.8 1086 * 17: GPIO128_GPS_PPS 1087 * 18: GPIO127_TS_IRQ 1088 * 19: GPIO170_HDQ_1WIRE 1089 * 20: GPIO163_IR_CTS3 1090 * 21: GPIO165_IR_RXD3 (console) 1091 * 22: GPIO166_IR_TXD3 (console) 1092 * 23: GPIO184_SCL3 (system eeprom) 1093 * 24: GPIO185_SDA3 (system eeprom) 1094 * 25: GND 1095 * 26: VCC_1.8 1096 * 27: GPIO146_PWM11 1097 * 28: GPIO145_PWM10 1098 * 29: GPIO147_PWM8 1099 * 30: GPIO144_PWM9 1100 * 31: PWM0 (TPS65950) 1101 * 32: PWM1 (TPS65950) 1102 * 33: ADCIN7 (TPS65950) 1103 * 34: ADCIN2 (TPS65950) 1104 * 35: ADCIN6 (TPS65950) 1105 * 36: ADCIN5 (TPS65950) 1106 * 37: AGND (TPS65950) 1107 * 38: ADCIN3 (TPS65950) 1108 * 39: ADCIN4 (TPS65950) 1109 * 40: VIN (TPS65950) 1110 */ 1111 1112 { 0x152, MUXMODE(4) | INPUTENABLE }, /* gpio_127 */ 1113 { 0x154, MUXMODE(4) | INPUTENABLE }, /* gpio_128 */ 1114 { 0x174, MUXMODE(4) | INPUTENABLE }, /* gpio_144 */ 1115 { 0x176, MUXMODE(4) | INPUTENABLE }, /* gpio_145 */ 1116 { 0x178, MUXMODE(4) | INPUTENABLE }, /* gpio_146 */ 1117 { 0x17a, MUXMODE(4) | INPUTENABLE }, /* gpio_147 */ 1118 { 0x19a, MUXMODE(4) | INPUTENABLE }, /* gpio_163 */ 1119 { -1 } 1120 }; 1121 static const struct omap_mux_conf overo_mux_uart1_conf[] = { 1122 { 0x17c, MUXMODE(0) }, /* uart1_tx */ 1123 { 0x182, MUXMODE(0) | INPUTENABLE }, /* uart1_rx */ 1124 { -1 } 1125 }; 1126 static const struct omap_mux_conf overo_mux_no_uart1_conf[] = { 1127 { 0x17c, MUXMODE(4) | INPUTENABLE }, /* gpio_148 */ 1128 { 0x182, MUXMODE(4) | INPUTENABLE }, /* gpio_151 */ 1129 { -1 } 1130 }; 1131 static const struct omap_mux_conf overo_mux_hdq_conf[] = { 1132 #if 0 1133 { 0x1c4, MUXMODE(0) | ??? | INPUTENABLE }, /* hdq_sio */ 1134 #endif 1135 { -1 } 1136 }; 1137 static const struct omap_mux_conf overo_mux_no_hdq_conf[] = { 1138 { 0x1c4, MUXMODE(4) | INPUTENABLE }, /* gpio_170 */ 1139 { -1 } 1140 }; 1141 1142 gxio_omap_mux_config(overo_mux_40pin_header_conf); 1143 if (uart1 == force_uart1) 1144 gxio_omap_mux_config(overo_mux_uart1_conf); 1145 else 1146 gxio_omap_mux_config_address("com", 0x4806a000, 1147 overo_mux_uart1_conf, overo_mux_no_uart1_conf); 1148 gxio_omap_mux_config_address("hdq", 0x480b2000, 1149 overo_mux_hdq_conf, overo_mux_no_hdq_conf); 1150 } 1151 1152 static void 1153 chestnut_config(void) 1154 { 1155 static const struct omap_mux_conf chestnut_mux_conf[] = { 1156 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1157 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1158 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1159 { -1 } 1160 }; 1161 1162 eth0_config(); 1163 lcd_config('R'); 1164 1165 header_40pin_config(uart1_if_exists); 1166 gxio_omap_mux_config(chestnut_mux_conf); 1167 } 1168 1169 static void 1170 gallop_config(void) 1171 { 1172 static const struct omap_mux_conf gallop43_mux_conf[] = { 1173 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1174 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1175 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1176 { -1 } 1177 }; 1178 1179 lcd_config('R'); 1180 1181 header_40pin_config(force_uart1); 1182 gxio_omap_mux_config(gallop43_mux_conf); 1183 } 1184 1185 static void 1186 summit_config(void) 1187 { 1188 1189 dvi_config(); 1190 1191 header_40pin_config(uart1_if_exists); 1192 } 1193 1194 static void 1195 tobi_config(void) 1196 { 1197 1198 eth0_config(); 1199 dvi_config(); 1200 1201 header_40pin_config(uart1_if_exists); 1202 } 1203 1204 static void 1205 tobiduo_config(void) 1206 { 1207 1208 eth0_config(); 1209 eth1_config(); 1210 } 1211 1212 #elif defined(DUOVERO) 1213 1214 static void 1215 ehci_config(void) 1216 { 1217 uint32_t val; 1218 1219 #define SCRM_ALTCLKSRC 0xa110 1220 #define ALTCLKSRC_ENABLE_EXT (1 << 3) 1221 #define ALTCLKSRC_ENABLE_INT (1 << 2) 1222 #define ALTCLKSRC_MODE_MASK (3 << 0) 1223 #define ALTCLKSRC_MODE_POWERDOWN (0 << 0) 1224 #define ALTCLKSRC_MODE_ACTIVE (1 << 0) 1225 #define ALTCLKSRC_MODE_BYPASS (2 << 0) 1226 #define SCRM_AUXCLK3 0xa31c 1227 #define AUXCLK3_CLKDIV(n) (((n) - 1) << 16) 1228 #define AUXCLK3_CLKDIV_MASK (0xf << 16) 1229 #define AUXCLK3_ENABLE (1 << 8) 1230 #define AUXCLK3_SRCSELECT_MASK (3 << 1) 1231 #define AUXCLK3_SRCSELECT_SYSCLK (0 << 1) 1232 #define AUXCLK3_SRCSELECT_CORE (1 << 1) 1233 #define AUXCLK3_SRCSELECT_PERDPLL (2 << 1) 1234 #define AUXCLK3_SRCSELECT_ALTCLK (3 << 1) 1235 #define AUXCLK3_POLARITY_LOW (0 << 0) 1236 #define AUXCLK3_POLARITY_HIGH (1 << 0) 1237 1238 /* Use the 1/2 auxiliary clock #3 of system clock. */ 1239 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3); 1240 val &= ~(AUXCLK3_CLKDIV_MASK | AUXCLK3_SRCSELECT_MASK); 1241 val |= (AUXCLK3_CLKDIV(2) | AUXCLK3_ENABLE | AUXCLK3_SRCSELECT_SYSCLK); 1242 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3, val); 1243 1244 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC); 1245 val &= ~ALTCLKSRC_MODE_MASK; 1246 val |= ALTCLKSRC_MODE_ACTIVE; 1247 val |= (ALTCLKSRC_ENABLE_EXT | ALTCLKSRC_ENABLE_INT); 1248 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC, val); 1249 } 1250 1251 static void 1252 parlor_config(void) 1253 { 1254 #if 0 1255 static const struct omap_mux_conf parlor_mux_40pin_header_conf[] = { 1256 /* 1257 * 1: GND 1258 * 2: GND 1259 * 3: MCSPI1_CLK or GPIO 134 1260 * 4: MCSPI1_CS0 or GPIO 137 1261 * 5: MCSPI1_SIMO or GPIO 136 1262 * 6: MCSPI1_CS1 or GPIO 138 1263 * 7: MCSPI1_SOMI or GPIO 135 1264 * 8: MCSPI1_CS2 or GPIO 139 1265 * 9: HDQ_SIO or GPIO 127 1266 * 10: MCSPI1_CS3 or GPIO 140 1267 * 11: SDMMC3_CMD or GPIO ??? 1268 * 12: I2C2_SCL or GPIO 128 1269 * 13: SDMMC3_CLK or GPIO ??? 1270 * 14: I2C2_SDA or GPIO 129 1271 * 15: UART2_TX or SDMMC3_DAT1 or GPIO 126 1272 * 16: PMIC_PWM2 (TWL6030) 1273 * 17: UART2_RX or SDMMC3_DAT0 or GPIO 125 1274 * 18: PMIC_PWM1 (TWL6030) 1275 * 19: BSP2_CLKX or GPIO 110 1276 * 20: BSP2_FSX or GPIO 113 1277 * 21: BSP2_DX or GPIO 112 1278 * 22: BSP2_DR or GPIO 111 1279 * 23: BSP2_CLKS or GPIO 118 1280 * 24: FREF1 1281 * 25: MCSPI4_SOMI or GPIO 153 1282 * 26: PMIC_NRESWARN 1283 * 27: MCSPI4_SIMO or GPIO 152 1284 * 28: SYSEN 1285 * 29: MCSPI4_CLK or GPIO 151 1286 * 30: PWRON 1287 * 31: MCSPI4_CS0 or GPIO 154 1288 * 32: REGEN1 1289 * 33: ADCIN3 (TWL6030) 1290 * 34: VCC_1.0 1291 * 35: ADCIN4_VREF (TWL6030) 1292 * 36: VDD_VAUX2 1293 * 37: ADCIN4 (TWL6030) 1294 * 38: VCC_3.3 1295 * 39: ADCIN5 (TWL6030) 1296 * 40: V_BATT_5 1297 */ 1298 { -1 } 1299 }; 1300 #endif 1301 static const struct omap_mux_conf parlor_mux_mcspi1_conf[] = { 1302 #if 0 1303 { 0x132, /* 3: MCSPI1_CLK */ 1304 MUXMODE(0) | ??? }, 1305 { 0x138, /* 4: MCSPI1_CS0 */ 1306 MUXMODE(0) | ??? }, 1307 { 0x136, /* 5: MCSPI1_SIMO */ 1308 MUXMODE(0) | ??? }, 1309 { 0x13a, /* 6: MCSPI1_CS1 */ 1310 MUXMODE(0) | ??? }, 1311 { 0x134, /* 7: MCSPI1_SOMI */ 1312 MUXMODE(0) | ??? | INPUTENABLE }, 1313 { 0x13c, /* 8: MCSPI1_CS2 */ 1314 MUXMODE(0) | ??? }, 1315 { 0x13e, /* 10: MCSPI1_CS3 */ 1316 MUXMODE(0) | ??? }, 1317 #endif 1318 { -1 } 1319 }; 1320 static const struct omap_mux_conf parlor_mux_no_mcspi1_conf[] = { 1321 { 0x132, /* 3: GPIO 134 */ 1322 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1323 { 0x138, /* 4: GPIO 137 */ 1324 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1325 { 0x136, /* 5: GPIO 136 */ 1326 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1327 { 0x13a, /* 6: GPIO 138 */ 1328 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1329 { 0x134, /* 7: GPIO 135 */ 1330 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1331 { 0x13c, /* 8: GPIO 139 */ 1332 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1333 { 0x13e, /* 10: GPIO 140 */ 1334 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1335 { -1 } 1336 }; 1337 static const struct omap_mux_conf parlor_mux_hdq_conf[] = { 1338 #if 0 1339 { 0x120, /* 9: HDQ_SIO */ 1340 MUXMODE(0) | ??? | INPUTENABLE }, 1341 #endif 1342 { -1 } 1343 }; 1344 static const struct omap_mux_conf parlor_mux_no_hdq_conf[] = { 1345 { 0x120, /* 9: GPIO_127 */ 1346 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1347 { -1 } 1348 }; 1349 static const struct omap_mux_conf parlor_mux_i2c2_conf[] = { 1350 { 0x126, /* 12: I2C2_SCL */ 1351 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1352 { 0x128, /* 14: I2C2_SDA */ 1353 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1354 { -1 } 1355 }; 1356 static const struct omap_mux_conf parlor_mux_no_i2c2_conf[] = { 1357 { 0x126, /* 12: GPIO 128 */ 1358 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1359 { 0x128, /* 14: GPIO 129 */ 1360 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1361 { -1 } 1362 }; 1363 static const struct omap_mux_conf parlor_mux_sdmmc3_conf[] = { 1364 #if 0 1365 11 SDMMC3_CMD DuoVero J2 A15 <- omap pin AG10 1366 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1367 13 SDMMC3_CLK DuoVero J2 A16 <- omap pin AE9 1368 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1369 #endif 1370 { 0x11c, /* 17: SDMMC3_DAT0 */ 1371 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1372 { 0x11e, /* 15: SDMMC3_DAT1 */ 1373 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1374 { -1 } 1375 }; 1376 static const struct omap_mux_conf parlor_mux_uart2_conf[] = { 1377 { 0x11c, /* 17: UART2_RX */ 1378 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1379 { 0x11e, 1380 MUXMODE(0) | PULLUDENABLE }, /* 15: UART2_TX */ 1381 { -1 } 1382 }; 1383 static const struct omap_mux_conf parlor_mux_no_uart2_conf[] = { 1384 { 0x11c, /* 17: GPIO 125 */ 1385 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1386 { 0x11e, /* 15: GPIO 126 */ 1387 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1388 { -1 } 1389 }; 1390 static const struct omap_mux_conf parlor_mux_bsp2_conf[] = { 1391 { 0x0f6, /* 19: BSP2_CLKX */ 1392 MUXMODE(0) | INPUTENABLE }, 1393 { 0x0fc, /* 20: BSP2_FSX */ 1394 MUXMODE(0) | INPUTENABLE }, 1395 { 0x0fa, /* 21: BSP2_DX */ 1396 MUXMODE(0) | PULLUDENABLE }, 1397 { 0x0f8, /* 22: BSP2_DR */ 1398 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1399 { 0x10e, /* 23: BSP2_CLKS */ 1400 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1401 { -1 } 1402 }; 1403 static const struct omap_mux_conf parlor_mux_no_bsp2_conf[] = { 1404 { 0x0f6, /* 19: GPIO 110 */ 1405 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1406 { 0x0fc, /* 20: GPIO 113 */ 1407 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1408 { 0x0fa, /* 21: GPIO 112 */ 1409 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1410 { 0x0f8, /* 22: GPIO 111 */ 1411 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1412 { 0x10e, /* 23: GPIO 118 */ 1413 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1414 { -1 } 1415 }; 1416 static const struct omap_mux_conf parlor_mux_mcspi4_conf[] = { 1417 #if 0 1418 { 0x158, /* 25: MCSPI4_SOMI */ 1419 MUXMODE(0) | ??? | INPUTENABLE }, 1420 { 0x156, /* 27: MCSPI4_SIMO */ 1421 MUXMODE(0) | ??? }, 1422 { 0x154, /* 29: MCSPI4_CLK */ 1423 MUXMODE(0) | ??? }, 1424 { 0x15a, /* 31: MCSPI4_CS0 */ 1425 MUXMODE(0) | ??? }, 1426 #endif 1427 { -1 } 1428 }; 1429 static const struct omap_mux_conf parlor_mux_no_mcspi4_conf[] = { 1430 { 0x158, /* 25: GPIO 153 */ 1431 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1432 { 0x156, /* 27: GPIO 152 */ 1433 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1434 { 0x154, /* 29: GPIO 151 */ 1435 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1436 { 0x15a, /* 31: GPIO 154 */ 1437 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1438 { -1 } 1439 }; 1440 1441 /* 1442 * ETH0 connects via CS5. It use GPIO 44 for IRQ. 1443 * Also GPIO 45 is NRESET. 1444 */ 1445 smsh_config(NULL, 44, 45); 1446 1447 ehci_config(); 1448 1449 gxio_omap_mux_config_address("mcspi", 0x48098000, 1450 parlor_mux_mcspi1_conf, parlor_mux_no_mcspi1_conf); 1451 gxio_omap_mux_config_address("hdq", 0x480b2000, 1452 parlor_mux_hdq_conf, parlor_mux_no_hdq_conf); 1453 gxio_omap_mux_config_address("tiiic", 0x48072000, 1454 parlor_mux_i2c2_conf, parlor_mux_no_i2c2_conf); 1455 if (gxio_omap_mux_config_address("sdhc", 0x480ad000, 1456 parlor_mux_sdmmc3_conf, NULL) != 0) 1457 gxio_omap_mux_config_address("com", 0x4806c000, 1458 parlor_mux_uart2_conf, parlor_mux_no_uart2_conf); 1459 gxio_omap_mux_config_address("mcbsp", 0x49024000, 1460 parlor_mux_bsp2_conf, parlor_mux_no_bsp2_conf); 1461 gxio_omap_mux_config_address("mcspi", 0x480ba000, 1462 parlor_mux_mcspi4_conf, parlor_mux_no_mcspi4_conf); 1463 } 1464 1465 #elif defined(PEPPER) 1466 1467 static void 1468 lcd_config(void) 1469 { 1470 static const struct tifb_panel_info panel_lcd = { 1471 .panel_tft = 1, 1472 .panel_mono = false, 1473 .panel_bpp = 24, 1474 1475 .panel_pxl_clk = 18400000, 1476 .panel_width = 480, 1477 .panel_height = 272, 1478 .panel_hfp = 8, 1479 .panel_hbp = 4, 1480 .panel_hsw = 41, 1481 .panel_vfp = 4, 1482 .panel_vbp = 2, 1483 .panel_vsw = 10, 1484 .panel_invert_hsync = 0, 1485 .panel_invert_vsync = 0, 1486 1487 .panel_ac_bias = 255, 1488 .panel_ac_bias_intrpt = 0, 1489 .panel_dma_burst_sz = 16, 1490 .panel_fdd = 0x80, 1491 .panel_sync_edge = 0, 1492 .panel_sync_ctrl = 1, 1493 .panel_tft_alt_mode = 0, 1494 .panel_invert_pxl_clk = 0, 1495 }; 1496 static const struct omap_mux_conf pepper_mux_lcd_conf[] = { 1497 /* 1498 * LCD_DATA[0-23] configures in tifb.c 1499 */ 1500 1501 { 0x8e0, MMODE(0) | PUDEN }, /* LCD_VSYNC */ 1502 { 0x8e4, MMODE(0) | PUDEN }, /* LCD_HSYNC */ 1503 { 0x8e8, MMODE(0) | PUDEN }, /* LCD_PCLK */ 1504 { 0x8ec, MMODE(0) | PUDEN }, /* LCD_AC_BIAS_EN */ 1505 1506 { 0x86c, MMODE(7) | PUTYPESEL }, /* GPIO 59: Enable */ 1507 { -1 } 1508 }; 1509 1510 if (gxio_omap_mux_config_address("tifb", 0x4830e000, 1511 pepper_mux_lcd_conf, NULL) == 0) { 1512 extern const struct tifb_panel_info *tifb_panel_info; 1513 extern bool use_tps65217_wled; 1514 1515 tifb_panel_info = &panel_lcd; 1516 use_tps65217_wled = true; 1517 } 1518 } 1519 1520 static void 1521 pepper43_config(void) 1522 { 1523 static const struct omap_mux_conf pepper43_mux_wilink8_conf[] = { 1524 /* TI WiLink 8 */ 1525 { 0x800, MMODE(7) | PUTYPESEL }, /* GPIO 32: Bluetooth */ 1526 { 0x804, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 33: irq */ 1527 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: WiFi */ 1528 { -1 } 1529 }; 1530 static const struct omap_mux_conf pepper43_mux_i2c1_conf[] = { 1531 { 0x968, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1532 { 0x96c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1533 { -1 } 1534 }; 1535 static const struct omap_mux_conf pepper43_mpu9150_conf[] = { 1536 /* MPU9150 at I2C1 */ 1537 { 0x808, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 34: IRQ */ 1538 { 0x898, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 68 */ 1539 { 0x870, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 30 */ 1540 { -1 } 1541 }; 1542 static const struct omap_mux_conf pepper43_mux_20pin_header_conf[] = { 1543 { 0x85c, MMODE(7) | PUDEN | RXACTIVE }, /* 1: GPIO 55 */ 1544 { 0x80c, MMODE(7) | PUDEN | RXACTIVE }, /* 2: GPIO 35 */ 1545 { 0x810, MMODE(7) | PUDEN | RXACTIVE }, /* 3: GPIO 36 */ 1546 { 0x814, MMODE(7) | PUDEN | RXACTIVE }, /* 4: GPIO 37 */ 1547 { 0x818, MMODE(7) | PUDEN | RXACTIVE }, /* 5: GPIO 38 */ 1548 { 0x81c, MMODE(7) | PUDEN | RXACTIVE }, /* 6: GPIO 39 */ 1549 { 0x87c, MMODE(7) | PUDEN | RXACTIVE }, /* 7: GPIO 61 */ 1550 { 0x880, MMODE(7) | PUDEN | RXACTIVE }, /* 8: GPIO 62 */ 1551 { 0x884, MMODE(7) | PUDEN | RXACTIVE }, /* 9: GPIO 63 */ 1552 { 0x9e4, MMODE(7) | PUDEN | RXACTIVE }, /* 10: GPIO 103 */ 1553 { 0x9e8, MMODE(7) | PUDEN | RXACTIVE }, /* 11: GPIO 104 */ 1554 { 0x9b0, MMODE(7) | PUDEN | RXACTIVE }, /* 12: GPIO 19 */ 1555 #if 0 /* UART3 or GPIO */ 1556 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* 13: GPIO 7 */ 1557 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* 14: GPIO 6 */ 1558 #endif 1559 #if 0 /* UART2 or GPIO */ 1560 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* 15: GPIO 98 */ 1561 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* 16: GPIO 97 */ 1562 #endif 1563 /* 17: VCC 5v */ 1564 /* 18: VCC 3.3v */ 1565 /* 19: GND */ 1566 /* 20: GND */ 1567 { -1 } 1568 }; 1569 static const struct omap_mux_conf pepper43_mux_uart2_conf[] = { 1570 { 0x90c, MMODE(6) | PUTYPESEL | RXACTIVE }, /* UART2_RXD */ 1571 { 0x910, MMODE(6) | PUDEN }, /* UART2_TXD */ 1572 { -1 } 1573 }; 1574 static const struct omap_mux_conf pepper43_mux_no_uart2_conf[] = { 1575 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 97 */ 1576 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 98 */ 1577 { -1 } 1578 }; 1579 static const struct omap_mux_conf pepper43_mux_uart3_conf[] = { 1580 { 0x960, MMODE(1) | PUTYPESEL | RXACTIVE }, /* UART3_RXD */ 1581 { 0x964, MMODE(1) | PUDEN }, /* UART3_TXD */ 1582 { -1 } 1583 }; 1584 static const struct omap_mux_conf pepper43_mux_no_uart3_conf[] = { 1585 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 6 */ 1586 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 7 */ 1587 { -1 } 1588 }; 1589 1590 static const struct omap_mux_conf *pepper43_mux_conf[] = { 1591 pepper43_mux_wilink8_conf, 1592 pepper43_mux_i2c1_conf, 1593 pepper43_mpu9150_conf, 1594 pepper43_mux_20pin_header_conf, 1595 }; 1596 1597 static const struct omap_gpio_conf pepper43_gpio_wl18xx_conf[] = { 1598 { 32, conf_output_0 }, /* #Reset: Bluetooth */ 1599 { 56, conf_output_0 }, /* #Reset: WiFi */ 1600 { -1 } 1601 }; 1602 int i; 1603 1604 lcd_config(); 1605 1606 for (i = 0; i < __arraycount(pepper43_mux_conf); i++) 1607 gxio_omap_mux_config(pepper43_mux_conf[i]); 1608 gxio_omap_gpio_config(pepper43_gpio_wl18xx_conf); 1609 1610 #if 0 1611 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 52 (Blue) */ 1612 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 20)); 1613 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1614 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 20)); 1615 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 53 (Red) */ 1616 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 21)); 1617 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1618 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 21)); 1619 #endif 1620 1621 gxio_omap_mux_config_address("com", 0x48024000, 1622 pepper43_mux_uart2_conf, pepper43_mux_no_uart2_conf); 1623 gxio_omap_mux_config_address("com", 0x481a6000, 1624 pepper43_mux_uart3_conf, pepper43_mux_no_uart3_conf); 1625 } 1626 1627 static void 1628 pepper_config(void) 1629 { 1630 static const struct omap_mux_conf pepper_mux_button2_conf[] = { 1631 { 0x85c, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 55 */ 1632 { -1 } 1633 }; 1634 static const struct omap_mux_conf pepper_mux_i2c1_conf[] = { 1635 { 0x90c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1636 { 0x910, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1637 { -1 } 1638 }; 1639 static const struct omap_mux_conf pepper_mux_wi2wi_conf[] = { 1640 { 0x9b4, MMODE(3) | PUDEN }, /* CLKOUT2 */ 1641 /* Wi2Wi */ 1642 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: nReset */ 1643 { 0x870, MMODE(7) | PUTYPESEL }, /* GPIO 30: nPower */ 1644 { -1 } 1645 }; 1646 static const struct omap_mux_conf pepper_mux_uart1_conf[] = { 1647 { 0x978, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_CTSn */ 1648 { 0x97c, MMODE(0) }, /* UART1_RTSn */ 1649 { 0x980, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_RXD */ 1650 { 0x984, MMODE(0) }, /* UART1_TXD */ 1651 { -1 } 1652 }; 1653 static const struct omap_mux_conf pepper_mux_no_uart1_conf[] = { 1654 { 0x978, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 12 */ 1655 { 0x97c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 13 */ 1656 { 0x980, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 14 */ 1657 { 0x984, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 15 */ 1658 { -1 } 1659 }; 1660 static const struct omap_mux_conf *pepper_mux_conf[] = { 1661 pepper_mux_button2_conf, 1662 pepper_mux_i2c1_conf, 1663 pepper_mux_wi2wi_conf, 1664 }; 1665 1666 int i; 1667 1668 lcd_config(); 1669 1670 for (i = 0; i < __arraycount(pepper_mux_conf); i++) 1671 gxio_omap_mux_config(pepper_mux_conf[i]); 1672 gxio_omap_mux_config_address("com", 0x48022000, 1673 pepper_mux_uart1_conf, pepper_mux_no_uart1_conf); 1674 } 1675 1676 static void 1677 c_config(void) 1678 { 1679 static const struct omap_mux_conf pepper43c_mux_ft5306_conf[] = { 1680 /* FT5306 at I2C2 */ 1681 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20 */ 1682 { 0x95c, MMODE(7) | PUDEN }, /* GPIO 5 */ 1683 { -1 } 1684 }; 1685 static const struct omap_mux_conf pepper43c_mux_i2c2_conf[] = { 1686 { 0x950, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SDA */ 1687 { 0x954, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SCL */ 1688 { -1 } 1689 }; 1690 static const struct omap_mux_conf *pepper43c_mux_conf[] = { 1691 pepper43c_mux_ft5306_conf, 1692 pepper43c_mux_i2c2_conf, 1693 }; 1694 1695 static const struct omap_gpio_conf pepper43c_gpio_ft5306_conf[] = { 1696 { 5, conf_output_0 }, /* #Reset */ 1697 { -1 } 1698 }; 1699 int i; 1700 1701 pepper43_config(); 1702 1703 for (i = 0; i < __arraycount(pepper43c_mux_conf); i++) 1704 gxio_omap_mux_config(pepper43c_mux_conf[i]); 1705 gxio_omap_gpio_config(pepper43c_gpio_ft5306_conf); 1706 } 1707 1708 static void 1709 dvi_config(void) 1710 { 1711 /* XXXX: hmm... mismatch found in Linux's dts and pubs.gumstix.org... */ 1712 1713 extern struct cfdata cfdata[]; 1714 extern const struct tifb_panel_info *tifb_panel_info; 1715 1716 static const struct tifb_panel_info panel_dvi = { 1717 .panel_tft = 1, 1718 .panel_mono = false, 1719 .panel_bpp = 16, 1720 1721 .panel_pxl_clk = 63500000, 1722 .panel_width = 1024, 1723 .panel_height = 768, 1724 .panel_hfp = 8, 1725 .panel_hbp = 4, 1726 .panel_hsw = 41, 1727 .panel_vfp = 4, 1728 .panel_vbp = 2, 1729 .panel_vsw = 10, 1730 .panel_invert_hsync = 0, 1731 .panel_invert_vsync = 0, 1732 1733 .panel_ac_bias = 255, 1734 .panel_ac_bias_intrpt = 0, 1735 .panel_dma_burst_sz = 16, 1736 .panel_fdd = 0x80, 1737 .panel_sync_edge = 0, 1738 .panel_sync_ctrl = 1, 1739 .panel_invert_pxl_clk = 0, 1740 }; 1741 cfdata_t cf = &cfdata[0]; 1742 1743 /* Disable wireless module. */ 1744 while (cf->cf_name != NULL) { 1745 if (strcmp(cf->cf_name, "sdhc") == 0 && 1746 strcmp(cf->cf_atname, "mainbus") == 0 && 1747 cf->cf_loc[MAINBUSCF_BASE] == 0x47810000) { 1748 if (cf->cf_fstate == FSTATE_NOTFOUND) 1749 cf->cf_fstate = FSTATE_DNOTFOUND; 1750 else if (cf->cf_fstate == FSTATE_STAR) 1751 cf->cf_fstate = FSTATE_DSTAR; 1752 } 1753 cf++; 1754 } 1755 1756 tifb_panel_info = &panel_dvi; 1757 } 1758 1759 static void 1760 r_config(void) 1761 { 1762 static const struct omap_mux_conf pepper43r_mux_ads7846_conf[] = { 1763 /* ADS7846 at McSPI0 */ 1764 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20: IRQ */ 1765 { -1 } 1766 }; 1767 static const struct omap_mux_conf pepper43r_mux_spi0_conf[] = { 1768 { 0x950, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_SCLK */ 1769 { 0x954, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D0 */ 1770 { 0x958, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D1 */ 1771 { 0x95c, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_CS0 */ 1772 { -1 } 1773 }; 1774 static const struct omap_mux_conf *pepper43r_mux_conf[] = { 1775 pepper43r_mux_ads7846_conf, 1776 pepper43r_mux_spi0_conf, 1777 }; 1778 int i; 1779 1780 pepper43_config(); 1781 1782 for (i = 0; i < __arraycount(pepper43r_mux_conf); i++) 1783 gxio_omap_mux_config(pepper43r_mux_conf[i]); 1784 } 1785 1786 #endif 1787 1788 #if defined(OVERO) || defined(DUOVERO) 1789 static void 1790 smsh_config(struct omap_mux_conf *smsh_mux_conf, int intr, int nreset) 1791 { 1792 struct omap_gpio_conf smsh_gpio_conf[] = { 1793 { intr, conf_input }, 1794 { nreset, conf_output_0 }, 1795 { -1 } 1796 }; 1797 1798 /* 1799 * Basically use current settings by U-Boot. 1800 * However remap physical address to configured address. 1801 */ 1802 1803 if (smsh_mux_conf != NULL) 1804 gxio_omap_mux_config(smsh_mux_conf); 1805 gxio_omap_gpio_config(smsh_gpio_conf); 1806 __udelay(100000); 1807 gxio_omap_gpio_write(nreset, 1); 1808 } 1809 #endif 1810 1811 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1812 /* 1813 * The delay for configuration time. 1814 * This function use initialized timer by U-Boot. 1815 */ 1816 static void 1817 __udelay(unsigned int usec) 1818 { 1819 #if defined(OVERO) || defined(DUOVERO) 1820 #define V_SCLK (26000000 >> 1) 1821 #define TCRR 0x28 1822 #elif defined(PEPPER) 1823 #define V_SCLK 24000000 1824 #define TCRR 0x3c 1825 #endif 1826 #define SYS_PTV 2 1827 #define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV)) 1828 1829 const vaddr_t timer_base = 1830 #if defined(OVERO) 1831 OVERO_L4_PERIPHERAL_VBASE + 0x32000; 1832 #elif defined(DUOVERO) 1833 DUOVERO_L4_PERIPHERAL_VBASE + 0x32000; 1834 #elif defined(PEPPER) 1835 PEPPER_L4_PERIPHERAL_VBASE + 0x40000; 1836 #endif 1837 long timo = usec * (TIMER_CLOCK / 1000) / 1000; 1838 uint32_t now, last; 1839 1840 last = ioreg_read(timer_base + TCRR); 1841 while (timo > 0) { 1842 now = ioreg_read(timer_base + TCRR); 1843 if (last > now) 1844 timo -= __BITS(0, 31) - last + now + 1; 1845 else 1846 timo -= now - last; 1847 last = now; 1848 } 1849 } 1850 #endif 1851 1852 #if defined(PEPPER) 1853 static int 1854 read_i2c_device(const vaddr_t i2c_base, uint16_t sa, uint8_t addr, int len, 1855 uint8_t *buf) 1856 { 1857 uint16_t v; 1858 int aok = 0, cnt = 0; 1859 1860 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1861 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1862 while (v & I2C_IRQSTATUS_BB) { 1863 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, v); 1864 __udelay(20); 1865 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1866 } 1867 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1868 1869 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1870 ioreg16_write(i2c_base + OMAP2_I2C_CNT, sizeof(addr)); 1871 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1872 I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STP | I2C_CON_STT); 1873 while (1 /*CONSTCOND*/) { 1874 __udelay(20); 1875 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1876 if ((v & I2C_IRQSTATUS_XRDY) && aok == 0) { 1877 aok = 1; 1878 ioreg16_write(i2c_base + OMAP2_I2C_DATA, addr); 1879 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1880 I2C_IRQSTATUS_XRDY); 1881 } 1882 if (v & I2C_IRQSTATUS_ARDY) { 1883 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1884 I2C_IRQSTATUS_ARDY); 1885 break; 1886 } 1887 } 1888 1889 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1890 ioreg16_write(i2c_base + OMAP2_I2C_CNT, len); 1891 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1892 I2C_CON_EN | I2C_CON_MST | I2C_CON_STP | I2C_CON_STT); 1893 while (1 /*CONSTCOND*/) { 1894 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1895 if (v & I2C_IRQSTATUS_RRDY && 1896 cnt < len) { 1897 buf[cnt++] = ioreg16_read(i2c_base + OMAP2_I2C_DATA); 1898 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1899 I2C_IRQSTATUS_RRDY); 1900 } 1901 if (v & I2C_IRQSTATUS_ARDY) { 1902 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1903 I2C_IRQSTATUS_ARDY); 1904 break; 1905 } 1906 } 1907 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1908 return 0; 1909 } 1910 #endif 1911
Indexes created Mon Sep 29 21:09:56 GMT 2025