gxio.c revision 1.22
1 /* $NetBSD: gxio.c,v 1.22 2016/10/16 13:54:28 kiyohara Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: gxio.c,v 1.22 2016/10/16 13:54:28 kiyohara Exp $"); 35 36 #include "opt_cputypes.h" 37 #include "opt_gumstix.h" 38 #include "opt_gxio.h" 39 #if defined(OVERO) 40 #include "opt_omap.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/device.h> 45 #include <sys/errno.h> 46 #include <sys/kernel.h> 47 48 #include <sys/systm.h> 49 50 #include <machine/bootconfig.h> 51 52 #include <arm/omap/omap2_gpmcreg.h> 53 #if defined(OMAP2) 54 #include <arm/omap/omap2_reg.h> 55 #if defined(OMAP3530) 56 #include <arm/omap/omap2_intr.h> 57 #endif 58 #endif 59 #include <arm/omap/omap_var.h> 60 #include <arm/omap/ti_iicreg.h> 61 #if defined(CPU_XSCALE) 62 #include <arm/xscale/pxa2x0cpu.h> 63 #endif 64 #include <arm/xscale/pxa2x0reg.h> 65 #include <arm/xscale/pxa2x0var.h> 66 #include <arm/xscale/pxa2x0_gpio.h> 67 #include <evbarm/gumstix/gumstixreg.h> 68 #include <evbarm/gumstix/gumstixvar.h> 69 70 #include "ioconf.h" 71 #include "locators.h" 72 73 74 struct gxioconf { 75 const char *name; 76 void (*config)(void); 77 }; 78 79 #if defined(GUMSTIX) 80 static int gxiomatch(device_t, cfdata_t, void *); 81 static void gxioattach(device_t, device_t, void *); 82 static int gxiosearch(device_t, cfdata_t, const int *, void *); 83 static int gxioprint(void *, const char *); 84 85 CFATTACH_DECL_NEW(gxio, sizeof(struct gxio_softc), 86 gxiomatch, gxioattach, NULL, NULL); 87 #endif 88 89 void gxio_config(void); 90 void gxio_config_expansion(char *); 91 #if defined(GUMSTIX) 92 static void basix_config(void); 93 static void cfstix_config(void); 94 static void etherstix_config(void); 95 static void netcf_config(void); 96 static void netcf_vx_config(void); 97 static void netduommc_config(void); 98 static void netduo_config(void); 99 static void netmicrosd_config(void); 100 static void netwifimicrosd_config(void); 101 static void netmmc_config(void); 102 static void wifistix_config(void); 103 static void wifistix_cf_config(void); 104 #elif defined(OVERO) 105 static void eth0_config(void); 106 static void eth1_config(void); 107 static void dvi_config(void); 108 static void lcd_config(char); 109 static void header_40pin_config(int); 110 111 static void chestnut_config(void); 112 static void gallop_config(void); 113 static void summit_config(void); 114 static void tobi_config(void); 115 static void tobiduo_config(void); 116 #elif defined(DUOVERO) 117 static void ehci_config(void); 118 119 static void parlor_config(void); 120 #elif defined(PEPPER) 121 static void lcd_config(void); 122 static void pepper43_config(void); 123 124 static void pepper_config(void); 125 static void c_config(void); 126 static void dvi_config(void); 127 static void r_config(void); 128 #endif 129 #if defined(OVERO) || defined(DUOVERO) 130 struct omap_mux_conf; 131 static void smsh_config(struct omap_mux_conf *, int, int); 132 #endif 133 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 134 static void __udelay(unsigned int); 135 #endif 136 #if defined(PEPPER) 137 static int read_i2c_device(const vaddr_t, uint16_t, uint8_t, int, uint8_t *); 138 #endif 139 140 #if defined(CPU_XSCALE_PXA250) 141 142 static struct pxa2x0_gpioconf pxa255dep_gpioconf[] = { 143 /* Bluetooth module configuration */ 144 { 7, GPIO_OUT | GPIO_SET }, /* power on */ 145 { 12, GPIO_ALT_FN_1_OUT }, /* 32kHz out. required by SingleStone */ 146 147 /* AC97 configuration */ 148 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 149 150 /* FFUART configuration */ 151 { 35, GPIO_ALT_FN_1_IN }, /* CTS */ 152 { 41, GPIO_ALT_FN_2_OUT }, /* RTS */ 153 154 #ifndef GXIO_BLUETOOTH_ON_HWUART 155 /* BTUART configuration */ 156 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 157 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 158 #else 159 /* HWUART configuration */ 160 { 42, GPIO_ALT_FN_3_IN }, /* HWRXD */ 161 { 43, GPIO_ALT_FN_3_OUT }, /* HWTXD */ 162 { 44, GPIO_ALT_FN_3_IN }, /* HWCTS */ 163 { 45, GPIO_ALT_FN_3_OUT }, /* HWRTS */ 164 #endif 165 166 #ifndef GXIO_BLUETOOTH_ON_HWUART 167 /* HWUART configuration */ 168 { 48, GPIO_ALT_FN_1_OUT }, /* HWTXD */ 169 { 49, GPIO_ALT_FN_1_IN }, /* HWRXD */ 170 { 50, GPIO_ALT_FN_1_IN }, /* HWCTS */ 171 { 51, GPIO_ALT_FN_1_OUT }, /* HWRTS */ 172 #endif 173 174 { -1 } 175 }; 176 #endif 177 #if defined(CPU_XSCALE_PXA270) 178 static struct pxa2x0_gpioconf verdexdep_gpioconf[] = { 179 /* Bluetooth module configuration */ 180 { 9, GPIO_ALT_FN_3_OUT }, /* CHOUT<0> */ 181 { 12, GPIO_OUT | GPIO_SET }, 182 183 /* LCD configuration */ 184 { 17, GPIO_IN }, /* backlight on */ 185 186 /* FFUART configuration */ 187 { 34, GPIO_ALT_FN_1_IN }, /* FFRXD */ 188 { 39, GPIO_ALT_FN_2_OUT }, /* FFTXD */ 189 190 /* BTUART configuration */ 191 { 42, GPIO_ALT_FN_1_IN }, /* BTRXD */ 192 { 43, GPIO_ALT_FN_2_OUT }, /* BTTXD */ 193 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 194 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 195 196 /* AC97 configuration */ 197 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 198 199 { -1 } 200 }; 201 202 #elif defined(OMAP2) 203 204 struct omap_mux_conf { 205 int offset; 206 uint32_t value; 207 /* OMAP3/4 register values */ 208 #define WAKEUPEVENT (1 << 15) 209 #define WAKEUPENABLE (1 << 14) 210 #define OFFMODEPULLTYPESELECT (1 << 13) 211 #define OFFMODEPULLUDENABLE (1 << 12) 212 #define OFFMODEOUTVALUE (1 << 11) 213 #define OFFMODEOUTENABLE (1 << 10) 214 #define OFFMODEENABLE (1 << 9) 215 #define INPUTENABLE (1 << 8) 216 #define PULLTYPESELECT (1 << 4) 217 #define PULLUDENABLE (1 << 3) 218 #define MUXMODE(n) ((n) & 0x7) 219 220 /* Sitara AM3xxx register values */ 221 #define SLEWCTRL (1 << 6) 222 #define RXACTIVE (1 << 5) 223 #define PUTYPESEL (1 << 4) 224 #define PUDEN (1 << 3) 225 #define MMODE(n) ((n) & 0x7) 226 }; 227 struct omap_gpio_conf { 228 int pin; 229 enum { 230 conf_input = -1, 231 conf_output_0, 232 conf_output_1, 233 } conf; 234 }; 235 236 static void gxio_omap_mux_config(const struct omap_mux_conf []); 237 static int gxio_omap_mux_config_address(const char *, unsigned long, 238 const struct omap_mux_conf[], 239 const struct omap_mux_conf[]); 240 static void gxio_omap_gpio_config(const struct omap_gpio_conf[]); 241 void gxio_omap_gpio_write(int, int); 242 243 static const struct omap_mux_conf overo_mux_i2c3_conf[] = { 244 { 0x1c2, MUXMODE(0) | INPUTENABLE }, /* i2c3_scl */ 245 { 0x1c4, MUXMODE(0) | INPUTENABLE }, /* i2c3_sda */ 246 { -1 } 247 }; 248 static const struct omap_mux_conf overo_mux_mmchs2_conf[] = { 249 { 0x158, /* mmc2_clk */ 250 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 251 { 0x15a, /* mmc2_cmd */ 252 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 253 { 0x15c, /* mmc2_dat0 */ 254 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 255 { 0x15e, /* mmc2_dat1 */ 256 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 257 { 0x160, /* mmc2_dat2 */ 258 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 259 { 0x162, /* mmc2_dat3 */ 260 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 261 { -1 } 262 }; 263 static const struct omap_mux_conf overo_mux_wireless_conf[] = { 264 { 0x0b4, MUXMODE(4) }, /* gpio_54:BT_nPOWERON*/ 265 { 0x0bc, MUXMODE(4) | INPUTENABLE }, /* gpio_58: WIFI_IRQ */ 266 { 0x19c, MUXMODE(4) }, /* gpio_164:BT_nRESET */ 267 { 0x5e0, MUXMODE(4) }, /* gpio_16: W2W_nRESET*/ 268 { -1 } 269 }; 270 271 static const struct omap_mux_conf duovero_mux_led_conf[] = { 272 { 0x116, MUXMODE(3) }, /* GPIO 122 */ 273 { -1 } 274 }; 275 static const struct omap_mux_conf duovero_mux_button_conf[] = { 276 { 0x114, /* GPIO 121 */ 277 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 278 { -1 } 279 }; 280 281 static const struct omap_mux_conf pepper_mux_led_conf[] = { 282 { 0x850, MMODE(7) | PUDEN }, /* GPIO 52: Blue */ 283 { 0x854, MMODE(7) | PUDEN }, /* GPIO 53: Red */ 284 { -1 } 285 }; 286 static const struct omap_mux_conf pepper_mux_button_conf[] = { 287 { 0x858, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 54 */ 288 { -1 } 289 }; 290 static const struct omap_mux_conf pepper_mux_mmchs3_conf[] = { 291 { 0x844, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT0 */ 292 { 0x848, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT1 */ 293 { 0x84c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT2 */ 294 { 0x878, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT3 */ 295 { 0x888, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CMD */ 296 { 0x88c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CLK */ 297 { -1 } 298 }; 299 static const struct omap_mux_conf pepper_mux_audio_codec_conf[] = { 300 { 0x840, MMODE(7) | PUDEN }, /* GPIO 48: #Reset */ 301 { -1 } 302 }; 303 304 #endif 305 306 static const struct gxioconf gxioconflist[] = { 307 #if defined(GUMSTIX) 308 { "basix", basix_config }, 309 { "cfstix", cfstix_config }, 310 { "etherstix", etherstix_config }, 311 { "netcf", netcf_config }, 312 { "netcf-vx", netcf_vx_config }, 313 { "netduo-mmc", netduommc_config }, 314 { "netduo", netduo_config }, 315 { "netmicrosd", netmicrosd_config }, 316 { "netmicrosd-vx", netmicrosd_config }, 317 { "netwifimicrosd", netwifimicrosd_config }, 318 { "netmmc", netmmc_config }, 319 { "netpro-vx", netwifimicrosd_config }, 320 { "wifistix-cf", wifistix_cf_config }, 321 { "wifistix", wifistix_config }, 322 #elif defined(OVERO) 323 { "chestnut43", chestnut_config }, 324 { "gallop43", gallop_config }, 325 { "summit", summit_config }, 326 { "tobi", tobi_config }, 327 { "tobi-duo", tobiduo_config }, 328 #elif defined(DUOVERO) 329 { "parlor", parlor_config }, 330 #elif defined(PEPPER) 331 { "43c", c_config }, 332 { "43r", r_config }, 333 { "dvi", dvi_config }, 334 #endif 335 { NULL } 336 }; 337 338 int gxpcic_gpio_reset; 339 struct gxpcic_slot_irqs gxpcic_slot_irqs[2] = { { 0, -1, -1 }, { 0, -1, -1 } }; 340 341 342 #if defined(GUMSTIX) 343 /* ARGSUSED */ 344 static int 345 gxiomatch(device_t parent, cfdata_t match, void *aux) 346 { 347 348 struct pxaip_attach_args *pxa = aux; 349 bus_space_tag_t iot = &pxa2x0_bs_tag; 350 bus_space_handle_t ioh; 351 352 if (strcmp(pxa->pxa_name, match->cf_name) != 0 || 353 pxa->pxa_addr != PXAIPCF_ADDR_DEFAULT) 354 return 0; 355 356 if (bus_space_map(iot, 357 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &ioh)) 358 return 0; 359 bus_space_unmap(iot, ioh, PXA2X0_MEMCTL_SIZE); 360 361 /* nothing */ 362 return 1; 363 } 364 365 /* ARGSUSED */ 366 static void 367 gxioattach(device_t parent, device_t self, void *aux) 368 { 369 struct gxio_softc *sc = device_private(self); 370 371 aprint_normal("\n"); 372 aprint_naive("\n"); 373 374 sc->sc_dev = self; 375 sc->sc_iot = &pxa2x0_bs_tag; 376 377 if (bus_space_map(sc->sc_iot, 378 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &sc->sc_ioh)) 379 return; 380 381 /* 382 * Attach each gumstix(busheader)/overo expansion board devices. 383 */ 384 config_search_ia(gxiosearch, self, "gxio", NULL); 385 } 386 387 /* ARGSUSED */ 388 static int 389 gxiosearch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 390 { 391 struct gxio_softc *sc = device_private(parent); 392 struct gxio_attach_args gxa; 393 394 gxa.gxa_sc = sc; 395 gxa.gxa_iot = sc->sc_iot; 396 gxa.gxa_addr = cf->cf_loc[GXIOCF_ADDR]; 397 gxa.gxa_gpirq = cf->cf_loc[GXIOCF_GPIRQ]; 398 399 if (config_match(parent, cf, &gxa)) 400 config_attach(parent, cf, &gxa, gxioprint); 401 402 return 0; 403 } 404 405 /* ARGSUSED */ 406 static int 407 gxioprint(void *aux, const char *name) 408 { 409 struct gxio_attach_args *gxa = (struct gxio_attach_args *)aux; 410 411 if (gxa->gxa_addr != GXIOCF_ADDR_DEFAULT) 412 printf(" addr 0x%lx", gxa->gxa_addr); 413 if (gxa->gxa_gpirq > 0) 414 printf(" gpirq %d", gxa->gxa_gpirq); 415 return UNCONF; 416 } 417 #endif 418 419 420 #if defined(GUMSTIX) 421 /* 422 * configure for GPIO pin and expansion boards. 423 */ 424 void 425 gxio_config(void) 426 { 427 #if defined(CPU_XSCALE_PXA250) 428 struct pxa2x0_gpioconf *gumstix_gpioconf[] = { 429 pxa25x_com_ffuart_gpioconf, 430 pxa25x_com_stuart_gpioconf, 431 #ifndef GXIO_BLUETOOTH_ON_HWUART 432 pxa25x_com_btuart_gpioconf, 433 #endif 434 pxa25x_com_hwuart_gpioconf, 435 pxa25x_i2c_gpioconf, 436 pxa25x_pxaacu_gpioconf, 437 pxa255dep_gpioconf, 438 NULL 439 }; 440 #endif 441 #if defined(CPU_XSCALE_PXA270) 442 struct pxa2x0_gpioconf *verdex_gpioconf[] = { 443 pxa27x_com_ffuart_gpioconf, 444 pxa27x_com_stuart_gpioconf, 445 pxa27x_com_btuart_gpioconf, 446 pxa27x_i2c_gpioconf, 447 pxa27x_pxaacu_gpioconf, 448 pxa27x_pxamci_gpioconf, 449 pxa27x_ohci_gpioconf, 450 verdexdep_gpioconf, 451 NULL 452 }; 453 #endif 454 455 /* XXX: turn off for power of bluetooth module */ 456 #if defined(CPU_XSCALE_PXA250) 457 pxa2x0_gpio_set_function(7, GPIO_OUT | GPIO_CLR); 458 #elif defined(CPU_XSCALE_PXA270) 459 pxa2x0_gpio_set_function(12, GPIO_OUT | GPIO_CLR); 460 #endif 461 delay(100); 462 463 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 464 pxa2x0_gpio_config( 465 (CPU_IS_PXA250) ? gumstix_gpioconf : verdex_gpioconf); 466 #elif defined(CPU_XSCALE_PXA270) || defined(CPU_XSCALE_PXA250) 467 #if defined(CPU_XSCALE_PXA270) 468 pxa2x0_gpio_config(verdex_gpioconf); 469 #else 470 pxa2x0_gpio_config(gumstix_gpioconf); 471 #endif 472 #endif 473 } 474 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 475 static void 476 gxio_omap_mux_config(const struct omap_mux_conf mux_conf[]) 477 { 478 #if defined(OVERO) 479 const vaddr_t ctrlmod_base = OVERO_L4_CORE_VBASE + 0x2000; 480 #elif defined(DUOVERO) 481 const vaddr_t ctrlmod_base = DUOVERO_L4_CM_VBASE; 482 #elif defined(PEPPER) 483 const vaddr_t ctrlmod_base = PEPPER_PRCM_VBASE + 0x10000; 484 #endif 485 int i; 486 487 for (i = 0; mux_conf[i].offset != -1; i++) 488 #if !defined(TI_AM335X) 489 ioreg16_write(ctrlmod_base + mux_conf[i].offset, 490 mux_conf[i].value); 491 #else 492 ioreg_write(ctrlmod_base + mux_conf[i].offset, 493 mux_conf[i].value); 494 #endif 495 } 496 497 static int 498 gxio_omap_mux_config_address(const char *name, unsigned long address, 499 const struct omap_mux_conf mux_conf[], 500 const struct omap_mux_conf not_mux_conf[]) 501 { 502 extern struct cfdata cfdata[]; 503 cfdata_t cf = &cfdata[0]; 504 505 while (cf->cf_name != NULL) { 506 if (strcmp(name, cf->cf_name) == 0 && 507 address == cf->cf_loc[OBIOCF_ADDR]) { 508 gxio_omap_mux_config(mux_conf); 509 return 0; 510 } 511 cf++; 512 } 513 514 if (not_mux_conf == NULL) 515 return -1; 516 517 gxio_omap_mux_config(not_mux_conf); 518 return 0; 519 } 520 521 #if defined(OVERO) 522 #define gpio_reg_read ioreg_read 523 #define gpio_reg_write ioreg_write 524 #elif defined(DUOVERO) || defined(PEPPER) 525 #define gpio_reg_read(a) ioreg_read((a) + GPIO_SIZE2) 526 #define gpio_reg_write(a, v) ioreg_write((a) + GPIO_SIZE2, (v)) 527 #endif 528 529 static const vaddr_t gpio_bases[] = { 530 #if defined(OVERO) 531 #define OVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 532 #define GPIO(n) GPIO ## n ## _BASE_3530 533 #define BASE(a, n) \ 534 (OVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP3530_L4_ ## a ## _BASE)) 535 536 GPIO1_BASE_3530, 537 GPIO2_BASE_3530, 538 GPIO3_BASE_3530, 539 GPIO4_BASE_3530, 540 GPIO5_BASE_3530, 541 GPIO6_BASE_3530, 542 543 #elif defined(DUOVERO) 544 #define DUOVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 545 #define GPIO(n) GPIO ## n ## _BASE_4430 546 #define BASE(a, n) \ 547 (DUOVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP4430_L4_ ## a ## _BASE)) 548 549 DUOVERO_GPIO_VBASE(1), 550 DUOVERO_GPIO_VBASE(2), 551 DUOVERO_GPIO_VBASE(3), 552 DUOVERO_GPIO_VBASE(4), 553 DUOVERO_GPIO_VBASE(5), 554 555 #elif defined(PEPPER) 556 #define PEPPER_GPIO_VBASE(n) ((n) == 0 ? WAKEUP(n) : PERIPHERAL(n)) 557 #define GPIO(n) GPIO ## n ## _BASE_TI_AM335X 558 #define WAKEUP(n) (PEPPER_PRCM_VBASE + (GPIO(n) - OMAP2_CM_BASE)) 559 #define PERIPHERAL(n) \ 560 (PEPPER_L4_PERIPHERAL_VBASE + (GPIO(n) - TI_AM335X_L4_PERIPHERAL_BASE)) 561 562 PEPPER_GPIO_VBASE(0), 563 PEPPER_GPIO_VBASE(1), 564 PEPPER_GPIO_VBASE(2), 565 PEPPER_GPIO_VBASE(3), 566 #endif 567 }; 568 569 static void 570 gxio_omap_gpio_config(const struct omap_gpio_conf gpio_conf[]) 571 { 572 vaddr_t gpio_base; 573 int mask, i; 574 575 for (i = 0; gpio_conf[i].pin != -1; i++) { 576 gpio_base = gpio_bases[gpio_conf[i].pin / 32]; 577 mask = 1 << (gpio_conf[i].pin % 32); 578 switch (gpio_conf[i].conf) { 579 case conf_input: 580 ioreg_write(gpio_base + GPIO_OE, 581 ioreg_read(gpio_base + GPIO_OE) | mask); 582 break; 583 case conf_output_0: 584 ioreg_write(gpio_base + GPIO_OE, 585 ioreg_read(gpio_base + GPIO_OE) | ~mask); 586 #if 0 587 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 588 #else 589 ioreg_write(gpio_base + GPIO_DATAOUT, 590 ioreg_read(gpio_base + GPIO_DATAOUT) & ~mask); 591 #endif 592 break; 593 case conf_output_1: 594 ioreg_write(gpio_base + GPIO_OE, 595 ioreg_read(gpio_base + GPIO_OE) | ~mask); 596 #if 0 597 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 598 #else 599 ioreg_write(gpio_base + GPIO_DATAOUT, 600 ioreg_read(gpio_base + GPIO_DATAOUT) | mask); 601 #endif 602 break; 603 } 604 } 605 } 606 607 void 608 gxio_omap_gpio_write(int pin, int val) 609 { 610 vaddr_t gpio_base; 611 int mask; 612 613 KASSERT(pin / 32 < __arraycount(gpio_bases)); 614 615 gpio_base = gpio_bases[pin / 32]; 616 mask = 1 << (pin % 32); 617 if (val == 0) 618 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 619 else 620 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 621 } 622 623 /* 624 * configure for MUX, GPIO. 625 */ 626 void 627 gxio_config(void) 628 { 629 const struct omap_mux_conf *mux_conf[] = { 630 #if defined(OVERO) 631 overo_mux_i2c3_conf, 632 overo_mux_mmchs2_conf, 633 overo_mux_wireless_conf, 634 #elif defined(DUOVERO) 635 duovero_mux_led_conf, 636 duovero_mux_button_conf, 637 #elif defined(PEPPER) 638 pepper_mux_led_conf, 639 pepper_mux_button_conf, 640 pepper_mux_mmchs3_conf, 641 pepper_mux_audio_codec_conf, 642 #endif 643 }; 644 const struct omap_gpio_conf gpio_conf[] = { 645 #if defined(OVERO) 646 { 16, conf_output_0 }, /* Wireless: #Reset */ 647 #elif defined(PEPPER) 648 { 48, conf_output_0 }, /* Audio Codec: #Reset */ 649 #endif 650 { -1 } 651 }; 652 int i; 653 654 for (i = 0; i < __arraycount(mux_conf); i++) 655 gxio_omap_mux_config(mux_conf[i]); 656 gxio_omap_gpio_config(gpio_conf); 657 } 658 #endif 659 660 void 661 gxio_config_expansion(char *expansion) 662 { 663 int i, d, s; 664 665 if (expansion == NULL) { 666 printf("not specified 'expansion=' in the boot args.\n"); 667 s = -1; 668 } else { 669 for (i = 0; gxioconflist[i].name != NULL; i++) 670 if (strncasecmp(gxioconflist[i].name, expansion, 671 strlen(gxioconflist[i].name) + 1) == 0) 672 break; 673 if (gxioconflist[i].name == NULL) 674 printf("unknown expansion specified: %s\n", expansion); 675 s = i; 676 } 677 #ifdef GXIO_DEFAULT_EXPANSION 678 for (i = 0; gxioconflist[i].name != NULL; i++) 679 if (strncasecmp(gxioconflist[i].name, GXIO_DEFAULT_EXPANSION, 680 strlen(gxioconflist[i].name) + 1) == 0) 681 break; 682 d = i; 683 #else 684 d = -1; 685 #endif 686 printf("supported expansions:\n"); 687 for (i = 0; gxioconflist[i].name != NULL; i++) 688 printf(" %s%s\n", 689 gxioconflist[i].name, 690 i == d ? " (DEFAULT)" : ""); 691 692 if (s < 0 || gxioconflist[i].name == NULL) { 693 #ifdef GXIO_DEFAULT_EXPANSION 694 expansion = __UNCONST(GXIO_DEFAULT_EXPANSION); 695 #else 696 return; 697 #endif 698 } 699 700 #if defined(PEPPER) 701 if (s < 0) { 702 struct pepper_board_id { 703 unsigned int device_vendor; 704 #define GUMSTIX_PEPPER 0x30000200 /* 1st gen */ 705 #define GUMSTIX_PEPPER_DVI 0x31000200 /* DVI and newer */ 706 unsigned char revision; 707 unsigned char content; 708 char fab_revision[8]; 709 char env_var[16]; 710 char env_setting[64]; 711 } id; 712 const vaddr_t i2c_base = PEPPER_PRCM_VBASE + 0xb000; 713 const uint8_t eeprom = 0x50; 714 const uint8_t len = sizeof(id); 715 int rv; 716 717 rv = read_i2c_device(i2c_base, eeprom, 0x00, len, (void *)&id); 718 if (rv == 0) 719 if (id.device_vendor == GUMSTIX_PEPPER) { 720 printf("configure auto detected expansion" 721 " (pepper)\n"); 722 pepper_config(); 723 return; 724 } 725 } 726 #endif 727 728 printf("configure %s expansion (%s)\n", 729 (s < 0 || gxioconflist[i].name == NULL) ? "default" : "specified", 730 expansion); 731 gxioconflist[(s < 0 || gxioconflist[i].name == NULL) ? d : s].config(); 732 } 733 734 735 #if defined(GUMSTIX) 736 737 static void 738 basix_config(void) 739 { 740 741 pxa2x0_gpio_set_function(8, GPIO_ALT_FN_1_OUT); /* MMCCS0 */ 742 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_1_OUT); /* MMCCLK */ 743 #if 0 744 /* this configuration set by gxmci.c::pxamci_attach() */ 745 pxa2x0_gpio_set_function(11, GPIO_IN); /* nSD_DETECT */ 746 pxa2x0_gpio_set_function(22, GPIO_IN); /* nSD_WP */ 747 #endif 748 } 749 750 static void 751 cfstix_config(void) 752 { 753 u_int gpio, npoe_fn; 754 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 755 int bvd = (CPU_IS_PXA250) ? 4 : 111; 756 #else 757 #if defined(CPU_XSCALE_PXA270) 758 const int bvd = 111; 759 #else 760 const int bvd = 4; 761 #endif 762 #endif 763 764 if (CPU_IS_PXA250) { 765 gxpcic_slot_irqs[0].valid = 1; 766 gxpcic_slot_irqs[0].cd = 11; 767 gxpcic_slot_irqs[0].prdy = 26; 768 gxpcic_gpio_reset = 8; 769 } else { 770 gxpcic_slot_irqs[0].valid = 1; 771 gxpcic_slot_irqs[0].cd = 104; 772 gxpcic_slot_irqs[0].prdy = 96; 773 gxpcic_gpio_reset = 97; 774 } 775 776 #if 1 777 /* PCD/PRDY set by pxa2x0_pcic.c::pxapcic_attach_common() */ 778 #else 779 pxa2x0_gpio_set_function(11, GPIO_IN); /* PCD1 */ 780 pxa2x0_gpio_set_function(26, GPIO_IN); /* PRDY1/~IRQ1 */ 781 #endif 782 pxa2x0_gpio_set_function(bvd, GPIO_IN); /* BVD1/~STSCHG1 */ 783 784 for (gpio = 48, npoe_fn = 0; gpio <= 53 ; gpio++) 785 npoe_fn |= pxa2x0_gpio_get_function(gpio); 786 npoe_fn &= GPIO_SET; 787 788 pxa2x0_gpio_set_function(48, GPIO_ALT_FN_2_OUT | npoe_fn); /* nPOE */ 789 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 790 pxa2x0_gpio_set_function(50, GPIO_ALT_FN_2_OUT); /* nPIOR */ 791 pxa2x0_gpio_set_function(51, GPIO_ALT_FN_2_OUT); /* nPIOW */ 792 if (CPU_IS_PXA250) { 793 pxa2x0_gpio_set_function(52, GPIO_ALT_FN_2_OUT); /* nPCE1 */ 794 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_2_OUT); /* nPCE2 */ 795 pxa2x0_gpio_set_function(54, GPIO_ALT_FN_2_OUT); /* pSKTSEL */ 796 } else { 797 pxa2x0_gpio_set_function(102, GPIO_ALT_FN_1_OUT); /* nPCE1 */ 798 pxa2x0_gpio_set_function(105, GPIO_ALT_FN_1_OUT); /* nPCE2 */ 799 pxa2x0_gpio_set_function(79, GPIO_ALT_FN_1_OUT); /* pSKTSEL */ 800 } 801 pxa2x0_gpio_set_function(55, GPIO_ALT_FN_2_OUT); /* nPREG */ 802 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); /* nPWAIT */ 803 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); /* nIOIS16 */ 804 } 805 806 static void 807 etherstix_config(void) 808 { 809 extern struct cfdata cfdata[]; 810 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 811 int rst = (CPU_IS_PXA250) ? 80 : 32; 812 int irq = (CPU_IS_PXA250) ? 36 : 99; 813 #else 814 #if defined(CPU_XSCALE_PXA270) 815 const int rst = 32, irq = 99; 816 #else 817 const int rst = 80, irq = 36; 818 #endif 819 #endif 820 int i; 821 822 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 823 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 824 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_SET); /* RESET 1 */ 825 delay(1); 826 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_CLR); 827 delay(50000); 828 829 for (i = 0; cfdata[i].cf_name != NULL; i++) 830 if (strcmp(cfdata[i].cf_name, "sm") == 0 && 831 strcmp(cfdata[i].cf_atname, "sm_gxio") == 0 && 832 cfdata[i].cf_loc[GXIOCF_ADDR] == 0x04000300 && 833 cfdata[i].cf_loc[GXIOCF_GPIRQ] == GXIOCF_GPIRQ_DEFAULT) 834 cfdata[i].cf_loc[GXIOCF_GPIRQ] = irq; 835 } 836 837 static void 838 netcf_config(void) 839 { 840 841 etherstix_config(); 842 cfstix_config(); 843 } 844 845 static void 846 netcf_vx_config(void) 847 { 848 849 /* 850 * XXXX: More power is necessary for NIC and USB??? 851 * (no document. from Linux) 852 */ 853 854 pxa2x0_gpio_set_function(27, GPIO_IN); 855 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); 856 pxa2x0_gpio_set_function(118, GPIO_ALT_FN_1_IN | GPIO_CLR); 857 858 etherstix_config(); 859 cfstix_config(); 860 if (CPU_IS_PXA270) { 861 /* Overwrite */ 862 gxpcic_slot_irqs[0].cd = 104; 863 gxpcic_slot_irqs[0].prdy = 109; 864 gxpcic_gpio_reset = 110; 865 }; 866 } 867 868 static void 869 netduommc_config(void) 870 { 871 872 netduo_config(); 873 basix_config(); 874 } 875 876 static void 877 netduo_config(void) 878 { 879 880 etherstix_config(); 881 882 pxa2x0_gpio_set_function(78, GPIO_ALT_FN_2_OUT); /* nCS 2 */ 883 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_SET); /* RESET 2 */ 884 delay(1); 885 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_CLR); 886 delay(50000); 887 } 888 889 static void 890 netmicrosd_config(void) 891 { 892 893 /* MicroSD(mci) always configure on PXA270 */ 894 895 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 896 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 897 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); /* RESET 1 */ 898 delay(hz / 2); 899 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_SET); 900 delay(50000); 901 } 902 903 static void 904 netwifimicrosd_config(void) 905 { 906 907 netmicrosd_config(); 908 909 cfstix_config(); 910 /* However use pxamci. */ 911 pxa2x0_gpio_set_function(111, GPIO_CLR | GPIO_ALT_FN_1_IN); 912 /* Power to Marvell 88W8385 */ 913 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 914 } 915 916 static void 917 netmmc_config(void) 918 { 919 920 etherstix_config(); 921 basix_config(); 922 } 923 924 static void 925 wifistix_config(void) 926 { 927 928 cfstix_config(); 929 930 /* Power to Marvell 88W8385 */ 931 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 932 } 933 934 static void 935 wifistix_cf_config(void) 936 { 937 938 gxpcic_slot_irqs[1].valid = 1; 939 gxpcic_slot_irqs[1].cd = 36; 940 gxpcic_slot_irqs[1].prdy = 27; 941 942 #if 1 943 /* this configuration set by pxa2x0_pcic.c::pxapcic_attach_common() */ 944 #else 945 pxa2x0_gpio_set_function(36, GPIO_IN); /* PCD2 */ 946 pxa2x0_gpio_set_function(27, GPIO_IN); /* PRDY2/~IRQ2 */ 947 #endif 948 pxa2x0_gpio_set_function(18, GPIO_IN); /* BVD2/~STSCHG2 */ 949 950 cfstix_config(); 951 952 /* Power to Marvell 88W8385 */ 953 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 954 } 955 956 #elif defined(OVERO) 957 958 static void 959 eth0_config(void) 960 { 961 /* 962 * ETH0 connects via CS5. It use GPIO 176 for IRQ. 963 * Also GPIO 64 is NRESET. 964 */ 965 966 smsh_config(NULL, 176, 64); 967 } 968 969 static void 970 eth1_config(void) 971 { 972 struct omap_mux_conf eth1_mux_conf[] = { 973 { 0x0d2, MUXMODE(4) | INPUTENABLE }, 974 { -1 } 975 }; 976 977 /* 978 * ETH1 connects via CS4. It use GPIO 65 for IRQ. 979 */ 980 981 smsh_config(eth1_mux_conf, 65, 64); 982 } 983 984 static void 985 dvi_config(void) 986 { 987 static const struct omap_mux_conf overo_mux_dvi_conf[] = { 988 { 0x0d4, MUXMODE(0) }, /* dss_pclk */ 989 { 0x0d6, MUXMODE(0) }, /* dss_pclk */ 990 { 0x0d8, MUXMODE(0) }, /* dss_pclk */ 991 { 0x0da, MUXMODE(0) }, /* dss_pclk */ 992 { 0x0dc, MUXMODE(0) }, /* dss_pclk */ 993 { 0x0de, MUXMODE(0) }, /* dss_pclk */ 994 { 0x0e0, MUXMODE(0) }, /* dss_pclk */ 995 { 0x0e2, MUXMODE(0) }, /* dss_pclk */ 996 { 0x0e4, MUXMODE(0) }, /* dss_pclk */ 997 { 0x0e6, MUXMODE(0) }, /* dss_pclk */ 998 { 0x0e8, MUXMODE(0) }, /* dss_pclk */ 999 { 0x0ea, MUXMODE(0) }, /* dss_pclk */ 1000 { 0x0ec, MUXMODE(0) }, /* dss_pclk */ 1001 { 0x0ee, MUXMODE(0) }, /* dss_pclk */ 1002 { 0x0f0, MUXMODE(0) }, /* dss_pclk */ 1003 { 0x0f2, MUXMODE(0) }, /* dss_pclk */ 1004 { 0x0f4, MUXMODE(0) }, /* dss_pclk */ 1005 { 0x0f6, MUXMODE(0) }, /* dss_pclk */ 1006 { 0x0f8, MUXMODE(0) }, /* dss_pclk */ 1007 { 0x0fa, MUXMODE(0) }, /* dss_pclk */ 1008 { 0x0fc, MUXMODE(0) }, /* dss_pclk */ 1009 { 0x0fe, MUXMODE(0) }, /* dss_pclk */ 1010 { 0x100, MUXMODE(0) }, /* dss_pclk */ 1011 { 0x102, MUXMODE(0) }, /* dss_pclk */ 1012 { 0x104, MUXMODE(0) }, /* dss_pclk */ 1013 { 0x106, MUXMODE(0) }, /* dss_pclk */ 1014 { 0x108, MUXMODE(0) }, /* dss_pclk */ 1015 { 0x10a, MUXMODE(0) }, /* dss_pclk */ 1016 { -1 } 1017 }; 1018 1019 gxio_omap_mux_config(overo_mux_dvi_conf); 1020 } 1021 1022 static void 1023 lcd_config(char type) 1024 { 1025 static const struct omap_mux_conf overo_mux_mcspi1_conf[] = { 1026 { 0x1c8, MUXMODE(0) | INPUTENABLE }, /* mcspi1_clk */ 1027 { 0x1ca, MUXMODE(0) | INPUTENABLE }, /* mcspi1_simo*/ 1028 { 0x1cc, MUXMODE(0) | INPUTENABLE }, /* mcspi1_somi*/ 1029 { 0x1ce, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs0 */ 1030 { 0x1d0, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs1 */ 1031 { -1 } 1032 }; 1033 static const struct omap_mux_conf overo_mux_ads7846_conf[] = { 1034 { 0x138, /* gpio_114: NPENIRQ */ 1035 MUXMODE(4) | PULLUDENABLE | INPUTENABLE }, 1036 { -1 } 1037 }; 1038 static const struct omap_mux_conf overo_mux_lcd_conf[] = { 1039 { 0x174, MUXMODE(4) }, /* gpio_144: DISPLAY_EN */ 1040 { 0x176, MUXMODE(4) }, /* gpio_145: Brightness */ 1041 { -1 } 1042 }; 1043 1044 static const struct omap_gpio_conf overo_gpio_lcd_conf[] = { 1045 { 144, conf_output_0 }, /* DISPLAY_EN */ 1046 { 145, conf_output_0 }, /* Brightness */ 1047 { -1 } 1048 }; 1049 1050 dvi_config(); 1051 if (type != 'C') { 1052 gxio_omap_mux_config(overo_mux_mcspi1_conf); 1053 gxio_omap_mux_config(overo_mux_ads7846_conf); 1054 } 1055 gxio_omap_mux_config(overo_mux_lcd_conf); 1056 1057 gxio_omap_gpio_config(overo_gpio_lcd_conf); 1058 } 1059 1060 enum { 1061 uart1_if_exists = 0, 1062 force_uart1 1063 }; 1064 static void 1065 header_40pin_config(int uart1) 1066 { 1067 static const struct omap_mux_conf overo_mux_40pin_header_conf[] = { 1068 /* 1069 * 1: GND 1070 * 2: VCC_3.3 1071 * 3: GPIO171_SPI1_CLK 1072 * 4: GPIO114_SPI1_NIRQ 1073 * 5: GPIO172_SPI1_MOSI 1074 * 6: GPIO174_SPI1_CS0 1075 * 7: GPIO173_SPI1_MISO 1076 * 8: GPIO175_SPI1_CS1 1077 * 9: GPIO151_RXD1 1078 * 10: GPIO148_TXD1 1079 * 11: SYS_EN 1080 * 12: VBACKUP 1081 * 13: GPIO0_WAKEUP 1082 * 14: POWERON 1083 * 15: GND 1084 * 16: VCC_1.8 1085 * 17: GPIO128_GPS_PPS 1086 * 18: GPIO127_TS_IRQ 1087 * 19: GPIO170_HDQ_1WIRE 1088 * 20: GPIO163_IR_CTS3 1089 * 21: GPIO165_IR_RXD3 (console) 1090 * 22: GPIO166_IR_TXD3 (console) 1091 * 23: GPIO184_SCL3 (system eeprom) 1092 * 24: GPIO185_SDA3 (system eeprom) 1093 * 25: GND 1094 * 26: VCC_1.8 1095 * 27: GPIO146_PWM11 1096 * 28: GPIO145_PWM10 1097 * 29: GPIO147_PWM8 1098 * 30: GPIO144_PWM9 1099 * 31: PWM0 (TPS65950) 1100 * 32: PWM1 (TPS65950) 1101 * 33: ADCIN7 (TPS65950) 1102 * 34: ADCIN2 (TPS65950) 1103 * 35: ADCIN6 (TPS65950) 1104 * 36: ADCIN5 (TPS65950) 1105 * 37: AGND (TPS65950) 1106 * 38: ADCIN3 (TPS65950) 1107 * 39: ADCIN4 (TPS65950) 1108 * 40: VIN (TPS65950) 1109 */ 1110 1111 { 0x152, MUXMODE(4) | INPUTENABLE }, /* gpio_127 */ 1112 { 0x154, MUXMODE(4) | INPUTENABLE }, /* gpio_128 */ 1113 { 0x174, MUXMODE(4) | INPUTENABLE }, /* gpio_144 */ 1114 { 0x176, MUXMODE(4) | INPUTENABLE }, /* gpio_145 */ 1115 { 0x178, MUXMODE(4) | INPUTENABLE }, /* gpio_146 */ 1116 { 0x17a, MUXMODE(4) | INPUTENABLE }, /* gpio_147 */ 1117 { 0x19a, MUXMODE(4) | INPUTENABLE }, /* gpio_163 */ 1118 { -1 } 1119 }; 1120 static const struct omap_mux_conf overo_mux_uart1_conf[] = { 1121 { 0x17c, MUXMODE(0) }, /* uart1_tx */ 1122 { 0x182, MUXMODE(0) | INPUTENABLE }, /* uart1_rx */ 1123 { -1 } 1124 }; 1125 static const struct omap_mux_conf overo_mux_no_uart1_conf[] = { 1126 { 0x17c, MUXMODE(4) | INPUTENABLE }, /* gpio_148 */ 1127 { 0x182, MUXMODE(4) | INPUTENABLE }, /* gpio_151 */ 1128 { -1 } 1129 }; 1130 static const struct omap_mux_conf overo_mux_hdq_conf[] = { 1131 #if 0 1132 { 0x1c4, MUXMODE(0) | ??? | INPUTENABLE }, /* hdq_sio */ 1133 #endif 1134 { -1 } 1135 }; 1136 static const struct omap_mux_conf overo_mux_no_hdq_conf[] = { 1137 { 0x1c4, MUXMODE(4) | INPUTENABLE }, /* gpio_170 */ 1138 { -1 } 1139 }; 1140 1141 gxio_omap_mux_config(overo_mux_40pin_header_conf); 1142 if (uart1 == force_uart1) 1143 gxio_omap_mux_config(overo_mux_uart1_conf); 1144 else 1145 gxio_omap_mux_config_address("com", 0x4806a000, 1146 overo_mux_uart1_conf, overo_mux_no_uart1_conf); 1147 gxio_omap_mux_config_address("hdq", 0x480b2000, 1148 overo_mux_hdq_conf, overo_mux_no_hdq_conf); 1149 } 1150 1151 static void 1152 chestnut_config(void) 1153 { 1154 static const struct omap_mux_conf chestnut_mux_conf[] = { 1155 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1156 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1157 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1158 { -1 } 1159 }; 1160 1161 eth0_config(); 1162 lcd_config('R'); 1163 1164 header_40pin_config(uart1_if_exists); 1165 gxio_omap_mux_config(chestnut_mux_conf); 1166 } 1167 1168 static void 1169 gallop_config(void) 1170 { 1171 static const struct omap_mux_conf gallop43_mux_conf[] = { 1172 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1173 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1174 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1175 { -1 } 1176 }; 1177 1178 lcd_config('R'); 1179 1180 header_40pin_config(force_uart1); 1181 gxio_omap_mux_config(gallop43_mux_conf); 1182 } 1183 1184 static void 1185 summit_config(void) 1186 { 1187 1188 dvi_config(); 1189 1190 header_40pin_config(uart1_if_exists); 1191 } 1192 1193 static void 1194 tobi_config(void) 1195 { 1196 1197 eth0_config(); 1198 dvi_config(); 1199 1200 header_40pin_config(uart1_if_exists); 1201 } 1202 1203 static void 1204 tobiduo_config(void) 1205 { 1206 1207 eth0_config(); 1208 eth1_config(); 1209 } 1210 1211 #elif defined(DUOVERO) 1212 1213 static void 1214 ehci_config(void) 1215 { 1216 uint32_t val; 1217 1218 #define SCRM_ALTCLKSRC 0xa110 1219 #define ALTCLKSRC_ENABLE_EXT (1 << 3) 1220 #define ALTCLKSRC_ENABLE_INT (1 << 2) 1221 #define ALTCLKSRC_MODE_MASK (3 << 0) 1222 #define ALTCLKSRC_MODE_POWERDOWN (0 << 0) 1223 #define ALTCLKSRC_MODE_ACTIVE (1 << 0) 1224 #define ALTCLKSRC_MODE_BYPASS (2 << 0) 1225 #define SCRM_AUXCLK3 0xa31c 1226 #define AUXCLK3_CLKDIV(n) (((n) - 1) << 16) 1227 #define AUXCLK3_CLKDIV_MASK (0xf << 16) 1228 #define AUXCLK3_ENABLE (1 << 8) 1229 #define AUXCLK3_SRCSELECT_MASK (3 << 1) 1230 #define AUXCLK3_SRCSELECT_SYSCLK (0 << 1) 1231 #define AUXCLK3_SRCSELECT_CORE (1 << 1) 1232 #define AUXCLK3_SRCSELECT_PERDPLL (2 << 1) 1233 #define AUXCLK3_SRCSELECT_ALTCLK (3 << 1) 1234 #define AUXCLK3_POLARITY_LOW (0 << 0) 1235 #define AUXCLK3_POLARITY_HIGH (1 << 0) 1236 1237 /* Use the 1/2 auxiliary clock #3 of system clock. */ 1238 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3); 1239 val &= ~(AUXCLK3_CLKDIV_MASK | AUXCLK3_SRCSELECT_MASK); 1240 val |= (AUXCLK3_CLKDIV(2) | AUXCLK3_ENABLE | AUXCLK3_SRCSELECT_SYSCLK); 1241 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3, val); 1242 1243 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC); 1244 val &= ~ALTCLKSRC_MODE_MASK; 1245 val |= ALTCLKSRC_MODE_ACTIVE; 1246 val |= (ALTCLKSRC_ENABLE_EXT | ALTCLKSRC_ENABLE_INT); 1247 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC, val); 1248 } 1249 1250 static void 1251 parlor_config(void) 1252 { 1253 #if 0 1254 static const struct omap_mux_conf parlor_mux_40pin_header_conf[] = { 1255 /* 1256 * 1: GND 1257 * 2: GND 1258 * 3: MCSPI1_CLK or GPIO 134 1259 * 4: MCSPI1_CS0 or GPIO 137 1260 * 5: MCSPI1_SIMO or GPIO 136 1261 * 6: MCSPI1_CS1 or GPIO 138 1262 * 7: MCSPI1_SOMI or GPIO 135 1263 * 8: MCSPI1_CS2 or GPIO 139 1264 * 9: HDQ_SIO or GPIO 127 1265 * 10: MCSPI1_CS3 or GPIO 140 1266 * 11: SDMMC3_CMD or GPIO ??? 1267 * 12: I2C2_SCL or GPIO 128 1268 * 13: SDMMC3_CLK or GPIO ??? 1269 * 14: I2C2_SDA or GPIO 129 1270 * 15: UART2_TX or SDMMC3_DAT1 or GPIO 126 1271 * 16: PMIC_PWM2 (TWL6030) 1272 * 17: UART2_RX or SDMMC3_DAT0 or GPIO 125 1273 * 18: PMIC_PWM1 (TWL6030) 1274 * 19: BSP2_CLKX or GPIO 110 1275 * 20: BSP2_FSX or GPIO 113 1276 * 21: BSP2_DX or GPIO 112 1277 * 22: BSP2_DR or GPIO 111 1278 * 23: BSP2_CLKS or GPIO 118 1279 * 24: FREF1 1280 * 25: MCSPI4_SOMI or GPIO 153 1281 * 26: PMIC_NRESWARN 1282 * 27: MCSPI4_SIMO or GPIO 152 1283 * 28: SYSEN 1284 * 29: MCSPI4_CLK or GPIO 151 1285 * 30: PWRON 1286 * 31: MCSPI4_CS0 or GPIO 154 1287 * 32: REGEN1 1288 * 33: ADCIN3 (TWL6030) 1289 * 34: VCC_1.0 1290 * 35: ADCIN4_VREF (TWL6030) 1291 * 36: VDD_VAUX2 1292 * 37: ADCIN4 (TWL6030) 1293 * 38: VCC_3.3 1294 * 39: ADCIN5 (TWL6030) 1295 * 40: V_BATT_5 1296 */ 1297 { -1 } 1298 }; 1299 #endif 1300 static const struct omap_mux_conf parlor_mux_mcspi1_conf[] = { 1301 #if 0 1302 { 0x132, /* 3: MCSPI1_CLK */ 1303 MUXMODE(0) | ??? }, 1304 { 0x138, /* 4: MCSPI1_CS0 */ 1305 MUXMODE(0) | ??? }, 1306 { 0x136, /* 5: MCSPI1_SIMO */ 1307 MUXMODE(0) | ??? }, 1308 { 0x13a, /* 6: MCSPI1_CS1 */ 1309 MUXMODE(0) | ??? }, 1310 { 0x134, /* 7: MCSPI1_SOMI */ 1311 MUXMODE(0) | ??? | INPUTENABLE }, 1312 { 0x13c, /* 8: MCSPI1_CS2 */ 1313 MUXMODE(0) | ??? }, 1314 { 0x13e, /* 10: MCSPI1_CS3 */ 1315 MUXMODE(0) | ??? }, 1316 #endif 1317 { -1 } 1318 }; 1319 static const struct omap_mux_conf parlor_mux_no_mcspi1_conf[] = { 1320 { 0x132, /* 3: GPIO 134 */ 1321 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1322 { 0x138, /* 4: GPIO 137 */ 1323 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1324 { 0x136, /* 5: GPIO 136 */ 1325 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1326 { 0x13a, /* 6: GPIO 138 */ 1327 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1328 { 0x134, /* 7: GPIO 135 */ 1329 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1330 { 0x13c, /* 8: GPIO 139 */ 1331 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1332 { 0x13e, /* 10: GPIO 140 */ 1333 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1334 { -1 } 1335 }; 1336 static const struct omap_mux_conf parlor_mux_hdq_conf[] = { 1337 #if 0 1338 { 0x120, /* 9: HDQ_SIO */ 1339 MUXMODE(0) | ??? | INPUTENABLE }, 1340 #endif 1341 { -1 } 1342 }; 1343 static const struct omap_mux_conf parlor_mux_no_hdq_conf[] = { 1344 { 0x120, /* 9: GPIO_127 */ 1345 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1346 { -1 } 1347 }; 1348 static const struct omap_mux_conf parlor_mux_i2c2_conf[] = { 1349 { 0x126, /* 12: I2C2_SCL */ 1350 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1351 { 0x128, /* 14: I2C2_SDA */ 1352 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1353 { -1 } 1354 }; 1355 static const struct omap_mux_conf parlor_mux_no_i2c2_conf[] = { 1356 { 0x126, /* 12: GPIO 128 */ 1357 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1358 { 0x128, /* 14: GPIO 129 */ 1359 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1360 { -1 } 1361 }; 1362 static const struct omap_mux_conf parlor_mux_sdmmc3_conf[] = { 1363 #if 0 1364 11 SDMMC3_CMD DuoVero J2 A15 <- omap pin AG10 1365 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1366 13 SDMMC3_CLK DuoVero J2 A16 <- omap pin AE9 1367 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1368 #endif 1369 { 0x11c, /* 17: SDMMC3_DAT0 */ 1370 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1371 { 0x11e, /* 15: SDMMC3_DAT1 */ 1372 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1373 { -1 } 1374 }; 1375 static const struct omap_mux_conf parlor_mux_uart2_conf[] = { 1376 { 0x11c, /* 17: UART2_RX */ 1377 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1378 { 0x11e, 1379 MUXMODE(0) | PULLUDENABLE }, /* 15: UART2_TX */ 1380 { -1 } 1381 }; 1382 static const struct omap_mux_conf parlor_mux_no_uart2_conf[] = { 1383 { 0x11c, /* 17: GPIO 125 */ 1384 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1385 { 0x11e, /* 15: GPIO 126 */ 1386 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1387 { -1 } 1388 }; 1389 static const struct omap_mux_conf parlor_mux_bsp2_conf[] = { 1390 { 0x0f6, /* 19: BSP2_CLKX */ 1391 MUXMODE(0) | INPUTENABLE }, 1392 { 0x0fc, /* 20: BSP2_FSX */ 1393 MUXMODE(0) | INPUTENABLE }, 1394 { 0x0fa, /* 21: BSP2_DX */ 1395 MUXMODE(0) | PULLUDENABLE }, 1396 { 0x0f8, /* 22: BSP2_DR */ 1397 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1398 { 0x10e, /* 23: BSP2_CLKS */ 1399 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1400 { -1 } 1401 }; 1402 static const struct omap_mux_conf parlor_mux_no_bsp2_conf[] = { 1403 { 0x0f6, /* 19: GPIO 110 */ 1404 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1405 { 0x0fc, /* 20: GPIO 113 */ 1406 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1407 { 0x0fa, /* 21: GPIO 112 */ 1408 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1409 { 0x0f8, /* 22: GPIO 111 */ 1410 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1411 { 0x10e, /* 23: GPIO 118 */ 1412 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1413 { -1 } 1414 }; 1415 static const struct omap_mux_conf parlor_mux_mcspi4_conf[] = { 1416 #if 0 1417 { 0x158, /* 25: MCSPI4_SOMI */ 1418 MUXMODE(0) | ??? | INPUTENABLE }, 1419 { 0x156, /* 27: MCSPI4_SIMO */ 1420 MUXMODE(0) | ??? }, 1421 { 0x154, /* 29: MCSPI4_CLK */ 1422 MUXMODE(0) | ??? }, 1423 { 0x15a, /* 31: MCSPI4_CS0 */ 1424 MUXMODE(0) | ??? }, 1425 #endif 1426 { -1 } 1427 }; 1428 static const struct omap_mux_conf parlor_mux_no_mcspi4_conf[] = { 1429 { 0x158, /* 25: GPIO 153 */ 1430 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1431 { 0x156, /* 27: GPIO 152 */ 1432 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1433 { 0x154, /* 29: GPIO 151 */ 1434 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1435 { 0x15a, /* 31: GPIO 154 */ 1436 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1437 { -1 } 1438 }; 1439 1440 /* 1441 * ETH0 connects via CS5. It use GPIO 44 for IRQ. 1442 * Also GPIO 45 is NRESET. 1443 */ 1444 smsh_config(NULL, 44, 45); 1445 1446 ehci_config(); 1447 1448 gxio_omap_mux_config_address("mcspi", 0x48098000, 1449 parlor_mux_mcspi1_conf, parlor_mux_no_mcspi1_conf); 1450 gxio_omap_mux_config_address("hdq", 0x480b2000, 1451 parlor_mux_hdq_conf, parlor_mux_no_hdq_conf); 1452 gxio_omap_mux_config_address("tiiic", 0x48072000, 1453 parlor_mux_i2c2_conf, parlor_mux_no_i2c2_conf); 1454 if (gxio_omap_mux_config_address("sdhc", 0x480ad000, 1455 parlor_mux_sdmmc3_conf, NULL) != 0) 1456 gxio_omap_mux_config_address("com", 0x4806c000, 1457 parlor_mux_uart2_conf, parlor_mux_no_uart2_conf); 1458 gxio_omap_mux_config_address("mcbsp", 0x49024000, 1459 parlor_mux_bsp2_conf, parlor_mux_no_bsp2_conf); 1460 gxio_omap_mux_config_address("mcspi", 0x480ba000, 1461 parlor_mux_mcspi4_conf, parlor_mux_no_mcspi4_conf); 1462 } 1463 1464 #elif defined(PEPPER) 1465 1466 static void 1467 lcd_config(void) 1468 { 1469 static const struct tifb_panel_info panel_lcd = { 1470 .panel_tft = 1, 1471 .panel_mono = false, 1472 .panel_bpp = 24, 1473 1474 .panel_pxl_clk = 18400000, 1475 .panel_width = 480, 1476 .panel_height = 272, 1477 .panel_hfp = 8, 1478 .panel_hbp = 4, 1479 .panel_hsw = 41, 1480 .panel_vfp = 4, 1481 .panel_vbp = 2, 1482 .panel_vsw = 10, 1483 .panel_invert_hsync = 0, 1484 .panel_invert_vsync = 0, 1485 1486 .panel_ac_bias = 255, 1487 .panel_ac_bias_intrpt = 0, 1488 .panel_dma_burst_sz = 16, 1489 .panel_fdd = 0x80, 1490 .panel_sync_edge = 0, 1491 .panel_sync_ctrl = 1, 1492 .panel_tft_alt_mode = 0, 1493 .panel_invert_pxl_clk = 0, 1494 }; 1495 static const struct omap_mux_conf pepper_mux_lcd_conf[] = { 1496 /* 1497 * LCD_DATA[0-23] configures in tifb.c 1498 */ 1499 1500 { 0x8e0, MMODE(0) | PUDEN }, /* LCD_VSYNC */ 1501 { 0x8e4, MMODE(0) | PUDEN }, /* LCD_HSYNC */ 1502 { 0x8e8, MMODE(0) | PUDEN }, /* LCD_PCLK */ 1503 { 0x8ec, MMODE(0) | PUDEN }, /* LCD_AC_BIAS_EN */ 1504 1505 { 0x86c, MMODE(7) | PUTYPESEL }, /* GPIO 59: Enable */ 1506 { -1 } 1507 }; 1508 1509 if (gxio_omap_mux_config_address("tifb", 0x4830e000, 1510 pepper_mux_lcd_conf, NULL) == 0) { 1511 extern const struct tifb_panel_info *tifb_panel_info; 1512 extern bool use_tps65217_wled; 1513 1514 tifb_panel_info = &panel_lcd; 1515 use_tps65217_wled = true; 1516 } 1517 } 1518 1519 static void 1520 pepper43_config(void) 1521 { 1522 static const struct omap_mux_conf pepper43_mux_wilink8_conf[] = { 1523 /* TI WiLink 8 */ 1524 { 0x800, MMODE(7) | PUTYPESEL }, /* GPIO 32: Bluetooth */ 1525 { 0x804, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 33: irq */ 1526 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: WiFi */ 1527 { -1 } 1528 }; 1529 static const struct omap_mux_conf pepper43_mux_i2c1_conf[] = { 1530 { 0x968, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1531 { 0x96c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1532 { -1 } 1533 }; 1534 static const struct omap_mux_conf pepper43_mpu9150_conf[] = { 1535 /* MPU9150 at I2C1 */ 1536 { 0x808, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 34: IRQ */ 1537 { 0x898, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 68 */ 1538 { 0x870, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 30 */ 1539 { -1 } 1540 }; 1541 static const struct omap_mux_conf pepper43_mux_20pin_header_conf[] = { 1542 { 0x85c, MMODE(7) | PUDEN | RXACTIVE }, /* 1: GPIO 55 */ 1543 { 0x80c, MMODE(7) | PUDEN | RXACTIVE }, /* 2: GPIO 35 */ 1544 { 0x810, MMODE(7) | PUDEN | RXACTIVE }, /* 3: GPIO 36 */ 1545 { 0x814, MMODE(7) | PUDEN | RXACTIVE }, /* 4: GPIO 37 */ 1546 { 0x818, MMODE(7) | PUDEN | RXACTIVE }, /* 5: GPIO 38 */ 1547 { 0x81c, MMODE(7) | PUDEN | RXACTIVE }, /* 6: GPIO 39 */ 1548 { 0x87c, MMODE(7) | PUDEN | RXACTIVE }, /* 7: GPIO 61 */ 1549 { 0x880, MMODE(7) | PUDEN | RXACTIVE }, /* 8: GPIO 62 */ 1550 { 0x884, MMODE(7) | PUDEN | RXACTIVE }, /* 9: GPIO 63 */ 1551 { 0x9e4, MMODE(7) | PUDEN | RXACTIVE }, /* 10: GPIO 103 */ 1552 { 0x9e8, MMODE(7) | PUDEN | RXACTIVE }, /* 11: GPIO 104 */ 1553 { 0x9b0, MMODE(7) | PUDEN | RXACTIVE }, /* 12: GPIO 19 */ 1554 #if 0 /* UART3 or GPIO */ 1555 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* 13: GPIO 7 */ 1556 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* 14: GPIO 6 */ 1557 #endif 1558 #if 0 /* UART2 or GPIO */ 1559 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* 15: GPIO 98 */ 1560 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* 16: GPIO 97 */ 1561 #endif 1562 /* 17: VCC 5v */ 1563 /* 18: VCC 3.3v */ 1564 /* 19: GND */ 1565 /* 20: GND */ 1566 { -1 } 1567 }; 1568 static const struct omap_mux_conf pepper43_mux_uart2_conf[] = { 1569 { 0x90c, MMODE(6) | PUTYPESEL | RXACTIVE }, /* UART2_RXD */ 1570 { 0x910, MMODE(6) | PUDEN }, /* UART2_TXD */ 1571 { -1 } 1572 }; 1573 static const struct omap_mux_conf pepper43_mux_no_uart2_conf[] = { 1574 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 97 */ 1575 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 98 */ 1576 { -1 } 1577 }; 1578 static const struct omap_mux_conf pepper43_mux_uart3_conf[] = { 1579 { 0x960, MMODE(1) | PUTYPESEL | RXACTIVE }, /* UART3_RXD */ 1580 { 0x964, MMODE(1) | PUDEN }, /* UART3_TXD */ 1581 { -1 } 1582 }; 1583 static const struct omap_mux_conf pepper43_mux_no_uart3_conf[] = { 1584 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 6 */ 1585 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 7 */ 1586 { -1 } 1587 }; 1588 1589 static const struct omap_mux_conf *pepper43_mux_conf[] = { 1590 pepper43_mux_wilink8_conf, 1591 pepper43_mux_i2c1_conf, 1592 pepper43_mpu9150_conf, 1593 pepper43_mux_20pin_header_conf, 1594 }; 1595 1596 static const struct omap_gpio_conf pepper43_gpio_wl18xx_conf[] = { 1597 { 32, conf_output_0 }, /* #Reset: Bluetooth */ 1598 { 56, conf_output_0 }, /* #Reset: WiFi */ 1599 { -1 } 1600 }; 1601 int i; 1602 1603 lcd_config(); 1604 1605 for (i = 0; i < __arraycount(pepper43_mux_conf); i++) 1606 gxio_omap_mux_config(pepper43_mux_conf[i]); 1607 gxio_omap_gpio_config(pepper43_gpio_wl18xx_conf); 1608 1609 #if 0 1610 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 52 (Blue) */ 1611 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 20)); 1612 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1613 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 20)); 1614 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 53 (Red) */ 1615 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 21)); 1616 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1617 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 21)); 1618 #endif 1619 1620 gxio_omap_mux_config_address("com", 0x48024000, 1621 pepper43_mux_uart2_conf, pepper43_mux_no_uart2_conf); 1622 gxio_omap_mux_config_address("com", 0x481a6000, 1623 pepper43_mux_uart3_conf, pepper43_mux_no_uart3_conf); 1624 } 1625 1626 static void 1627 pepper_config(void) 1628 { 1629 static const struct omap_mux_conf pepper_mux_button2_conf[] = { 1630 { 0x85c, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 55 */ 1631 { -1 } 1632 }; 1633 static const struct omap_mux_conf pepper_mux_i2c1_conf[] = { 1634 { 0x90c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1635 { 0x910, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1636 { -1 } 1637 }; 1638 static const struct omap_mux_conf pepper_mux_wi2wi_conf[] = { 1639 { 0x9b4, MMODE(3) | PUDEN }, /* CLKOUT2 */ 1640 /* Wi2Wi */ 1641 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: nReset */ 1642 { 0x870, MMODE(7) | PUTYPESEL }, /* GPIO 30: nPower */ 1643 { -1 } 1644 }; 1645 static const struct omap_mux_conf pepper_mux_uart1_conf[] = { 1646 { 0x978, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_CTSn */ 1647 { 0x97c, MMODE(0) }, /* UART1_RTSn */ 1648 { 0x980, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_RXD */ 1649 { 0x984, MMODE(0) }, /* UART1_TXD */ 1650 { -1 } 1651 }; 1652 static const struct omap_mux_conf pepper_mux_no_uart1_conf[] = { 1653 { 0x978, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 12 */ 1654 { 0x97c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 13 */ 1655 { 0x980, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 14 */ 1656 { 0x984, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 15 */ 1657 { -1 } 1658 }; 1659 static const struct omap_mux_conf *pepper_mux_conf[] = { 1660 pepper_mux_button2_conf, 1661 pepper_mux_i2c1_conf, 1662 pepper_mux_wi2wi_conf, 1663 }; 1664 1665 int i; 1666 1667 lcd_config(); 1668 1669 for (i = 0; i < __arraycount(pepper_mux_conf); i++) 1670 gxio_omap_mux_config(pepper_mux_conf[i]); 1671 gxio_omap_mux_config_address("com", 0x48022000, 1672 pepper_mux_uart1_conf, pepper_mux_no_uart1_conf); 1673 } 1674 1675 static void 1676 c_config(void) 1677 { 1678 static const struct omap_mux_conf pepper43c_mux_ft5306_conf[] = { 1679 /* FT5306 at I2C2 */ 1680 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20 */ 1681 { 0x95c, MMODE(7) | PUDEN }, /* GPIO 5 */ 1682 { -1 } 1683 }; 1684 static const struct omap_mux_conf pepper43c_mux_i2c2_conf[] = { 1685 { 0x950, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SDA */ 1686 { 0x954, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SCL */ 1687 { -1 } 1688 }; 1689 static const struct omap_mux_conf *pepper43c_mux_conf[] = { 1690 pepper43c_mux_ft5306_conf, 1691 pepper43c_mux_i2c2_conf, 1692 }; 1693 1694 static const struct omap_gpio_conf pepper43c_gpio_ft5306_conf[] = { 1695 { 5, conf_output_0 }, /* #Reset */ 1696 { -1 } 1697 }; 1698 int i; 1699 1700 pepper43_config(); 1701 1702 for (i = 0; i < __arraycount(pepper43c_mux_conf); i++) 1703 gxio_omap_mux_config(pepper43c_mux_conf[i]); 1704 gxio_omap_gpio_config(pepper43c_gpio_ft5306_conf); 1705 } 1706 1707 static void 1708 dvi_config(void) 1709 { 1710 /* XXXX: hmm... mismatch found in Linux's dts and pubs.gumstix.org... */ 1711 1712 extern struct cfdata cfdata[]; 1713 extern const struct tifb_panel_info *tifb_panel_info; 1714 1715 static const struct tifb_panel_info panel_dvi = { 1716 .panel_tft = 1, 1717 .panel_mono = false, 1718 .panel_bpp = 16, 1719 1720 .panel_pxl_clk = 63500000, 1721 .panel_width = 1024, 1722 .panel_height = 768, 1723 .panel_hfp = 8, 1724 .panel_hbp = 4, 1725 .panel_hsw = 41, 1726 .panel_vfp = 4, 1727 .panel_vbp = 2, 1728 .panel_vsw = 10, 1729 .panel_invert_hsync = 0, 1730 .panel_invert_vsync = 0, 1731 1732 .panel_ac_bias = 255, 1733 .panel_ac_bias_intrpt = 0, 1734 .panel_dma_burst_sz = 16, 1735 .panel_fdd = 0x80, 1736 .panel_sync_edge = 0, 1737 .panel_sync_ctrl = 1, 1738 .panel_invert_pxl_clk = 0, 1739 }; 1740 cfdata_t cf = &cfdata[0]; 1741 1742 /* Disable wireless module. */ 1743 while (cf->cf_name != NULL) { 1744 if (strcmp(cf->cf_name, "sdhc") == 0 && 1745 strcmp(cf->cf_atname, "mainbus") == 0 && 1746 cf->cf_loc[MAINBUSCF_BASE] == 0x47810000) { 1747 if (cf->cf_fstate == FSTATE_NOTFOUND) 1748 cf->cf_fstate = FSTATE_DNOTFOUND; 1749 else if (cf->cf_fstate == FSTATE_STAR) 1750 cf->cf_fstate = FSTATE_DSTAR; 1751 } 1752 cf++; 1753 } 1754 1755 tifb_panel_info = &panel_dvi; 1756 } 1757 1758 static void 1759 r_config(void) 1760 { 1761 static const struct omap_mux_conf pepper43r_mux_ads7846_conf[] = { 1762 /* ADS7846 at McSPI0 */ 1763 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20: IRQ */ 1764 { -1 } 1765 }; 1766 static const struct omap_mux_conf pepper43r_mux_spi0_conf[] = { 1767 { 0x950, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_SCLK */ 1768 { 0x954, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D0 */ 1769 { 0x958, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D1 */ 1770 { 0x95c, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_CS0 */ 1771 { -1 } 1772 }; 1773 static const struct omap_mux_conf *pepper43r_mux_conf[] = { 1774 pepper43r_mux_ads7846_conf, 1775 pepper43r_mux_spi0_conf, 1776 }; 1777 int i; 1778 1779 pepper43_config(); 1780 1781 for (i = 0; i < __arraycount(pepper43r_mux_conf); i++) 1782 gxio_omap_mux_config(pepper43r_mux_conf[i]); 1783 } 1784 1785 #endif 1786 1787 #if defined(OVERO) || defined(DUOVERO) 1788 static void 1789 smsh_config(struct omap_mux_conf *smsh_mux_conf, int intr, int nreset) 1790 { 1791 struct omap_gpio_conf smsh_gpio_conf[] = { 1792 { intr, conf_input }, 1793 { nreset, conf_output_0 }, 1794 { -1 } 1795 }; 1796 1797 /* 1798 * Basically use current settings by U-Boot. 1799 * However remap physical address to configured address. 1800 */ 1801 1802 if (smsh_mux_conf != NULL) 1803 gxio_omap_mux_config(smsh_mux_conf); 1804 gxio_omap_gpio_config(smsh_gpio_conf); 1805 __udelay(100000); 1806 gxio_omap_gpio_write(nreset, 1); 1807 } 1808 #endif 1809 1810 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1811 /* 1812 * The delay for configuration time. 1813 * This function use initialized timer by U-Boot. 1814 */ 1815 static void 1816 __udelay(unsigned int usec) 1817 { 1818 #if defined(OVERO) || defined(DUOVERO) 1819 #define V_SCLK (26000000 >> 1) 1820 #define TCRR 0x28 1821 #elif defined(PEPPER) 1822 #define V_SCLK 24000000 1823 #define TCRR 0x3c 1824 #endif 1825 #define SYS_PTV 2 1826 #define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV)) 1827 1828 const vaddr_t timer_base = 1829 #if defined(OVERO) 1830 OVERO_L4_PERIPHERAL_VBASE + 0x32000; 1831 #elif defined(DUOVERO) 1832 DUOVERO_L4_PERIPHERAL_VBASE + 0x32000; 1833 #elif defined(PEPPER) 1834 PEPPER_L4_PERIPHERAL_VBASE + 0x40000; 1835 #endif 1836 long timo = usec * (TIMER_CLOCK / 1000) / 1000; 1837 uint32_t now, last; 1838 1839 last = ioreg_read(timer_base + TCRR); 1840 while (timo > 0) { 1841 now = ioreg_read(timer_base + TCRR); 1842 if (last > now) 1843 timo -= __BITS(0, 31) - last + now + 1; 1844 else 1845 timo -= now - last; 1846 last = now; 1847 } 1848 } 1849 #endif 1850 1851 #if defined(PEPPER) 1852 static int 1853 read_i2c_device(const vaddr_t i2c_base, uint16_t sa, uint8_t addr, int len, 1854 uint8_t *buf) 1855 { 1856 uint16_t v; 1857 int aok = 0, cnt = 0; 1858 1859 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1860 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1861 while (v & I2C_IRQSTATUS_BB) { 1862 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, v); 1863 __udelay(20); 1864 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1865 } 1866 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1867 1868 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1869 ioreg16_write(i2c_base + OMAP2_I2C_CNT, sizeof(addr)); 1870 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1871 I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STP | I2C_CON_STT); 1872 while (1 /*CONSTCOND*/) { 1873 __udelay(20); 1874 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1875 if ((v & I2C_IRQSTATUS_XRDY) && aok == 0) { 1876 aok = 1; 1877 ioreg16_write(i2c_base + OMAP2_I2C_DATA, addr); 1878 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1879 I2C_IRQSTATUS_XRDY); 1880 } 1881 if (v & I2C_IRQSTATUS_ARDY) { 1882 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1883 I2C_IRQSTATUS_ARDY); 1884 break; 1885 } 1886 } 1887 1888 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1889 ioreg16_write(i2c_base + OMAP2_I2C_CNT, len); 1890 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1891 I2C_CON_EN | I2C_CON_MST | I2C_CON_STP | I2C_CON_STT); 1892 while (1 /*CONSTCOND*/) { 1893 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1894 if (v & I2C_IRQSTATUS_RRDY && 1895 cnt < len) { 1896 buf[cnt++] = ioreg16_read(i2c_base + OMAP2_I2C_DATA); 1897 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1898 I2C_IRQSTATUS_RRDY); 1899 } 1900 if (v & I2C_IRQSTATUS_ARDY) { 1901 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1902 I2C_IRQSTATUS_ARDY); 1903 break; 1904 } 1905 } 1906 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1907 return 0; 1908 } 1909 #endif 1910
Indexes created Wed Oct 29 20:09:47 GMT 2025