gxio.c revision 1.24
1 /* $NetBSD: gxio.c,v 1.24 2016/10/28 19:00:48 christos Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: gxio.c,v 1.24 2016/10/28 19:00:48 christos Exp $"); 35 36 #include "opt_cputypes.h" 37 #include "opt_gumstix.h" 38 #include "opt_gxio.h" 39 #if defined(OVERO) 40 #include "opt_omap.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/device.h> 45 #include <sys/errno.h> 46 #include <sys/kernel.h> 47 48 #include <sys/systm.h> 49 50 #include <machine/bootconfig.h> 51 52 #include <arm/omap/omap2_gpmcreg.h> 53 #if defined(OMAP2) 54 #include <arm/omap/omap2_reg.h> 55 #if defined(OMAP3530) 56 #include <arm/omap/omap2_intr.h> 57 #endif 58 #endif 59 #include <arm/omap/omap_var.h> 60 #include <arm/omap/ti_iicreg.h> 61 #include <arm/omap/tifbvar.h> 62 #if defined(CPU_XSCALE) 63 #include <arm/xscale/pxa2x0cpu.h> 64 #endif 65 #include <arm/xscale/pxa2x0reg.h> 66 #include <arm/xscale/pxa2x0var.h> 67 #include <arm/xscale/pxa2x0_gpio.h> 68 #include <evbarm/gumstix/gumstixreg.h> 69 #include <evbarm/gumstix/gumstixvar.h> 70 71 #include "ioconf.h" 72 #include "locators.h" 73 74 75 struct gxioconf { 76 const char *name; 77 void (*config)(void); 78 }; 79 80 #if defined(GUMSTIX) 81 static int gxiomatch(device_t, cfdata_t, void *); 82 static void gxioattach(device_t, device_t, void *); 83 static int gxiosearch(device_t, cfdata_t, const int *, void *); 84 static int gxioprint(void *, const char *); 85 86 CFATTACH_DECL_NEW(gxio, sizeof(struct gxio_softc), 87 gxiomatch, gxioattach, NULL, NULL); 88 #endif 89 90 void gxio_config(void); 91 void gxio_config_expansion(char *); 92 #if defined(GUMSTIX) 93 static void basix_config(void); 94 static void cfstix_config(void); 95 static void etherstix_config(void); 96 static void netcf_config(void); 97 static void netcf_vx_config(void); 98 static void netduommc_config(void); 99 static void netduo_config(void); 100 static void netmicrosd_config(void); 101 static void netwifimicrosd_config(void); 102 static void netmmc_config(void); 103 static void wifistix_config(void); 104 static void wifistix_cf_config(void); 105 #elif defined(OVERO) 106 static void eth0_config(void); 107 static void eth1_config(void); 108 static void dvi_config(void); 109 static void lcd_config(char); 110 static void header_40pin_config(int); 111 112 static void chestnut_config(void); 113 static void gallop_config(void); 114 static void summit_config(void); 115 static void tobi_config(void); 116 static void tobiduo_config(void); 117 #elif defined(DUOVERO) 118 static void ehci_config(void); 119 120 static void parlor_config(void); 121 #elif defined(PEPPER) 122 static void lcd_config(void); 123 static void pepper43_config(void); 124 125 static void pepper_config(void); 126 static void c_config(void); 127 static void dvi_config(void); 128 static void r_config(void); 129 #endif 130 #if defined(OVERO) || defined(DUOVERO) 131 struct omap_mux_conf; 132 static void smsh_config(struct omap_mux_conf *, int, int); 133 #endif 134 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 135 static void __udelay(unsigned int); 136 #endif 137 #if defined(PEPPER) 138 static int read_i2c_device(const vaddr_t, uint16_t, uint8_t, int, uint8_t *); 139 #endif 140 141 #if defined(CPU_XSCALE_PXA250) 142 143 static struct pxa2x0_gpioconf pxa255dep_gpioconf[] = { 144 /* Bluetooth module configuration */ 145 { 7, GPIO_OUT | GPIO_SET }, /* power on */ 146 { 12, GPIO_ALT_FN_1_OUT }, /* 32kHz out. required by SingleStone */ 147 148 /* AC97 configuration */ 149 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 150 151 /* FFUART configuration */ 152 { 35, GPIO_ALT_FN_1_IN }, /* CTS */ 153 { 41, GPIO_ALT_FN_2_OUT }, /* RTS */ 154 155 #ifndef GXIO_BLUETOOTH_ON_HWUART 156 /* BTUART configuration */ 157 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 158 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 159 #else 160 /* HWUART configuration */ 161 { 42, GPIO_ALT_FN_3_IN }, /* HWRXD */ 162 { 43, GPIO_ALT_FN_3_OUT }, /* HWTXD */ 163 { 44, GPIO_ALT_FN_3_IN }, /* HWCTS */ 164 { 45, GPIO_ALT_FN_3_OUT }, /* HWRTS */ 165 #endif 166 167 #ifndef GXIO_BLUETOOTH_ON_HWUART 168 /* HWUART configuration */ 169 { 48, GPIO_ALT_FN_1_OUT }, /* HWTXD */ 170 { 49, GPIO_ALT_FN_1_IN }, /* HWRXD */ 171 { 50, GPIO_ALT_FN_1_IN }, /* HWCTS */ 172 { 51, GPIO_ALT_FN_1_OUT }, /* HWRTS */ 173 #endif 174 175 { -1 } 176 }; 177 #endif 178 #if defined(CPU_XSCALE_PXA270) 179 static struct pxa2x0_gpioconf verdexdep_gpioconf[] = { 180 /* Bluetooth module configuration */ 181 { 9, GPIO_ALT_FN_3_OUT }, /* CHOUT<0> */ 182 { 12, GPIO_OUT | GPIO_SET }, 183 184 /* LCD configuration */ 185 { 17, GPIO_IN }, /* backlight on */ 186 187 /* FFUART configuration */ 188 { 34, GPIO_ALT_FN_1_IN }, /* FFRXD */ 189 { 39, GPIO_ALT_FN_2_OUT }, /* FFTXD */ 190 191 /* BTUART configuration */ 192 { 42, GPIO_ALT_FN_1_IN }, /* BTRXD */ 193 { 43, GPIO_ALT_FN_2_OUT }, /* BTTXD */ 194 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 195 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 196 197 /* AC97 configuration */ 198 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 199 200 { -1 } 201 }; 202 203 #elif defined(OMAP2) 204 205 struct omap_mux_conf { 206 int offset; 207 uint32_t value; 208 /* OMAP3/4 register values */ 209 #define WAKEUPEVENT (1 << 15) 210 #define WAKEUPENABLE (1 << 14) 211 #define OFFMODEPULLTYPESELECT (1 << 13) 212 #define OFFMODEPULLUDENABLE (1 << 12) 213 #define OFFMODEOUTVALUE (1 << 11) 214 #define OFFMODEOUTENABLE (1 << 10) 215 #define OFFMODEENABLE (1 << 9) 216 #define INPUTENABLE (1 << 8) 217 #define PULLTYPESELECT (1 << 4) 218 #define PULLUDENABLE (1 << 3) 219 #define MUXMODE(n) ((n) & 0x7) 220 221 /* Sitara AM3xxx register values */ 222 #define SLEWCTRL (1 << 6) 223 #define RXACTIVE (1 << 5) 224 #define PUTYPESEL (1 << 4) 225 #define PUDEN (1 << 3) 226 #define MMODE(n) ((n) & 0x7) 227 }; 228 struct omap_gpio_conf { 229 int pin; 230 enum { 231 conf_input = -1, 232 conf_output_0, 233 conf_output_1, 234 } conf; 235 }; 236 237 static void gxio_omap_mux_config(const struct omap_mux_conf []); 238 static int gxio_omap_mux_config_address(const char *, unsigned long, 239 const struct omap_mux_conf[], 240 const struct omap_mux_conf[]); 241 static void gxio_omap_gpio_config(const struct omap_gpio_conf[]); 242 void gxio_omap_gpio_write(int, int); 243 244 static const struct omap_mux_conf overo_mux_i2c3_conf[] = { 245 { 0x1c2, MUXMODE(0) | INPUTENABLE }, /* i2c3_scl */ 246 { 0x1c4, MUXMODE(0) | INPUTENABLE }, /* i2c3_sda */ 247 { -1 } 248 }; 249 static const struct omap_mux_conf overo_mux_mmchs2_conf[] = { 250 { 0x158, /* mmc2_clk */ 251 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 252 { 0x15a, /* mmc2_cmd */ 253 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 254 { 0x15c, /* mmc2_dat0 */ 255 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 256 { 0x15e, /* mmc2_dat1 */ 257 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 258 { 0x160, /* mmc2_dat2 */ 259 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 260 { 0x162, /* mmc2_dat3 */ 261 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 262 { -1 } 263 }; 264 #if defined(OVERO) 265 static const struct omap_mux_conf overo_mux_wireless_conf[] = { 266 { 0x0b4, MUXMODE(4) }, /* gpio_54:BT_nPOWERON*/ 267 { 0x0bc, MUXMODE(4) | INPUTENABLE }, /* gpio_58: WIFI_IRQ */ 268 { 0x19c, MUXMODE(4) }, /* gpio_164:BT_nRESET */ 269 { 0x5e0, MUXMODE(4) }, /* gpio_16: W2W_nRESET*/ 270 { -1 } 271 }; 272 273 #elif defined(DUOVERO) 274 static const struct omap_mux_conf duovero_mux_led_conf[] = { 275 { 0x116, MUXMODE(3) }, /* GPIO 122 */ 276 { -1 } 277 }; 278 static const struct omap_mux_conf duovero_mux_button_conf[] = { 279 { 0x114, /* GPIO 121 */ 280 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 281 { -1 } 282 }; 283 284 #elif defined(PEPPER) 285 static const struct omap_mux_conf pepper_mux_led_conf[] = { 286 { 0x850, MMODE(7) | PUDEN }, /* GPIO 52: Blue */ 287 { 0x854, MMODE(7) | PUDEN }, /* GPIO 53: Red */ 288 { -1 } 289 }; 290 static const struct omap_mux_conf pepper_mux_button_conf[] = { 291 { 0x858, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 54 */ 292 { -1 } 293 }; 294 static const struct omap_mux_conf pepper_mux_mmchs3_conf[] = { 295 { 0x844, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT0 */ 296 { 0x848, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT1 */ 297 { 0x84c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT2 */ 298 { 0x878, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT3 */ 299 { 0x888, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CMD */ 300 { 0x88c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CLK */ 301 { -1 } 302 }; 303 static const struct omap_mux_conf pepper_mux_audio_codec_conf[] = { 304 { 0x840, MMODE(7) | PUDEN }, /* GPIO 48: #Reset */ 305 { -1 } 306 }; 307 #endif 308 309 #endif 310 311 static const struct gxioconf gxioconflist[] = { 312 #if defined(GUMSTIX) 313 { "basix", basix_config }, 314 { "cfstix", cfstix_config }, 315 { "etherstix", etherstix_config }, 316 { "netcf", netcf_config }, 317 { "netcf-vx", netcf_vx_config }, 318 { "netduo-mmc", netduommc_config }, 319 { "netduo", netduo_config }, 320 { "netmicrosd", netmicrosd_config }, 321 { "netmicrosd-vx", netmicrosd_config }, 322 { "netwifimicrosd", netwifimicrosd_config }, 323 { "netmmc", netmmc_config }, 324 { "netpro-vx", netwifimicrosd_config }, 325 { "wifistix-cf", wifistix_cf_config }, 326 { "wifistix", wifistix_config }, 327 #elif defined(OVERO) 328 { "chestnut43", chestnut_config }, 329 { "gallop43", gallop_config }, 330 { "summit", summit_config }, 331 { "tobi", tobi_config }, 332 { "tobi-duo", tobiduo_config }, 333 #elif defined(DUOVERO) 334 { "parlor", parlor_config }, 335 #elif defined(PEPPER) 336 { "43c", c_config }, 337 { "43r", r_config }, 338 { "dvi", dvi_config }, 339 #endif 340 { NULL } 341 }; 342 343 int gxpcic_gpio_reset; 344 struct gxpcic_slot_irqs gxpcic_slot_irqs[2] = { { 0, -1, -1 }, { 0, -1, -1 } }; 345 346 347 #if defined(GUMSTIX) 348 /* ARGSUSED */ 349 static int 350 gxiomatch(device_t parent, cfdata_t match, void *aux) 351 { 352 353 struct pxaip_attach_args *pxa = aux; 354 bus_space_tag_t iot = &pxa2x0_bs_tag; 355 bus_space_handle_t ioh; 356 357 if (strcmp(pxa->pxa_name, match->cf_name) != 0 || 358 pxa->pxa_addr != PXAIPCF_ADDR_DEFAULT) 359 return 0; 360 361 if (bus_space_map(iot, 362 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &ioh)) 363 return 0; 364 bus_space_unmap(iot, ioh, PXA2X0_MEMCTL_SIZE); 365 366 /* nothing */ 367 return 1; 368 } 369 370 /* ARGSUSED */ 371 static void 372 gxioattach(device_t parent, device_t self, void *aux) 373 { 374 struct gxio_softc *sc = device_private(self); 375 376 aprint_normal("\n"); 377 aprint_naive("\n"); 378 379 sc->sc_dev = self; 380 sc->sc_iot = &pxa2x0_bs_tag; 381 382 if (bus_space_map(sc->sc_iot, 383 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &sc->sc_ioh)) 384 return; 385 386 /* 387 * Attach each gumstix(busheader)/overo expansion board devices. 388 */ 389 config_search_ia(gxiosearch, self, "gxio", NULL); 390 } 391 392 /* ARGSUSED */ 393 static int 394 gxiosearch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 395 { 396 struct gxio_softc *sc = device_private(parent); 397 struct gxio_attach_args gxa; 398 399 gxa.gxa_sc = sc; 400 gxa.gxa_iot = sc->sc_iot; 401 gxa.gxa_addr = cf->cf_loc[GXIOCF_ADDR]; 402 gxa.gxa_gpirq = cf->cf_loc[GXIOCF_GPIRQ]; 403 404 if (config_match(parent, cf, &gxa)) 405 config_attach(parent, cf, &gxa, gxioprint); 406 407 return 0; 408 } 409 410 /* ARGSUSED */ 411 static int 412 gxioprint(void *aux, const char *name) 413 { 414 struct gxio_attach_args *gxa = (struct gxio_attach_args *)aux; 415 416 if (gxa->gxa_addr != GXIOCF_ADDR_DEFAULT) 417 printf(" addr 0x%lx", gxa->gxa_addr); 418 if (gxa->gxa_gpirq > 0) 419 printf(" gpirq %d", gxa->gxa_gpirq); 420 return UNCONF; 421 } 422 #endif 423 424 425 #if defined(GUMSTIX) 426 /* 427 * configure for GPIO pin and expansion boards. 428 */ 429 void 430 gxio_config(void) 431 { 432 #if defined(CPU_XSCALE_PXA250) 433 struct pxa2x0_gpioconf *gumstix_gpioconf[] = { 434 pxa25x_com_ffuart_gpioconf, 435 pxa25x_com_stuart_gpioconf, 436 #ifndef GXIO_BLUETOOTH_ON_HWUART 437 pxa25x_com_btuart_gpioconf, 438 #endif 439 pxa25x_com_hwuart_gpioconf, 440 pxa25x_i2c_gpioconf, 441 pxa25x_pxaacu_gpioconf, 442 pxa255dep_gpioconf, 443 NULL 444 }; 445 #endif 446 #if defined(CPU_XSCALE_PXA270) 447 struct pxa2x0_gpioconf *verdex_gpioconf[] = { 448 pxa27x_com_ffuart_gpioconf, 449 pxa27x_com_stuart_gpioconf, 450 pxa27x_com_btuart_gpioconf, 451 pxa27x_i2c_gpioconf, 452 pxa27x_pxaacu_gpioconf, 453 pxa27x_pxamci_gpioconf, 454 pxa27x_ohci_gpioconf, 455 verdexdep_gpioconf, 456 NULL 457 }; 458 #endif 459 460 /* XXX: turn off for power of bluetooth module */ 461 #if defined(CPU_XSCALE_PXA250) 462 pxa2x0_gpio_set_function(7, GPIO_OUT | GPIO_CLR); 463 #elif defined(CPU_XSCALE_PXA270) 464 pxa2x0_gpio_set_function(12, GPIO_OUT | GPIO_CLR); 465 #endif 466 delay(100); 467 468 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 469 pxa2x0_gpio_config( 470 (CPU_IS_PXA250) ? gumstix_gpioconf : verdex_gpioconf); 471 #elif defined(CPU_XSCALE_PXA270) || defined(CPU_XSCALE_PXA250) 472 #if defined(CPU_XSCALE_PXA270) 473 pxa2x0_gpio_config(verdex_gpioconf); 474 #else 475 pxa2x0_gpio_config(gumstix_gpioconf); 476 #endif 477 #endif 478 } 479 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 480 static void 481 gxio_omap_mux_config(const struct omap_mux_conf mux_conf[]) 482 { 483 #if defined(OVERO) 484 const vaddr_t ctrlmod_base = OVERO_L4_CORE_VBASE + 0x2000; 485 #elif defined(DUOVERO) 486 const vaddr_t ctrlmod_base = DUOVERO_L4_CM_VBASE; 487 #elif defined(PEPPER) 488 const vaddr_t ctrlmod_base = PEPPER_PRCM_VBASE + 0x10000; 489 #endif 490 int i; 491 492 for (i = 0; mux_conf[i].offset != -1; i++) 493 #if !defined(TI_AM335X) 494 ioreg16_write(ctrlmod_base + mux_conf[i].offset, 495 mux_conf[i].value); 496 #else 497 ioreg_write(ctrlmod_base + mux_conf[i].offset, 498 mux_conf[i].value); 499 #endif 500 } 501 502 static int 503 gxio_omap_mux_config_address(const char *name, unsigned long address, 504 const struct omap_mux_conf mux_conf[], 505 const struct omap_mux_conf not_mux_conf[]) 506 { 507 extern struct cfdata cfdata[]; 508 cfdata_t cf = &cfdata[0]; 509 510 while (cf->cf_name != NULL) { 511 if (strcmp(name, cf->cf_name) == 0 && 512 address == cf->cf_loc[OBIOCF_ADDR]) { 513 gxio_omap_mux_config(mux_conf); 514 return 0; 515 } 516 cf++; 517 } 518 519 if (not_mux_conf == NULL) 520 return -1; 521 522 gxio_omap_mux_config(not_mux_conf); 523 return 0; 524 } 525 526 #if defined(OVERO) 527 #define gpio_reg_read ioreg_read 528 #define gpio_reg_write ioreg_write 529 #elif defined(DUOVERO) || defined(PEPPER) 530 #define gpio_reg_read(a) ioreg_read((a) + GPIO_SIZE2) 531 #define gpio_reg_write(a, v) ioreg_write((a) + GPIO_SIZE2, (v)) 532 #endif 533 534 static const vaddr_t gpio_bases[] = { 535 #if defined(OVERO) 536 #define OVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 537 #define GPIO(n) GPIO ## n ## _BASE_3530 538 #define BASE(a, n) \ 539 (OVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP3530_L4_ ## a ## _BASE)) 540 541 GPIO1_BASE_3530, 542 GPIO2_BASE_3530, 543 GPIO3_BASE_3530, 544 GPIO4_BASE_3530, 545 GPIO5_BASE_3530, 546 GPIO6_BASE_3530, 547 548 #elif defined(DUOVERO) 549 #define DUOVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 550 #define GPIO(n) GPIO ## n ## _BASE_4430 551 #define BASE(a, n) \ 552 (DUOVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP4430_L4_ ## a ## _BASE)) 553 554 DUOVERO_GPIO_VBASE(1), 555 DUOVERO_GPIO_VBASE(2), 556 DUOVERO_GPIO_VBASE(3), 557 DUOVERO_GPIO_VBASE(4), 558 DUOVERO_GPIO_VBASE(5), 559 560 #elif defined(PEPPER) 561 #define PEPPER_GPIO_VBASE(n) ((n) == 0 ? WAKEUP(n) : PERIPHERAL(n)) 562 #define GPIO(n) GPIO ## n ## _BASE_TI_AM335X 563 #define WAKEUP(n) (PEPPER_PRCM_VBASE + (GPIO(n) - OMAP2_CM_BASE)) 564 #define PERIPHERAL(n) \ 565 (PEPPER_L4_PERIPHERAL_VBASE + (GPIO(n) - TI_AM335X_L4_PERIPHERAL_BASE)) 566 567 PEPPER_GPIO_VBASE(0), 568 PEPPER_GPIO_VBASE(1), 569 PEPPER_GPIO_VBASE(2), 570 PEPPER_GPIO_VBASE(3), 571 #endif 572 }; 573 574 static void 575 gxio_omap_gpio_config(const struct omap_gpio_conf gpio_conf[]) 576 { 577 vaddr_t gpio_base; 578 int mask, i; 579 580 for (i = 0; gpio_conf[i].pin != -1; i++) { 581 gpio_base = gpio_bases[gpio_conf[i].pin / 32]; 582 mask = 1 << (gpio_conf[i].pin % 32); 583 switch (gpio_conf[i].conf) { 584 case conf_input: 585 ioreg_write(gpio_base + GPIO_OE, 586 ioreg_read(gpio_base + GPIO_OE) | mask); 587 break; 588 case conf_output_0: 589 ioreg_write(gpio_base + GPIO_OE, 590 ioreg_read(gpio_base + GPIO_OE) | ~mask); 591 #if 0 592 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 593 #else 594 ioreg_write(gpio_base + GPIO_DATAOUT, 595 ioreg_read(gpio_base + GPIO_DATAOUT) & ~mask); 596 #endif 597 break; 598 case conf_output_1: 599 ioreg_write(gpio_base + GPIO_OE, 600 ioreg_read(gpio_base + GPIO_OE) | ~mask); 601 #if 0 602 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 603 #else 604 ioreg_write(gpio_base + GPIO_DATAOUT, 605 ioreg_read(gpio_base + GPIO_DATAOUT) | mask); 606 #endif 607 break; 608 } 609 } 610 } 611 612 void 613 gxio_omap_gpio_write(int pin, int val) 614 { 615 vaddr_t gpio_base; 616 int mask; 617 618 KASSERT(pin / 32 < __arraycount(gpio_bases)); 619 620 gpio_base = gpio_bases[pin / 32]; 621 mask = 1 << (pin % 32); 622 if (val == 0) 623 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 624 else 625 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 626 } 627 628 /* 629 * configure for MUX, GPIO. 630 */ 631 void 632 gxio_config(void) 633 { 634 const struct omap_mux_conf *mux_conf[] = { 635 #if defined(OVERO) 636 overo_mux_i2c3_conf, 637 overo_mux_mmchs2_conf, 638 overo_mux_wireless_conf, 639 #elif defined(DUOVERO) 640 duovero_mux_led_conf, 641 duovero_mux_button_conf, 642 #elif defined(PEPPER) 643 pepper_mux_led_conf, 644 pepper_mux_button_conf, 645 pepper_mux_mmchs3_conf, 646 pepper_mux_audio_codec_conf, 647 #endif 648 }; 649 const struct omap_gpio_conf gpio_conf[] = { 650 #if defined(OVERO) 651 { 16, conf_output_0 }, /* Wireless: #Reset */ 652 #elif defined(PEPPER) 653 { 48, conf_output_0 }, /* Audio Codec: #Reset */ 654 #endif 655 { -1 } 656 }; 657 int i; 658 659 for (i = 0; i < __arraycount(mux_conf); i++) 660 gxio_omap_mux_config(mux_conf[i]); 661 gxio_omap_gpio_config(gpio_conf); 662 } 663 #endif 664 665 void 666 gxio_config_expansion(char *expansion) 667 { 668 int i, d, s; 669 670 if (expansion == NULL) { 671 printf("not specified 'expansion=' in the boot args.\n"); 672 s = -1; 673 } else { 674 for (i = 0; gxioconflist[i].name != NULL; i++) 675 if (strncasecmp(gxioconflist[i].name, expansion, 676 strlen(gxioconflist[i].name) + 1) == 0) 677 break; 678 if (gxioconflist[i].name == NULL) 679 printf("unknown expansion specified: %s\n", expansion); 680 s = i; 681 } 682 #ifdef GXIO_DEFAULT_EXPANSION 683 for (i = 0; gxioconflist[i].name != NULL; i++) 684 if (strncasecmp(gxioconflist[i].name, GXIO_DEFAULT_EXPANSION, 685 strlen(gxioconflist[i].name) + 1) == 0) 686 break; 687 d = i; 688 #else 689 d = -1; 690 #endif 691 printf("supported expansions:\n"); 692 for (i = 0; gxioconflist[i].name != NULL; i++) 693 printf(" %s%s\n", 694 gxioconflist[i].name, 695 i == d ? " (DEFAULT)" : ""); 696 697 if (s < 0 || gxioconflist[i].name == NULL) { 698 #ifdef GXIO_DEFAULT_EXPANSION 699 expansion = __UNCONST(GXIO_DEFAULT_EXPANSION); 700 #else 701 return; 702 #endif 703 } 704 705 #if defined(PEPPER) 706 if (s < 0) { 707 struct pepper_board_id { 708 unsigned int device_vendor; 709 #define GUMSTIX_PEPPER 0x30000200 /* 1st gen */ 710 #define GUMSTIX_PEPPER_DVI 0x31000200 /* DVI and newer */ 711 unsigned char revision; 712 unsigned char content; 713 char fab_revision[8]; 714 char env_var[16]; 715 char env_setting[64]; 716 } id; 717 const vaddr_t i2c_base = PEPPER_PRCM_VBASE + 0xb000; 718 const uint8_t eeprom = 0x50; 719 const uint8_t len = sizeof(id); 720 int rv; 721 722 rv = read_i2c_device(i2c_base, eeprom, 0x00, len, (void *)&id); 723 if (rv == 0) 724 if (id.device_vendor == GUMSTIX_PEPPER) { 725 printf("configure auto detected expansion" 726 " (pepper)\n"); 727 pepper_config(); 728 return; 729 } 730 } 731 #endif 732 733 printf("configure %s expansion (%s)\n", 734 (s < 0 || gxioconflist[i].name == NULL) ? "default" : "specified", 735 expansion); 736 gxioconflist[(s < 0 || gxioconflist[i].name == NULL) ? d : s].config(); 737 } 738 739 740 #if defined(GUMSTIX) 741 742 static void 743 basix_config(void) 744 { 745 746 pxa2x0_gpio_set_function(8, GPIO_ALT_FN_1_OUT); /* MMCCS0 */ 747 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_1_OUT); /* MMCCLK */ 748 #if 0 749 /* this configuration set by gxmci.c::pxamci_attach() */ 750 pxa2x0_gpio_set_function(11, GPIO_IN); /* nSD_DETECT */ 751 pxa2x0_gpio_set_function(22, GPIO_IN); /* nSD_WP */ 752 #endif 753 } 754 755 static void 756 cfstix_config(void) 757 { 758 u_int gpio, npoe_fn; 759 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 760 int bvd = (CPU_IS_PXA250) ? 4 : 111; 761 #else 762 #if defined(CPU_XSCALE_PXA270) 763 const int bvd = 111; 764 #else 765 const int bvd = 4; 766 #endif 767 #endif 768 769 if (CPU_IS_PXA250) { 770 gxpcic_slot_irqs[0].valid = 1; 771 gxpcic_slot_irqs[0].cd = 11; 772 gxpcic_slot_irqs[0].prdy = 26; 773 gxpcic_gpio_reset = 8; 774 } else { 775 gxpcic_slot_irqs[0].valid = 1; 776 gxpcic_slot_irqs[0].cd = 104; 777 gxpcic_slot_irqs[0].prdy = 96; 778 gxpcic_gpio_reset = 97; 779 } 780 781 #if 1 782 /* PCD/PRDY set by pxa2x0_pcic.c::pxapcic_attach_common() */ 783 #else 784 pxa2x0_gpio_set_function(11, GPIO_IN); /* PCD1 */ 785 pxa2x0_gpio_set_function(26, GPIO_IN); /* PRDY1/~IRQ1 */ 786 #endif 787 pxa2x0_gpio_set_function(bvd, GPIO_IN); /* BVD1/~STSCHG1 */ 788 789 for (gpio = 48, npoe_fn = 0; gpio <= 53 ; gpio++) 790 npoe_fn |= pxa2x0_gpio_get_function(gpio); 791 npoe_fn &= GPIO_SET; 792 793 pxa2x0_gpio_set_function(48, GPIO_ALT_FN_2_OUT | npoe_fn); /* nPOE */ 794 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 795 pxa2x0_gpio_set_function(50, GPIO_ALT_FN_2_OUT); /* nPIOR */ 796 pxa2x0_gpio_set_function(51, GPIO_ALT_FN_2_OUT); /* nPIOW */ 797 if (CPU_IS_PXA250) { 798 pxa2x0_gpio_set_function(52, GPIO_ALT_FN_2_OUT); /* nPCE1 */ 799 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_2_OUT); /* nPCE2 */ 800 pxa2x0_gpio_set_function(54, GPIO_ALT_FN_2_OUT); /* pSKTSEL */ 801 } else { 802 pxa2x0_gpio_set_function(102, GPIO_ALT_FN_1_OUT); /* nPCE1 */ 803 pxa2x0_gpio_set_function(105, GPIO_ALT_FN_1_OUT); /* nPCE2 */ 804 pxa2x0_gpio_set_function(79, GPIO_ALT_FN_1_OUT); /* pSKTSEL */ 805 } 806 pxa2x0_gpio_set_function(55, GPIO_ALT_FN_2_OUT); /* nPREG */ 807 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); /* nPWAIT */ 808 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); /* nIOIS16 */ 809 } 810 811 static void 812 etherstix_config(void) 813 { 814 extern struct cfdata cfdata[]; 815 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 816 int rst = (CPU_IS_PXA250) ? 80 : 32; 817 int irq = (CPU_IS_PXA250) ? 36 : 99; 818 #else 819 #if defined(CPU_XSCALE_PXA270) 820 const int rst = 32, irq = 99; 821 #else 822 const int rst = 80, irq = 36; 823 #endif 824 #endif 825 int i; 826 827 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 828 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 829 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_SET); /* RESET 1 */ 830 delay(1); 831 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_CLR); 832 delay(50000); 833 834 for (i = 0; cfdata[i].cf_name != NULL; i++) 835 if (strcmp(cfdata[i].cf_name, "sm") == 0 && 836 strcmp(cfdata[i].cf_atname, "sm_gxio") == 0 && 837 cfdata[i].cf_loc[GXIOCF_ADDR] == 0x04000300 && 838 cfdata[i].cf_loc[GXIOCF_GPIRQ] == GXIOCF_GPIRQ_DEFAULT) 839 cfdata[i].cf_loc[GXIOCF_GPIRQ] = irq; 840 } 841 842 static void 843 netcf_config(void) 844 { 845 846 etherstix_config(); 847 cfstix_config(); 848 } 849 850 static void 851 netcf_vx_config(void) 852 { 853 854 /* 855 * XXXX: More power is necessary for NIC and USB??? 856 * (no document. from Linux) 857 */ 858 859 pxa2x0_gpio_set_function(27, GPIO_IN); 860 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); 861 pxa2x0_gpio_set_function(118, GPIO_ALT_FN_1_IN | GPIO_CLR); 862 863 etherstix_config(); 864 cfstix_config(); 865 if (CPU_IS_PXA270) { 866 /* Overwrite */ 867 gxpcic_slot_irqs[0].cd = 104; 868 gxpcic_slot_irqs[0].prdy = 109; 869 gxpcic_gpio_reset = 110; 870 }; 871 } 872 873 static void 874 netduommc_config(void) 875 { 876 877 netduo_config(); 878 basix_config(); 879 } 880 881 static void 882 netduo_config(void) 883 { 884 885 etherstix_config(); 886 887 pxa2x0_gpio_set_function(78, GPIO_ALT_FN_2_OUT); /* nCS 2 */ 888 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_SET); /* RESET 2 */ 889 delay(1); 890 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_CLR); 891 delay(50000); 892 } 893 894 static void 895 netmicrosd_config(void) 896 { 897 898 /* MicroSD(mci) always configure on PXA270 */ 899 900 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 901 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 902 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); /* RESET 1 */ 903 delay(hz / 2); 904 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_SET); 905 delay(50000); 906 } 907 908 static void 909 netwifimicrosd_config(void) 910 { 911 912 netmicrosd_config(); 913 914 cfstix_config(); 915 /* However use pxamci. */ 916 pxa2x0_gpio_set_function(111, GPIO_CLR | GPIO_ALT_FN_1_IN); 917 /* Power to Marvell 88W8385 */ 918 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 919 } 920 921 static void 922 netmmc_config(void) 923 { 924 925 etherstix_config(); 926 basix_config(); 927 } 928 929 static void 930 wifistix_config(void) 931 { 932 933 cfstix_config(); 934 935 /* Power to Marvell 88W8385 */ 936 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 937 } 938 939 static void 940 wifistix_cf_config(void) 941 { 942 943 gxpcic_slot_irqs[1].valid = 1; 944 gxpcic_slot_irqs[1].cd = 36; 945 gxpcic_slot_irqs[1].prdy = 27; 946 947 #if 1 948 /* this configuration set by pxa2x0_pcic.c::pxapcic_attach_common() */ 949 #else 950 pxa2x0_gpio_set_function(36, GPIO_IN); /* PCD2 */ 951 pxa2x0_gpio_set_function(27, GPIO_IN); /* PRDY2/~IRQ2 */ 952 #endif 953 pxa2x0_gpio_set_function(18, GPIO_IN); /* BVD2/~STSCHG2 */ 954 955 cfstix_config(); 956 957 /* Power to Marvell 88W8385 */ 958 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 959 } 960 961 #elif defined(OVERO) 962 963 static void 964 eth0_config(void) 965 { 966 /* 967 * ETH0 connects via CS5. It use GPIO 176 for IRQ. 968 * Also GPIO 64 is NRESET. 969 */ 970 971 smsh_config(NULL, 176, 64); 972 } 973 974 static void 975 eth1_config(void) 976 { 977 struct omap_mux_conf eth1_mux_conf[] = { 978 { 0x0d2, MUXMODE(4) | INPUTENABLE }, 979 { -1 } 980 }; 981 982 /* 983 * ETH1 connects via CS4. It use GPIO 65 for IRQ. 984 */ 985 986 smsh_config(eth1_mux_conf, 65, 64); 987 } 988 989 static void 990 dvi_config(void) 991 { 992 static const struct omap_mux_conf overo_mux_dvi_conf[] = { 993 { 0x0d4, MUXMODE(0) }, /* dss_pclk */ 994 { 0x0d6, MUXMODE(0) }, /* dss_pclk */ 995 { 0x0d8, MUXMODE(0) }, /* dss_pclk */ 996 { 0x0da, MUXMODE(0) }, /* dss_pclk */ 997 { 0x0dc, MUXMODE(0) }, /* dss_pclk */ 998 { 0x0de, MUXMODE(0) }, /* dss_pclk */ 999 { 0x0e0, MUXMODE(0) }, /* dss_pclk */ 1000 { 0x0e2, MUXMODE(0) }, /* dss_pclk */ 1001 { 0x0e4, MUXMODE(0) }, /* dss_pclk */ 1002 { 0x0e6, MUXMODE(0) }, /* dss_pclk */ 1003 { 0x0e8, MUXMODE(0) }, /* dss_pclk */ 1004 { 0x0ea, MUXMODE(0) }, /* dss_pclk */ 1005 { 0x0ec, MUXMODE(0) }, /* dss_pclk */ 1006 { 0x0ee, MUXMODE(0) }, /* dss_pclk */ 1007 { 0x0f0, MUXMODE(0) }, /* dss_pclk */ 1008 { 0x0f2, MUXMODE(0) }, /* dss_pclk */ 1009 { 0x0f4, MUXMODE(0) }, /* dss_pclk */ 1010 { 0x0f6, MUXMODE(0) }, /* dss_pclk */ 1011 { 0x0f8, MUXMODE(0) }, /* dss_pclk */ 1012 { 0x0fa, MUXMODE(0) }, /* dss_pclk */ 1013 { 0x0fc, MUXMODE(0) }, /* dss_pclk */ 1014 { 0x0fe, MUXMODE(0) }, /* dss_pclk */ 1015 { 0x100, MUXMODE(0) }, /* dss_pclk */ 1016 { 0x102, MUXMODE(0) }, /* dss_pclk */ 1017 { 0x104, MUXMODE(0) }, /* dss_pclk */ 1018 { 0x106, MUXMODE(0) }, /* dss_pclk */ 1019 { 0x108, MUXMODE(0) }, /* dss_pclk */ 1020 { 0x10a, MUXMODE(0) }, /* dss_pclk */ 1021 { -1 } 1022 }; 1023 1024 gxio_omap_mux_config(overo_mux_dvi_conf); 1025 } 1026 1027 static void 1028 lcd_config(char type) 1029 { 1030 static const struct omap_mux_conf overo_mux_mcspi1_conf[] = { 1031 { 0x1c8, MUXMODE(0) | INPUTENABLE }, /* mcspi1_clk */ 1032 { 0x1ca, MUXMODE(0) | INPUTENABLE }, /* mcspi1_simo*/ 1033 { 0x1cc, MUXMODE(0) | INPUTENABLE }, /* mcspi1_somi*/ 1034 { 0x1ce, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs0 */ 1035 { 0x1d0, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs1 */ 1036 { -1 } 1037 }; 1038 static const struct omap_mux_conf overo_mux_ads7846_conf[] = { 1039 { 0x138, /* gpio_114: NPENIRQ */ 1040 MUXMODE(4) | PULLUDENABLE | INPUTENABLE }, 1041 { -1 } 1042 }; 1043 static const struct omap_mux_conf overo_mux_lcd_conf[] = { 1044 { 0x174, MUXMODE(4) }, /* gpio_144: DISPLAY_EN */ 1045 { 0x176, MUXMODE(4) }, /* gpio_145: Brightness */ 1046 { -1 } 1047 }; 1048 1049 static const struct omap_gpio_conf overo_gpio_lcd_conf[] = { 1050 { 144, conf_output_0 }, /* DISPLAY_EN */ 1051 { 145, conf_output_0 }, /* Brightness */ 1052 { -1 } 1053 }; 1054 1055 dvi_config(); 1056 if (type != 'C') { 1057 gxio_omap_mux_config(overo_mux_mcspi1_conf); 1058 gxio_omap_mux_config(overo_mux_ads7846_conf); 1059 } 1060 gxio_omap_mux_config(overo_mux_lcd_conf); 1061 1062 gxio_omap_gpio_config(overo_gpio_lcd_conf); 1063 } 1064 1065 enum { 1066 uart1_if_exists = 0, 1067 force_uart1 1068 }; 1069 static void 1070 header_40pin_config(int uart1) 1071 { 1072 static const struct omap_mux_conf overo_mux_40pin_header_conf[] = { 1073 /* 1074 * 1: GND 1075 * 2: VCC_3.3 1076 * 3: GPIO171_SPI1_CLK 1077 * 4: GPIO114_SPI1_NIRQ 1078 * 5: GPIO172_SPI1_MOSI 1079 * 6: GPIO174_SPI1_CS0 1080 * 7: GPIO173_SPI1_MISO 1081 * 8: GPIO175_SPI1_CS1 1082 * 9: GPIO151_RXD1 1083 * 10: GPIO148_TXD1 1084 * 11: SYS_EN 1085 * 12: VBACKUP 1086 * 13: GPIO0_WAKEUP 1087 * 14: POWERON 1088 * 15: GND 1089 * 16: VCC_1.8 1090 * 17: GPIO128_GPS_PPS 1091 * 18: GPIO127_TS_IRQ 1092 * 19: GPIO170_HDQ_1WIRE 1093 * 20: GPIO163_IR_CTS3 1094 * 21: GPIO165_IR_RXD3 (console) 1095 * 22: GPIO166_IR_TXD3 (console) 1096 * 23: GPIO184_SCL3 (system eeprom) 1097 * 24: GPIO185_SDA3 (system eeprom) 1098 * 25: GND 1099 * 26: VCC_1.8 1100 * 27: GPIO146_PWM11 1101 * 28: GPIO145_PWM10 1102 * 29: GPIO147_PWM8 1103 * 30: GPIO144_PWM9 1104 * 31: PWM0 (TPS65950) 1105 * 32: PWM1 (TPS65950) 1106 * 33: ADCIN7 (TPS65950) 1107 * 34: ADCIN2 (TPS65950) 1108 * 35: ADCIN6 (TPS65950) 1109 * 36: ADCIN5 (TPS65950) 1110 * 37: AGND (TPS65950) 1111 * 38: ADCIN3 (TPS65950) 1112 * 39: ADCIN4 (TPS65950) 1113 * 40: VIN (TPS65950) 1114 */ 1115 1116 { 0x152, MUXMODE(4) | INPUTENABLE }, /* gpio_127 */ 1117 { 0x154, MUXMODE(4) | INPUTENABLE }, /* gpio_128 */ 1118 { 0x174, MUXMODE(4) | INPUTENABLE }, /* gpio_144 */ 1119 { 0x176, MUXMODE(4) | INPUTENABLE }, /* gpio_145 */ 1120 { 0x178, MUXMODE(4) | INPUTENABLE }, /* gpio_146 */ 1121 { 0x17a, MUXMODE(4) | INPUTENABLE }, /* gpio_147 */ 1122 { 0x19a, MUXMODE(4) | INPUTENABLE }, /* gpio_163 */ 1123 { -1 } 1124 }; 1125 static const struct omap_mux_conf overo_mux_uart1_conf[] = { 1126 { 0x17c, MUXMODE(0) }, /* uart1_tx */ 1127 { 0x182, MUXMODE(0) | INPUTENABLE }, /* uart1_rx */ 1128 { -1 } 1129 }; 1130 static const struct omap_mux_conf overo_mux_no_uart1_conf[] = { 1131 { 0x17c, MUXMODE(4) | INPUTENABLE }, /* gpio_148 */ 1132 { 0x182, MUXMODE(4) | INPUTENABLE }, /* gpio_151 */ 1133 { -1 } 1134 }; 1135 static const struct omap_mux_conf overo_mux_hdq_conf[] = { 1136 #if 0 1137 { 0x1c4, MUXMODE(0) | ??? | INPUTENABLE }, /* hdq_sio */ 1138 #endif 1139 { -1 } 1140 }; 1141 static const struct omap_mux_conf overo_mux_no_hdq_conf[] = { 1142 { 0x1c4, MUXMODE(4) | INPUTENABLE }, /* gpio_170 */ 1143 { -1 } 1144 }; 1145 1146 gxio_omap_mux_config(overo_mux_40pin_header_conf); 1147 if (uart1 == force_uart1) 1148 gxio_omap_mux_config(overo_mux_uart1_conf); 1149 else 1150 gxio_omap_mux_config_address("com", 0x4806a000, 1151 overo_mux_uart1_conf, overo_mux_no_uart1_conf); 1152 gxio_omap_mux_config_address("hdq", 0x480b2000, 1153 overo_mux_hdq_conf, overo_mux_no_hdq_conf); 1154 } 1155 1156 static void 1157 chestnut_config(void) 1158 { 1159 static const struct omap_mux_conf chestnut_mux_conf[] = { 1160 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1161 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1162 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1163 { -1 } 1164 }; 1165 1166 eth0_config(); 1167 lcd_config('R'); 1168 1169 header_40pin_config(uart1_if_exists); 1170 gxio_omap_mux_config(chestnut_mux_conf); 1171 } 1172 1173 static void 1174 gallop_config(void) 1175 { 1176 static const struct omap_mux_conf gallop43_mux_conf[] = { 1177 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1178 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1179 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1180 { -1 } 1181 }; 1182 1183 lcd_config('R'); 1184 1185 header_40pin_config(force_uart1); 1186 gxio_omap_mux_config(gallop43_mux_conf); 1187 } 1188 1189 static void 1190 summit_config(void) 1191 { 1192 1193 dvi_config(); 1194 1195 header_40pin_config(uart1_if_exists); 1196 } 1197 1198 static void 1199 tobi_config(void) 1200 { 1201 1202 eth0_config(); 1203 dvi_config(); 1204 1205 header_40pin_config(uart1_if_exists); 1206 } 1207 1208 static void 1209 tobiduo_config(void) 1210 { 1211 1212 eth0_config(); 1213 eth1_config(); 1214 } 1215 1216 #elif defined(DUOVERO) 1217 1218 static void 1219 ehci_config(void) 1220 { 1221 uint32_t val; 1222 1223 #define SCRM_ALTCLKSRC 0xa110 1224 #define ALTCLKSRC_ENABLE_EXT (1 << 3) 1225 #define ALTCLKSRC_ENABLE_INT (1 << 2) 1226 #define ALTCLKSRC_MODE_MASK (3 << 0) 1227 #define ALTCLKSRC_MODE_POWERDOWN (0 << 0) 1228 #define ALTCLKSRC_MODE_ACTIVE (1 << 0) 1229 #define ALTCLKSRC_MODE_BYPASS (2 << 0) 1230 #define SCRM_AUXCLK3 0xa31c 1231 #define AUXCLK3_CLKDIV(n) (((n) - 1) << 16) 1232 #define AUXCLK3_CLKDIV_MASK (0xf << 16) 1233 #define AUXCLK3_ENABLE (1 << 8) 1234 #define AUXCLK3_SRCSELECT_MASK (3 << 1) 1235 #define AUXCLK3_SRCSELECT_SYSCLK (0 << 1) 1236 #define AUXCLK3_SRCSELECT_CORE (1 << 1) 1237 #define AUXCLK3_SRCSELECT_PERDPLL (2 << 1) 1238 #define AUXCLK3_SRCSELECT_ALTCLK (3 << 1) 1239 #define AUXCLK3_POLARITY_LOW (0 << 0) 1240 #define AUXCLK3_POLARITY_HIGH (1 << 0) 1241 1242 /* Use the 1/2 auxiliary clock #3 of system clock. */ 1243 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3); 1244 val &= ~(AUXCLK3_CLKDIV_MASK | AUXCLK3_SRCSELECT_MASK); 1245 val |= (AUXCLK3_CLKDIV(2) | AUXCLK3_ENABLE | AUXCLK3_SRCSELECT_SYSCLK); 1246 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3, val); 1247 1248 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC); 1249 val &= ~ALTCLKSRC_MODE_MASK; 1250 val |= ALTCLKSRC_MODE_ACTIVE; 1251 val |= (ALTCLKSRC_ENABLE_EXT | ALTCLKSRC_ENABLE_INT); 1252 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC, val); 1253 } 1254 1255 static void 1256 parlor_config(void) 1257 { 1258 #if 0 1259 static const struct omap_mux_conf parlor_mux_40pin_header_conf[] = { 1260 /* 1261 * 1: GND 1262 * 2: GND 1263 * 3: MCSPI1_CLK or GPIO 134 1264 * 4: MCSPI1_CS0 or GPIO 137 1265 * 5: MCSPI1_SIMO or GPIO 136 1266 * 6: MCSPI1_CS1 or GPIO 138 1267 * 7: MCSPI1_SOMI or GPIO 135 1268 * 8: MCSPI1_CS2 or GPIO 139 1269 * 9: HDQ_SIO or GPIO 127 1270 * 10: MCSPI1_CS3 or GPIO 140 1271 * 11: SDMMC3_CMD or GPIO ??? 1272 * 12: I2C2_SCL or GPIO 128 1273 * 13: SDMMC3_CLK or GPIO ??? 1274 * 14: I2C2_SDA or GPIO 129 1275 * 15: UART2_TX or SDMMC3_DAT1 or GPIO 126 1276 * 16: PMIC_PWM2 (TWL6030) 1277 * 17: UART2_RX or SDMMC3_DAT0 or GPIO 125 1278 * 18: PMIC_PWM1 (TWL6030) 1279 * 19: BSP2_CLKX or GPIO 110 1280 * 20: BSP2_FSX or GPIO 113 1281 * 21: BSP2_DX or GPIO 112 1282 * 22: BSP2_DR or GPIO 111 1283 * 23: BSP2_CLKS or GPIO 118 1284 * 24: FREF1 1285 * 25: MCSPI4_SOMI or GPIO 153 1286 * 26: PMIC_NRESWARN 1287 * 27: MCSPI4_SIMO or GPIO 152 1288 * 28: SYSEN 1289 * 29: MCSPI4_CLK or GPIO 151 1290 * 30: PWRON 1291 * 31: MCSPI4_CS0 or GPIO 154 1292 * 32: REGEN1 1293 * 33: ADCIN3 (TWL6030) 1294 * 34: VCC_1.0 1295 * 35: ADCIN4_VREF (TWL6030) 1296 * 36: VDD_VAUX2 1297 * 37: ADCIN4 (TWL6030) 1298 * 38: VCC_3.3 1299 * 39: ADCIN5 (TWL6030) 1300 * 40: V_BATT_5 1301 */ 1302 { -1 } 1303 }; 1304 #endif 1305 static const struct omap_mux_conf parlor_mux_mcspi1_conf[] = { 1306 #if 0 1307 { 0x132, /* 3: MCSPI1_CLK */ 1308 MUXMODE(0) | ??? }, 1309 { 0x138, /* 4: MCSPI1_CS0 */ 1310 MUXMODE(0) | ??? }, 1311 { 0x136, /* 5: MCSPI1_SIMO */ 1312 MUXMODE(0) | ??? }, 1313 { 0x13a, /* 6: MCSPI1_CS1 */ 1314 MUXMODE(0) | ??? }, 1315 { 0x134, /* 7: MCSPI1_SOMI */ 1316 MUXMODE(0) | ??? | INPUTENABLE }, 1317 { 0x13c, /* 8: MCSPI1_CS2 */ 1318 MUXMODE(0) | ??? }, 1319 { 0x13e, /* 10: MCSPI1_CS3 */ 1320 MUXMODE(0) | ??? }, 1321 #endif 1322 { -1 } 1323 }; 1324 static const struct omap_mux_conf parlor_mux_no_mcspi1_conf[] = { 1325 { 0x132, /* 3: GPIO 134 */ 1326 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1327 { 0x138, /* 4: GPIO 137 */ 1328 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1329 { 0x136, /* 5: GPIO 136 */ 1330 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1331 { 0x13a, /* 6: GPIO 138 */ 1332 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1333 { 0x134, /* 7: GPIO 135 */ 1334 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1335 { 0x13c, /* 8: GPIO 139 */ 1336 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1337 { 0x13e, /* 10: GPIO 140 */ 1338 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1339 { -1 } 1340 }; 1341 static const struct omap_mux_conf parlor_mux_hdq_conf[] = { 1342 #if 0 1343 { 0x120, /* 9: HDQ_SIO */ 1344 MUXMODE(0) | ??? | INPUTENABLE }, 1345 #endif 1346 { -1 } 1347 }; 1348 static const struct omap_mux_conf parlor_mux_no_hdq_conf[] = { 1349 { 0x120, /* 9: GPIO_127 */ 1350 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1351 { -1 } 1352 }; 1353 static const struct omap_mux_conf parlor_mux_i2c2_conf[] = { 1354 { 0x126, /* 12: I2C2_SCL */ 1355 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1356 { 0x128, /* 14: I2C2_SDA */ 1357 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1358 { -1 } 1359 }; 1360 static const struct omap_mux_conf parlor_mux_no_i2c2_conf[] = { 1361 { 0x126, /* 12: GPIO 128 */ 1362 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1363 { 0x128, /* 14: GPIO 129 */ 1364 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1365 { -1 } 1366 }; 1367 static const struct omap_mux_conf parlor_mux_sdmmc3_conf[] = { 1368 #if 0 1369 11 SDMMC3_CMD DuoVero J2 A15 <- omap pin AG10 1370 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1371 13 SDMMC3_CLK DuoVero J2 A16 <- omap pin AE9 1372 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1373 #endif 1374 { 0x11c, /* 17: SDMMC3_DAT0 */ 1375 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1376 { 0x11e, /* 15: SDMMC3_DAT1 */ 1377 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1378 { -1 } 1379 }; 1380 static const struct omap_mux_conf parlor_mux_uart2_conf[] = { 1381 { 0x11c, /* 17: UART2_RX */ 1382 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1383 { 0x11e, 1384 MUXMODE(0) | PULLUDENABLE }, /* 15: UART2_TX */ 1385 { -1 } 1386 }; 1387 static const struct omap_mux_conf parlor_mux_no_uart2_conf[] = { 1388 { 0x11c, /* 17: GPIO 125 */ 1389 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1390 { 0x11e, /* 15: GPIO 126 */ 1391 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1392 { -1 } 1393 }; 1394 static const struct omap_mux_conf parlor_mux_bsp2_conf[] = { 1395 { 0x0f6, /* 19: BSP2_CLKX */ 1396 MUXMODE(0) | INPUTENABLE }, 1397 { 0x0fc, /* 20: BSP2_FSX */ 1398 MUXMODE(0) | INPUTENABLE }, 1399 { 0x0fa, /* 21: BSP2_DX */ 1400 MUXMODE(0) | PULLUDENABLE }, 1401 { 0x0f8, /* 22: BSP2_DR */ 1402 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1403 { 0x10e, /* 23: BSP2_CLKS */ 1404 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1405 { -1 } 1406 }; 1407 static const struct omap_mux_conf parlor_mux_no_bsp2_conf[] = { 1408 { 0x0f6, /* 19: GPIO 110 */ 1409 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1410 { 0x0fc, /* 20: GPIO 113 */ 1411 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1412 { 0x0fa, /* 21: GPIO 112 */ 1413 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1414 { 0x0f8, /* 22: GPIO 111 */ 1415 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1416 { 0x10e, /* 23: GPIO 118 */ 1417 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1418 { -1 } 1419 }; 1420 static const struct omap_mux_conf parlor_mux_mcspi4_conf[] = { 1421 #if 0 1422 { 0x158, /* 25: MCSPI4_SOMI */ 1423 MUXMODE(0) | ??? | INPUTENABLE }, 1424 { 0x156, /* 27: MCSPI4_SIMO */ 1425 MUXMODE(0) | ??? }, 1426 { 0x154, /* 29: MCSPI4_CLK */ 1427 MUXMODE(0) | ??? }, 1428 { 0x15a, /* 31: MCSPI4_CS0 */ 1429 MUXMODE(0) | ??? }, 1430 #endif 1431 { -1 } 1432 }; 1433 static const struct omap_mux_conf parlor_mux_no_mcspi4_conf[] = { 1434 { 0x158, /* 25: GPIO 153 */ 1435 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1436 { 0x156, /* 27: GPIO 152 */ 1437 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1438 { 0x154, /* 29: GPIO 151 */ 1439 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1440 { 0x15a, /* 31: GPIO 154 */ 1441 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1442 { -1 } 1443 }; 1444 1445 /* 1446 * ETH0 connects via CS5. It use GPIO 44 for IRQ. 1447 * Also GPIO 45 is NRESET. 1448 */ 1449 smsh_config(NULL, 44, 45); 1450 1451 ehci_config(); 1452 1453 gxio_omap_mux_config_address("mcspi", 0x48098000, 1454 parlor_mux_mcspi1_conf, parlor_mux_no_mcspi1_conf); 1455 gxio_omap_mux_config_address("hdq", 0x480b2000, 1456 parlor_mux_hdq_conf, parlor_mux_no_hdq_conf); 1457 gxio_omap_mux_config_address("tiiic", 0x48072000, 1458 parlor_mux_i2c2_conf, parlor_mux_no_i2c2_conf); 1459 if (gxio_omap_mux_config_address("sdhc", 0x480ad000, 1460 parlor_mux_sdmmc3_conf, NULL) != 0) 1461 gxio_omap_mux_config_address("com", 0x4806c000, 1462 parlor_mux_uart2_conf, parlor_mux_no_uart2_conf); 1463 gxio_omap_mux_config_address("mcbsp", 0x49024000, 1464 parlor_mux_bsp2_conf, parlor_mux_no_bsp2_conf); 1465 gxio_omap_mux_config_address("mcspi", 0x480ba000, 1466 parlor_mux_mcspi4_conf, parlor_mux_no_mcspi4_conf); 1467 } 1468 1469 #elif defined(PEPPER) 1470 1471 static void 1472 lcd_config(void) 1473 { 1474 static const struct tifb_panel_info panel_lcd = { 1475 .panel_tft = 1, 1476 .panel_mono = false, 1477 .panel_bpp = 24, 1478 1479 .panel_pxl_clk = 18400000, 1480 .panel_width = 480, 1481 .panel_height = 272, 1482 .panel_hfp = 8, 1483 .panel_hbp = 4, 1484 .panel_hsw = 41, 1485 .panel_vfp = 4, 1486 .panel_vbp = 2, 1487 .panel_vsw = 10, 1488 .panel_invert_hsync = 0, 1489 .panel_invert_vsync = 0, 1490 1491 .panel_ac_bias = 255, 1492 .panel_ac_bias_intrpt = 0, 1493 .panel_dma_burst_sz = 16, 1494 .panel_fdd = 0x80, 1495 .panel_sync_edge = 0, 1496 .panel_sync_ctrl = 1, 1497 .panel_tft_alt_mode = 0, 1498 .panel_invert_pxl_clk = 0, 1499 }; 1500 static const struct omap_mux_conf pepper_mux_lcd_conf[] = { 1501 /* 1502 * LCD_DATA[0-23] configures in tifb.c 1503 */ 1504 1505 { 0x8e0, MMODE(0) | PUDEN }, /* LCD_VSYNC */ 1506 { 0x8e4, MMODE(0) | PUDEN }, /* LCD_HSYNC */ 1507 { 0x8e8, MMODE(0) | PUDEN }, /* LCD_PCLK */ 1508 { 0x8ec, MMODE(0) | PUDEN }, /* LCD_AC_BIAS_EN */ 1509 1510 { 0x86c, MMODE(7) | PUTYPESEL }, /* GPIO 59: Enable */ 1511 { -1 } 1512 }; 1513 1514 if (gxio_omap_mux_config_address("tifb", 0x4830e000, 1515 pepper_mux_lcd_conf, NULL) == 0) { 1516 extern const struct tifb_panel_info *tifb_panel_info; 1517 extern bool use_tps65217_wled; 1518 1519 tifb_panel_info = &panel_lcd; 1520 use_tps65217_wled = true; 1521 } 1522 } 1523 1524 static void 1525 pepper43_config(void) 1526 { 1527 static const struct omap_mux_conf pepper43_mux_wilink8_conf[] = { 1528 /* TI WiLink 8 */ 1529 { 0x800, MMODE(7) | PUTYPESEL }, /* GPIO 32: Bluetooth */ 1530 { 0x804, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 33: irq */ 1531 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: WiFi */ 1532 { -1 } 1533 }; 1534 static const struct omap_mux_conf pepper43_mux_i2c1_conf[] = { 1535 { 0x968, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1536 { 0x96c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1537 { -1 } 1538 }; 1539 static const struct omap_mux_conf pepper43_mpu9150_conf[] = { 1540 /* MPU9150 at I2C1 */ 1541 { 0x808, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 34: IRQ */ 1542 { 0x898, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 68 */ 1543 { 0x870, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 30 */ 1544 { -1 } 1545 }; 1546 static const struct omap_mux_conf pepper43_mux_20pin_header_conf[] = { 1547 { 0x85c, MMODE(7) | PUDEN | RXACTIVE }, /* 1: GPIO 55 */ 1548 { 0x80c, MMODE(7) | PUDEN | RXACTIVE }, /* 2: GPIO 35 */ 1549 { 0x810, MMODE(7) | PUDEN | RXACTIVE }, /* 3: GPIO 36 */ 1550 { 0x814, MMODE(7) | PUDEN | RXACTIVE }, /* 4: GPIO 37 */ 1551 { 0x818, MMODE(7) | PUDEN | RXACTIVE }, /* 5: GPIO 38 */ 1552 { 0x81c, MMODE(7) | PUDEN | RXACTIVE }, /* 6: GPIO 39 */ 1553 { 0x87c, MMODE(7) | PUDEN | RXACTIVE }, /* 7: GPIO 61 */ 1554 { 0x880, MMODE(7) | PUDEN | RXACTIVE }, /* 8: GPIO 62 */ 1555 { 0x884, MMODE(7) | PUDEN | RXACTIVE }, /* 9: GPIO 63 */ 1556 { 0x9e4, MMODE(7) | PUDEN | RXACTIVE }, /* 10: GPIO 103 */ 1557 { 0x9e8, MMODE(7) | PUDEN | RXACTIVE }, /* 11: GPIO 104 */ 1558 { 0x9b0, MMODE(7) | PUDEN | RXACTIVE }, /* 12: GPIO 19 */ 1559 #if 0 /* UART3 or GPIO */ 1560 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* 13: GPIO 7 */ 1561 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* 14: GPIO 6 */ 1562 #endif 1563 #if 0 /* UART2 or GPIO */ 1564 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* 15: GPIO 98 */ 1565 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* 16: GPIO 97 */ 1566 #endif 1567 /* 17: VCC 5v */ 1568 /* 18: VCC 3.3v */ 1569 /* 19: GND */ 1570 /* 20: GND */ 1571 { -1 } 1572 }; 1573 static const struct omap_mux_conf pepper43_mux_uart2_conf[] = { 1574 { 0x90c, MMODE(6) | PUTYPESEL | RXACTIVE }, /* UART2_RXD */ 1575 { 0x910, MMODE(6) | PUDEN }, /* UART2_TXD */ 1576 { -1 } 1577 }; 1578 static const struct omap_mux_conf pepper43_mux_no_uart2_conf[] = { 1579 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 97 */ 1580 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 98 */ 1581 { -1 } 1582 }; 1583 static const struct omap_mux_conf pepper43_mux_uart3_conf[] = { 1584 { 0x960, MMODE(1) | PUTYPESEL | RXACTIVE }, /* UART3_RXD */ 1585 { 0x964, MMODE(1) | PUDEN }, /* UART3_TXD */ 1586 { -1 } 1587 }; 1588 static const struct omap_mux_conf pepper43_mux_no_uart3_conf[] = { 1589 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 6 */ 1590 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 7 */ 1591 { -1 } 1592 }; 1593 1594 static const struct omap_mux_conf *pepper43_mux_conf[] = { 1595 pepper43_mux_wilink8_conf, 1596 pepper43_mux_i2c1_conf, 1597 pepper43_mpu9150_conf, 1598 pepper43_mux_20pin_header_conf, 1599 }; 1600 1601 static const struct omap_gpio_conf pepper43_gpio_wl18xx_conf[] = { 1602 { 32, conf_output_0 }, /* #Reset: Bluetooth */ 1603 { 56, conf_output_0 }, /* #Reset: WiFi */ 1604 { -1 } 1605 }; 1606 int i; 1607 1608 lcd_config(); 1609 1610 for (i = 0; i < __arraycount(pepper43_mux_conf); i++) 1611 gxio_omap_mux_config(pepper43_mux_conf[i]); 1612 gxio_omap_gpio_config(pepper43_gpio_wl18xx_conf); 1613 1614 #if 0 1615 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 52 (Blue) */ 1616 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 20)); 1617 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1618 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 20)); 1619 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 53 (Red) */ 1620 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 21)); 1621 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1622 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 21)); 1623 #endif 1624 1625 gxio_omap_mux_config_address("com", 0x48024000, 1626 pepper43_mux_uart2_conf, pepper43_mux_no_uart2_conf); 1627 gxio_omap_mux_config_address("com", 0x481a6000, 1628 pepper43_mux_uart3_conf, pepper43_mux_no_uart3_conf); 1629 } 1630 1631 static void 1632 pepper_config(void) 1633 { 1634 static const struct omap_mux_conf pepper_mux_button2_conf[] = { 1635 { 0x85c, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 55 */ 1636 { -1 } 1637 }; 1638 static const struct omap_mux_conf pepper_mux_i2c1_conf[] = { 1639 { 0x90c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1640 { 0x910, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1641 { -1 } 1642 }; 1643 static const struct omap_mux_conf pepper_mux_wi2wi_conf[] = { 1644 { 0x9b4, MMODE(3) | PUDEN }, /* CLKOUT2 */ 1645 /* Wi2Wi */ 1646 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: nReset */ 1647 { 0x870, MMODE(7) | PUTYPESEL }, /* GPIO 30: nPower */ 1648 { -1 } 1649 }; 1650 static const struct omap_mux_conf pepper_mux_uart1_conf[] = { 1651 { 0x978, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_CTSn */ 1652 { 0x97c, MMODE(0) }, /* UART1_RTSn */ 1653 { 0x980, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_RXD */ 1654 { 0x984, MMODE(0) }, /* UART1_TXD */ 1655 { -1 } 1656 }; 1657 static const struct omap_mux_conf pepper_mux_no_uart1_conf[] = { 1658 { 0x978, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 12 */ 1659 { 0x97c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 13 */ 1660 { 0x980, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 14 */ 1661 { 0x984, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 15 */ 1662 { -1 } 1663 }; 1664 static const struct omap_mux_conf *pepper_mux_conf[] = { 1665 pepper_mux_button2_conf, 1666 pepper_mux_i2c1_conf, 1667 pepper_mux_wi2wi_conf, 1668 }; 1669 1670 int i; 1671 1672 lcd_config(); 1673 1674 for (i = 0; i < __arraycount(pepper_mux_conf); i++) 1675 gxio_omap_mux_config(pepper_mux_conf[i]); 1676 gxio_omap_mux_config_address("com", 0x48022000, 1677 pepper_mux_uart1_conf, pepper_mux_no_uart1_conf); 1678 } 1679 1680 static void 1681 c_config(void) 1682 { 1683 static const struct omap_mux_conf pepper43c_mux_ft5306_conf[] = { 1684 /* FT5306 at I2C2 */ 1685 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20 */ 1686 { 0x95c, MMODE(7) | PUDEN }, /* GPIO 5 */ 1687 { -1 } 1688 }; 1689 static const struct omap_mux_conf pepper43c_mux_i2c2_conf[] = { 1690 { 0x950, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SDA */ 1691 { 0x954, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SCL */ 1692 { -1 } 1693 }; 1694 static const struct omap_mux_conf *pepper43c_mux_conf[] = { 1695 pepper43c_mux_ft5306_conf, 1696 pepper43c_mux_i2c2_conf, 1697 }; 1698 1699 static const struct omap_gpio_conf pepper43c_gpio_ft5306_conf[] = { 1700 { 5, conf_output_0 }, /* #Reset */ 1701 { -1 } 1702 }; 1703 int i; 1704 1705 pepper43_config(); 1706 1707 for (i = 0; i < __arraycount(pepper43c_mux_conf); i++) 1708 gxio_omap_mux_config(pepper43c_mux_conf[i]); 1709 gxio_omap_gpio_config(pepper43c_gpio_ft5306_conf); 1710 } 1711 1712 static void 1713 dvi_config(void) 1714 { 1715 /* XXXX: hmm... mismatch found in Linux's dts and pubs.gumstix.org... */ 1716 1717 extern struct cfdata cfdata[]; 1718 extern const struct tifb_panel_info *tifb_panel_info; 1719 1720 static const struct tifb_panel_info panel_dvi = { 1721 .panel_tft = 1, 1722 .panel_mono = false, 1723 .panel_bpp = 16, 1724 1725 .panel_pxl_clk = 63500000, 1726 .panel_width = 1024, 1727 .panel_height = 768, 1728 .panel_hfp = 8, 1729 .panel_hbp = 4, 1730 .panel_hsw = 41, 1731 .panel_vfp = 4, 1732 .panel_vbp = 2, 1733 .panel_vsw = 10, 1734 .panel_invert_hsync = 0, 1735 .panel_invert_vsync = 0, 1736 1737 .panel_ac_bias = 255, 1738 .panel_ac_bias_intrpt = 0, 1739 .panel_dma_burst_sz = 16, 1740 .panel_fdd = 0x80, 1741 .panel_sync_edge = 0, 1742 .panel_sync_ctrl = 1, 1743 .panel_invert_pxl_clk = 0, 1744 }; 1745 cfdata_t cf = &cfdata[0]; 1746 1747 /* Disable wireless module. */ 1748 while (cf->cf_name != NULL) { 1749 if (strcmp(cf->cf_name, "sdhc") == 0 && 1750 strcmp(cf->cf_atname, "mainbus") == 0 && 1751 cf->cf_loc[MAINBUSCF_BASE] == 0x47810000) { 1752 if (cf->cf_fstate == FSTATE_NOTFOUND) 1753 cf->cf_fstate = FSTATE_DNOTFOUND; 1754 else if (cf->cf_fstate == FSTATE_STAR) 1755 cf->cf_fstate = FSTATE_DSTAR; 1756 } 1757 cf++; 1758 } 1759 1760 tifb_panel_info = &panel_dvi; 1761 } 1762 1763 static void 1764 r_config(void) 1765 { 1766 static const struct omap_mux_conf pepper43r_mux_ads7846_conf[] = { 1767 /* ADS7846 at McSPI0 */ 1768 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20: IRQ */ 1769 { -1 } 1770 }; 1771 static const struct omap_mux_conf pepper43r_mux_spi0_conf[] = { 1772 { 0x950, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_SCLK */ 1773 { 0x954, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D0 */ 1774 { 0x958, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D1 */ 1775 { 0x95c, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_CS0 */ 1776 { -1 } 1777 }; 1778 static const struct omap_mux_conf *pepper43r_mux_conf[] = { 1779 pepper43r_mux_ads7846_conf, 1780 pepper43r_mux_spi0_conf, 1781 }; 1782 int i; 1783 1784 pepper43_config(); 1785 1786 for (i = 0; i < __arraycount(pepper43r_mux_conf); i++) 1787 gxio_omap_mux_config(pepper43r_mux_conf[i]); 1788 } 1789 1790 #endif 1791 1792 #if defined(OVERO) || defined(DUOVERO) 1793 static void 1794 smsh_config(struct omap_mux_conf *smsh_mux_conf, int intr, int nreset) 1795 { 1796 struct omap_gpio_conf smsh_gpio_conf[] = { 1797 { intr, conf_input }, 1798 { nreset, conf_output_0 }, 1799 { -1 } 1800 }; 1801 1802 /* 1803 * Basically use current settings by U-Boot. 1804 * However remap physical address to configured address. 1805 */ 1806 1807 if (smsh_mux_conf != NULL) 1808 gxio_omap_mux_config(smsh_mux_conf); 1809 gxio_omap_gpio_config(smsh_gpio_conf); 1810 __udelay(100000); 1811 gxio_omap_gpio_write(nreset, 1); 1812 } 1813 #endif 1814 1815 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1816 /* 1817 * The delay for configuration time. 1818 * This function use initialized timer by U-Boot. 1819 */ 1820 static void 1821 __udelay(unsigned int usec) 1822 { 1823 #if defined(OVERO) || defined(DUOVERO) 1824 #define V_SCLK (26000000 >> 1) 1825 #define TCRR 0x28 1826 #elif defined(PEPPER) 1827 #define V_SCLK 24000000 1828 #define TCRR 0x3c 1829 #endif 1830 #define SYS_PTV 2 1831 #define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV)) 1832 1833 const vaddr_t timer_base = 1834 #if defined(OVERO) 1835 OVERO_L4_PERIPHERAL_VBASE + 0x32000; 1836 #elif defined(DUOVERO) 1837 DUOVERO_L4_PERIPHERAL_VBASE + 0x32000; 1838 #elif defined(PEPPER) 1839 PEPPER_L4_PERIPHERAL_VBASE + 0x40000; 1840 #endif 1841 long timo = usec * (TIMER_CLOCK / 1000) / 1000; 1842 uint32_t now, last; 1843 1844 last = ioreg_read(timer_base + TCRR); 1845 while (timo > 0) { 1846 now = ioreg_read(timer_base + TCRR); 1847 if (last > now) 1848 timo -= __BITS(0, 31) - last + now + 1; 1849 else 1850 timo -= now - last; 1851 last = now; 1852 } 1853 } 1854 #endif 1855 1856 #if defined(PEPPER) 1857 static int 1858 read_i2c_device(const vaddr_t i2c_base, uint16_t sa, uint8_t addr, int len, 1859 uint8_t *buf) 1860 { 1861 uint16_t v; 1862 int aok = 0, cnt = 0; 1863 1864 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1865 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1866 while (v & I2C_IRQSTATUS_BB) { 1867 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, v); 1868 __udelay(20); 1869 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1870 } 1871 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1872 1873 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1874 ioreg16_write(i2c_base + OMAP2_I2C_CNT, sizeof(addr)); 1875 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1876 I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STP | I2C_CON_STT); 1877 while (1 /*CONSTCOND*/) { 1878 __udelay(20); 1879 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1880 if ((v & I2C_IRQSTATUS_XRDY) && aok == 0) { 1881 aok = 1; 1882 ioreg16_write(i2c_base + OMAP2_I2C_DATA, addr); 1883 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1884 I2C_IRQSTATUS_XRDY); 1885 } 1886 if (v & I2C_IRQSTATUS_ARDY) { 1887 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1888 I2C_IRQSTATUS_ARDY); 1889 break; 1890 } 1891 } 1892 1893 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1894 ioreg16_write(i2c_base + OMAP2_I2C_CNT, len); 1895 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1896 I2C_CON_EN | I2C_CON_MST | I2C_CON_STP | I2C_CON_STT); 1897 while (1 /*CONSTCOND*/) { 1898 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1899 if (v & I2C_IRQSTATUS_RRDY && 1900 cnt < len) { 1901 buf[cnt++] = ioreg16_read(i2c_base + OMAP2_I2C_DATA); 1902 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1903 I2C_IRQSTATUS_RRDY); 1904 } 1905 if (v & I2C_IRQSTATUS_ARDY) { 1906 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1907 I2C_IRQSTATUS_ARDY); 1908 break; 1909 } 1910 } 1911 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1912 return 0; 1913 } 1914 #endif 1915
Indexes created Tue Sep 30 20:09:53 GMT 2025