gxio.c revision 1.25.12.1
1 /* $NetBSD: gxio.c,v 1.25.12.1 2018/03/15 09:12:02 pgoyette Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: gxio.c,v 1.25.12.1 2018/03/15 09:12:02 pgoyette Exp $"); 35 36 #include "opt_cputypes.h" 37 #include "opt_gumstix.h" 38 #include "opt_gxio.h" 39 #if defined(OVERO) 40 #include "opt_omap.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/device.h> 45 #include <sys/errno.h> 46 #include <sys/kernel.h> 47 48 #include <sys/systm.h> 49 50 #include <machine/bootconfig.h> 51 52 #include <arm/omap/omap2_gpmcreg.h> 53 #if defined(OMAP2) 54 #include <arm/omap/omap2_reg.h> 55 #if defined(OMAP3530) 56 #include <arm/omap/omap2_intr.h> 57 #endif 58 #endif 59 #include <arm/omap/omap_var.h> 60 #include <arm/omap/ti_iicreg.h> 61 #include <arm/omap/tifbvar.h> 62 #if defined(CPU_XSCALE) 63 #include <arm/xscale/pxa2x0cpu.h> 64 #endif 65 #include <arm/xscale/pxa2x0reg.h> 66 #include <arm/xscale/pxa2x0var.h> 67 #include <arm/xscale/pxa2x0_gpio.h> 68 #include <evbarm/gumstix/gumstixreg.h> 69 #include <evbarm/gumstix/gumstixvar.h> 70 71 #include "ioconf.h" 72 #include "locators.h" 73 74 75 struct gxioconf { 76 const char *name; 77 void (*config)(void); 78 }; 79 80 #if defined(GUMSTIX) 81 static int gxiomatch(device_t, cfdata_t, void *); 82 static void gxioattach(device_t, device_t, void *); 83 static int gxiosearch(device_t, cfdata_t, const int *, void *); 84 static int gxioprint(void *, const char *); 85 86 CFATTACH_DECL_NEW(gxio, sizeof(struct gxio_softc), 87 gxiomatch, gxioattach, NULL, NULL); 88 #endif 89 90 void gxio_config(void); 91 void gxio_config_expansion(const char *); 92 #if defined(GUMSTIX) 93 static void basix_config(void); 94 static void cfstix_config(void); 95 static void etherstix_config(void); 96 static void netcf_config(void); 97 static void netcf_vx_config(void); 98 static void netduommc_config(void); 99 static void netduo_config(void); 100 static void netmicrosd_config(void); 101 static void netwifimicrosd_config(void); 102 static void netmmc_config(void); 103 static void wifistix_config(void); 104 static void wifistix_cf_config(void); 105 #elif defined(OVERO) 106 static void eth0_config(void); 107 static void eth1_config(void); 108 static void dvi_config(void); 109 static void lcd_config(char); 110 static void header_40pin_config(int); 111 112 static void chestnut_config(void); 113 static void gallop_config(void); 114 static void summit_config(void); 115 static void tobi_config(void); 116 static void tobiduo_config(void); 117 #elif defined(DUOVERO) 118 static void ehci_config(void); 119 120 static void parlor_config(void); 121 #elif defined(PEPPER) 122 static void lcd_config(void); 123 static void pepper43_config(void); 124 125 static void pepper_config(void); 126 static void c_config(void); 127 static void dvi_config(void); 128 static void r_config(void); 129 #endif 130 #if defined(OVERO) || defined(DUOVERO) 131 struct omap_mux_conf; 132 static void smsh_config(struct omap_mux_conf *, int, int); 133 #endif 134 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 135 static void __udelay(unsigned int); 136 #endif 137 #if defined(PEPPER) 138 static int read_i2c_device(const vaddr_t, uint16_t, uint8_t, int, uint8_t *); 139 #endif 140 141 #if defined(CPU_XSCALE_PXA250) 142 143 static struct pxa2x0_gpioconf pxa255dep_gpioconf[] = { 144 /* Bluetooth module configuration */ 145 { 7, GPIO_OUT | GPIO_SET }, /* power on */ 146 { 12, GPIO_ALT_FN_1_OUT }, /* 32kHz out. required by SingleStone */ 147 148 /* AC97 configuration */ 149 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 150 151 /* FFUART configuration */ 152 { 35, GPIO_ALT_FN_1_IN }, /* CTS */ 153 { 41, GPIO_ALT_FN_2_OUT }, /* RTS */ 154 155 #ifndef GXIO_BLUETOOTH_ON_HWUART 156 /* BTUART configuration */ 157 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 158 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 159 #else 160 /* HWUART configuration */ 161 { 42, GPIO_ALT_FN_3_IN }, /* HWRXD */ 162 { 43, GPIO_ALT_FN_3_OUT }, /* HWTXD */ 163 { 44, GPIO_ALT_FN_3_IN }, /* HWCTS */ 164 { 45, GPIO_ALT_FN_3_OUT }, /* HWRTS */ 165 #endif 166 167 #ifndef GXIO_BLUETOOTH_ON_HWUART 168 /* HWUART configuration */ 169 { 48, GPIO_ALT_FN_1_OUT }, /* HWTXD */ 170 { 49, GPIO_ALT_FN_1_IN }, /* HWRXD */ 171 { 50, GPIO_ALT_FN_1_IN }, /* HWCTS */ 172 { 51, GPIO_ALT_FN_1_OUT }, /* HWRTS */ 173 #endif 174 175 { -1 } 176 }; 177 #endif 178 #if defined(CPU_XSCALE_PXA270) 179 static struct pxa2x0_gpioconf verdexdep_gpioconf[] = { 180 /* Bluetooth module configuration */ 181 { 9, GPIO_ALT_FN_3_OUT }, /* CHOUT<0> */ 182 { 12, GPIO_OUT | GPIO_SET }, 183 184 /* LCD configuration */ 185 { 17, GPIO_IN }, /* backlight on */ 186 187 /* FFUART configuration */ 188 { 34, GPIO_ALT_FN_1_IN }, /* FFRXD */ 189 { 39, GPIO_ALT_FN_2_OUT }, /* FFTXD */ 190 191 /* BTUART configuration */ 192 { 42, GPIO_ALT_FN_1_IN }, /* BTRXD */ 193 { 43, GPIO_ALT_FN_2_OUT }, /* BTTXD */ 194 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 195 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 196 197 /* AC97 configuration */ 198 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 199 200 { -1 } 201 }; 202 203 #elif defined(OMAP2) 204 205 struct omap_mux_conf { 206 int offset; 207 uint32_t value; 208 /* OMAP3/4 register values */ 209 #define WAKEUPEVENT (1 << 15) 210 #define WAKEUPENABLE (1 << 14) 211 #define OFFMODEPULLTYPESELECT (1 << 13) 212 #define OFFMODEPULLUDENABLE (1 << 12) 213 #define OFFMODEOUTVALUE (1 << 11) 214 #define OFFMODEOUTENABLE (1 << 10) 215 #define OFFMODEENABLE (1 << 9) 216 #define INPUTENABLE (1 << 8) 217 #define PULLTYPESELECT (1 << 4) 218 #define PULLUDENABLE (1 << 3) 219 #define MUXMODE(n) ((n) & 0x7) 220 221 /* Sitara AM3xxx register values */ 222 #define SLEWCTRL (1 << 6) 223 #define RXACTIVE (1 << 5) 224 #define PUTYPESEL (1 << 4) 225 #define PUDEN (1 << 3) 226 #define MMODE(n) ((n) & 0x7) 227 }; 228 struct omap_gpio_conf { 229 int pin; 230 enum { 231 conf_input = -1, 232 conf_output_0, 233 conf_output_1, 234 } conf; 235 }; 236 237 static void gxio_omap_mux_config(const struct omap_mux_conf []); 238 static int gxio_omap_mux_config_address(const char *, unsigned long, 239 const struct omap_mux_conf[], 240 const struct omap_mux_conf[]); 241 static void gxio_omap_gpio_config(const struct omap_gpio_conf[]); 242 void gxio_omap_gpio_write(int, int); 243 244 #if defined(OVERO) 245 static const struct omap_mux_conf overo_mux_i2c3_conf[] = { 246 { 0x1c2, MUXMODE(0) | INPUTENABLE }, /* i2c3_scl */ 247 { 0x1c4, MUXMODE(0) | INPUTENABLE }, /* i2c3_sda */ 248 { -1 } 249 }; 250 #endif 251 #if defined(OVERO) 252 static const struct omap_mux_conf overo_mux_mmchs2_conf[] = { 253 { 0x158, /* mmc2_clk */ 254 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 255 { 0x15a, /* mmc2_cmd */ 256 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 257 { 0x15c, /* mmc2_dat0 */ 258 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 259 { 0x15e, /* mmc2_dat1 */ 260 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 261 { 0x160, /* mmc2_dat2 */ 262 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 263 { 0x162, /* mmc2_dat3 */ 264 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 265 { -1 } 266 }; 267 #endif 268 #if defined(OVERO) 269 static const struct omap_mux_conf overo_mux_wireless_conf[] = { 270 { 0x0b4, MUXMODE(4) }, /* gpio_54:BT_nPOWERON*/ 271 { 0x0bc, MUXMODE(4) | INPUTENABLE }, /* gpio_58: WIFI_IRQ */ 272 { 0x19c, MUXMODE(4) }, /* gpio_164:BT_nRESET */ 273 { 0x5e0, MUXMODE(4) }, /* gpio_16: W2W_nRESET*/ 274 { -1 } 275 }; 276 277 #elif defined(DUOVERO) 278 static const struct omap_mux_conf duovero_mux_led_conf[] = { 279 { 0x116, MUXMODE(3) }, /* GPIO 122 */ 280 { -1 } 281 }; 282 static const struct omap_mux_conf duovero_mux_button_conf[] = { 283 { 0x114, /* GPIO 121 */ 284 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 285 { -1 } 286 }; 287 288 #elif defined(PEPPER) 289 static const struct omap_mux_conf pepper_mux_led_conf[] = { 290 { 0x850, MMODE(7) | PUDEN }, /* GPIO 52: Blue */ 291 { 0x854, MMODE(7) | PUDEN }, /* GPIO 53: Red */ 292 { -1 } 293 }; 294 static const struct omap_mux_conf pepper_mux_button_conf[] = { 295 { 0x858, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 54 */ 296 { -1 } 297 }; 298 static const struct omap_mux_conf pepper_mux_mmchs3_conf[] = { 299 { 0x844, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT0 */ 300 { 0x848, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT1 */ 301 { 0x84c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT2 */ 302 { 0x878, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT3 */ 303 { 0x888, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CMD */ 304 { 0x88c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CLK */ 305 { -1 } 306 }; 307 static const struct omap_mux_conf pepper_mux_audio_codec_conf[] = { 308 { 0x840, MMODE(7) | PUDEN }, /* GPIO 48: #Reset */ 309 { -1 } 310 }; 311 #endif 312 313 #endif 314 315 static const struct gxioconf gxioconflist[] = { 316 #if defined(GUMSTIX) 317 { "basix", basix_config }, 318 { "cfstix", cfstix_config }, 319 { "etherstix", etherstix_config }, 320 { "netcf", netcf_config }, 321 { "netcf-vx", netcf_vx_config }, 322 { "netduo-mmc", netduommc_config }, 323 { "netduo", netduo_config }, 324 { "netmicrosd", netmicrosd_config }, 325 { "netmicrosd-vx", netmicrosd_config }, 326 { "netwifimicrosd", netwifimicrosd_config }, 327 { "netmmc", netmmc_config }, 328 { "netpro-vx", netwifimicrosd_config }, 329 { "wifistix-cf", wifistix_cf_config }, 330 { "wifistix", wifistix_config }, 331 #elif defined(OVERO) 332 { "chestnut43", chestnut_config }, 333 { "gallop43", gallop_config }, 334 { "summit", summit_config }, 335 { "tobi", tobi_config }, 336 { "tobi-duo", tobiduo_config }, 337 #elif defined(DUOVERO) 338 { "parlor", parlor_config }, 339 #elif defined(PEPPER) 340 { "43c", c_config }, 341 { "43r", r_config }, 342 { "dvi", dvi_config }, 343 #endif 344 { NULL } 345 }; 346 347 int gxpcic_gpio_reset; 348 struct gxpcic_slot_irqs gxpcic_slot_irqs[2] = { { 0, -1, -1 }, { 0, -1, -1 } }; 349 350 351 #if defined(GUMSTIX) 352 /* ARGSUSED */ 353 static int 354 gxiomatch(device_t parent, cfdata_t match, void *aux) 355 { 356 357 struct pxaip_attach_args *pxa = aux; 358 bus_space_tag_t iot = &pxa2x0_bs_tag; 359 bus_space_handle_t ioh; 360 361 if (strcmp(pxa->pxa_name, match->cf_name) != 0 || 362 pxa->pxa_addr != PXAIPCF_ADDR_DEFAULT) 363 return 0; 364 365 if (bus_space_map(iot, 366 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &ioh)) 367 return 0; 368 bus_space_unmap(iot, ioh, PXA2X0_MEMCTL_SIZE); 369 370 /* nothing */ 371 return 1; 372 } 373 374 /* ARGSUSED */ 375 static void 376 gxioattach(device_t parent, device_t self, void *aux) 377 { 378 struct gxio_softc *sc = device_private(self); 379 380 aprint_normal("\n"); 381 aprint_naive("\n"); 382 383 sc->sc_dev = self; 384 sc->sc_iot = &pxa2x0_bs_tag; 385 386 if (bus_space_map(sc->sc_iot, 387 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &sc->sc_ioh)) 388 return; 389 390 /* 391 * Attach each gumstix(busheader)/overo expansion board devices. 392 */ 393 config_search_ia(gxiosearch, self, "gxio", NULL); 394 } 395 396 /* ARGSUSED */ 397 static int 398 gxiosearch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 399 { 400 struct gxio_softc *sc = device_private(parent); 401 struct gxio_attach_args gxa; 402 403 gxa.gxa_sc = sc; 404 gxa.gxa_iot = sc->sc_iot; 405 gxa.gxa_addr = cf->cf_loc[GXIOCF_ADDR]; 406 gxa.gxa_gpirq = cf->cf_loc[GXIOCF_GPIRQ]; 407 408 if (config_match(parent, cf, &gxa)) 409 config_attach(parent, cf, &gxa, gxioprint); 410 411 return 0; 412 } 413 414 /* ARGSUSED */ 415 static int 416 gxioprint(void *aux, const char *name) 417 { 418 struct gxio_attach_args *gxa = (struct gxio_attach_args *)aux; 419 420 if (gxa->gxa_addr != GXIOCF_ADDR_DEFAULT) 421 printf(" addr 0x%lx", gxa->gxa_addr); 422 if (gxa->gxa_gpirq > 0) 423 printf(" gpirq %d", gxa->gxa_gpirq); 424 return UNCONF; 425 } 426 #endif 427 428 429 #if defined(GUMSTIX) 430 /* 431 * configure for GPIO pin and expansion boards. 432 */ 433 void 434 gxio_config(void) 435 { 436 #if defined(CPU_XSCALE_PXA250) 437 struct pxa2x0_gpioconf *gumstix_gpioconf[] = { 438 pxa25x_com_ffuart_gpioconf, 439 pxa25x_com_stuart_gpioconf, 440 #ifndef GXIO_BLUETOOTH_ON_HWUART 441 pxa25x_com_btuart_gpioconf, 442 #endif 443 pxa25x_com_hwuart_gpioconf, 444 pxa25x_i2c_gpioconf, 445 pxa25x_pxaacu_gpioconf, 446 pxa255dep_gpioconf, 447 NULL 448 }; 449 #endif 450 #if defined(CPU_XSCALE_PXA270) 451 struct pxa2x0_gpioconf *verdex_gpioconf[] = { 452 pxa27x_com_ffuart_gpioconf, 453 pxa27x_com_stuart_gpioconf, 454 pxa27x_com_btuart_gpioconf, 455 pxa27x_i2c_gpioconf, 456 pxa27x_pxaacu_gpioconf, 457 pxa27x_pxamci_gpioconf, 458 pxa27x_ohci_gpioconf, 459 verdexdep_gpioconf, 460 NULL 461 }; 462 #endif 463 464 /* XXX: turn off for power of bluetooth module */ 465 #if defined(CPU_XSCALE_PXA250) 466 pxa2x0_gpio_set_function(7, GPIO_OUT | GPIO_CLR); 467 #elif defined(CPU_XSCALE_PXA270) 468 pxa2x0_gpio_set_function(12, GPIO_OUT | GPIO_CLR); 469 #endif 470 delay(100); 471 472 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 473 pxa2x0_gpio_config( 474 (CPU_IS_PXA250) ? gumstix_gpioconf : verdex_gpioconf); 475 #elif defined(CPU_XSCALE_PXA270) || defined(CPU_XSCALE_PXA250) 476 #if defined(CPU_XSCALE_PXA270) 477 pxa2x0_gpio_config(verdex_gpioconf); 478 #else 479 pxa2x0_gpio_config(gumstix_gpioconf); 480 #endif 481 #endif 482 } 483 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 484 static void 485 gxio_omap_mux_config(const struct omap_mux_conf mux_conf[]) 486 { 487 #if defined(OVERO) 488 const vaddr_t ctrlmod_base = OVERO_L4_CORE_VBASE + 0x2000; 489 #elif defined(DUOVERO) 490 const vaddr_t ctrlmod_base = DUOVERO_L4_CM_VBASE; 491 #elif defined(PEPPER) 492 const vaddr_t ctrlmod_base = PEPPER_PRCM_VBASE + 0x10000; 493 #endif 494 int i; 495 496 for (i = 0; mux_conf[i].offset != -1; i++) 497 #if !defined(TI_AM335X) 498 ioreg16_write(ctrlmod_base + mux_conf[i].offset, 499 mux_conf[i].value); 500 #else 501 ioreg_write(ctrlmod_base + mux_conf[i].offset, 502 mux_conf[i].value); 503 #endif 504 } 505 506 static int 507 gxio_omap_mux_config_address(const char *name, unsigned long address, 508 const struct omap_mux_conf mux_conf[], 509 const struct omap_mux_conf not_mux_conf[]) 510 { 511 extern struct cfdata cfdata[]; 512 cfdata_t cf = &cfdata[0]; 513 514 while (cf->cf_name != NULL) { 515 if (strcmp(name, cf->cf_name) == 0 && 516 address == cf->cf_loc[OBIOCF_ADDR]) { 517 gxio_omap_mux_config(mux_conf); 518 return 0; 519 } 520 cf++; 521 } 522 523 if (not_mux_conf == NULL) 524 return -1; 525 526 gxio_omap_mux_config(not_mux_conf); 527 return 0; 528 } 529 530 #if defined(OVERO) 531 #define gpio_reg_read ioreg_read 532 #define gpio_reg_write ioreg_write 533 #elif defined(DUOVERO) || defined(PEPPER) 534 #define gpio_reg_read(a) ioreg_read((a) + GPIO_SIZE2) 535 #define gpio_reg_write(a, v) ioreg_write((a) + GPIO_SIZE2, (v)) 536 #endif 537 538 static const vaddr_t gpio_bases[] = { 539 #if defined(OVERO) 540 #define OVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 541 #define GPIO(n) GPIO ## n ## _BASE_3530 542 #define BASE(a, n) \ 543 (OVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP3530_L4_ ## a ## _BASE)) 544 545 GPIO1_BASE_3530, 546 GPIO2_BASE_3530, 547 GPIO3_BASE_3530, 548 GPIO4_BASE_3530, 549 GPIO5_BASE_3530, 550 GPIO6_BASE_3530, 551 552 #elif defined(DUOVERO) 553 #define DUOVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 554 #define GPIO(n) GPIO ## n ## _BASE_4430 555 #define BASE(a, n) \ 556 (DUOVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP4430_L4_ ## a ## _BASE)) 557 558 DUOVERO_GPIO_VBASE(1), 559 DUOVERO_GPIO_VBASE(2), 560 DUOVERO_GPIO_VBASE(3), 561 DUOVERO_GPIO_VBASE(4), 562 DUOVERO_GPIO_VBASE(5), 563 564 #elif defined(PEPPER) 565 #define PEPPER_GPIO_VBASE(n) ((n) == 0 ? WAKEUP(n) : PERIPHERAL(n)) 566 #define GPIO(n) GPIO ## n ## _BASE_TI_AM335X 567 #define WAKEUP(n) (PEPPER_PRCM_VBASE + (GPIO(n) - OMAP2_CM_BASE)) 568 #define PERIPHERAL(n) \ 569 (PEPPER_L4_PERIPHERAL_VBASE + (GPIO(n) - TI_AM335X_L4_PERIPHERAL_BASE)) 570 571 PEPPER_GPIO_VBASE(0), 572 PEPPER_GPIO_VBASE(1), 573 PEPPER_GPIO_VBASE(2), 574 PEPPER_GPIO_VBASE(3), 575 #endif 576 }; 577 578 static void 579 gxio_omap_gpio_config(const struct omap_gpio_conf gpio_conf[]) 580 { 581 vaddr_t gpio_base; 582 int mask, i; 583 584 for (i = 0; gpio_conf[i].pin != -1; i++) { 585 gpio_base = gpio_bases[gpio_conf[i].pin / 32]; 586 mask = 1 << (gpio_conf[i].pin % 32); 587 switch (gpio_conf[i].conf) { 588 case conf_input: 589 ioreg_write(gpio_base + GPIO_OE, 590 ioreg_read(gpio_base + GPIO_OE) | mask); 591 break; 592 case conf_output_0: 593 ioreg_write(gpio_base + GPIO_OE, 594 ioreg_read(gpio_base + GPIO_OE) | ~mask); 595 #if 0 596 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 597 #else 598 ioreg_write(gpio_base + GPIO_DATAOUT, 599 ioreg_read(gpio_base + GPIO_DATAOUT) & ~mask); 600 #endif 601 break; 602 case conf_output_1: 603 ioreg_write(gpio_base + GPIO_OE, 604 ioreg_read(gpio_base + GPIO_OE) | ~mask); 605 #if 0 606 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 607 #else 608 ioreg_write(gpio_base + GPIO_DATAOUT, 609 ioreg_read(gpio_base + GPIO_DATAOUT) | mask); 610 #endif 611 break; 612 } 613 } 614 } 615 616 void 617 gxio_omap_gpio_write(int pin, int val) 618 { 619 vaddr_t gpio_base; 620 int mask; 621 622 KASSERT(pin / 32 < __arraycount(gpio_bases)); 623 624 gpio_base = gpio_bases[pin / 32]; 625 mask = 1 << (pin % 32); 626 if (val == 0) 627 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 628 else 629 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 630 } 631 632 /* 633 * configure for MUX, GPIO. 634 */ 635 void 636 gxio_config(void) 637 { 638 const struct omap_mux_conf *mux_conf[] = { 639 #if defined(OVERO) 640 overo_mux_i2c3_conf, 641 overo_mux_mmchs2_conf, 642 overo_mux_wireless_conf, 643 #elif defined(DUOVERO) 644 duovero_mux_led_conf, 645 duovero_mux_button_conf, 646 #elif defined(PEPPER) 647 pepper_mux_led_conf, 648 pepper_mux_button_conf, 649 pepper_mux_mmchs3_conf, 650 pepper_mux_audio_codec_conf, 651 #endif 652 }; 653 const struct omap_gpio_conf gpio_conf[] = { 654 #if defined(OVERO) 655 { 16, conf_output_0 }, /* Wireless: #Reset */ 656 #elif defined(PEPPER) 657 { 48, conf_output_0 }, /* Audio Codec: #Reset */ 658 #endif 659 { -1 } 660 }; 661 int i; 662 663 for (i = 0; i < __arraycount(mux_conf); i++) 664 gxio_omap_mux_config(mux_conf[i]); 665 gxio_omap_gpio_config(gpio_conf); 666 } 667 #endif 668 669 static int 670 gxio_find_default_expansion(void) 671 { 672 #ifdef GXIO_DEFAULT_EXPANSION 673 int i; 674 675 /* Find out the default expansion */ 676 for (i = 0; gxioconflist[i].name != NULL; i++) 677 if (strncasecmp(gxioconflist[i].name, GXIO_DEFAULT_EXPANSION, 678 strlen(gxioconflist[i].name) + 1) == 0) 679 break; 680 return gxioconflist[i].name == NULL ? -1 : i; 681 #else 682 return -1; 683 #endif 684 } 685 686 void 687 gxio_config_expansion(const char *expansion) 688 { 689 int i, d; 690 691 d = gxio_find_default_expansion(); 692 693 /* Print information about expansions */ 694 printf("supported expansions:\n"); 695 for (i = 0; gxioconflist[i].name != NULL; i++) 696 printf(" %s%s\n", gxioconflist[i].name, 697 i == d ? " (DEFAULT)" : ""); 698 699 700 if (expansion == NULL) { 701 printf("not specified 'expansion=' in the boot args.\n"); 702 i = -1; 703 } else { 704 for (i = 0; gxioconflist[i].name != NULL; i++) 705 if (strncasecmp(gxioconflist[i].name, expansion, 706 strlen(gxioconflist[i].name) + 1) == 0) 707 break; 708 if (gxioconflist[i].name == NULL) { 709 printf("unknown expansion specified: %s\n", expansion); 710 i = -1; 711 } 712 } 713 714 /* Do some magic stuff for PEPPER */ 715 #if defined(PEPPER) 716 if (i < 0) { 717 struct pepper_board_id { 718 unsigned int device_vendor; 719 #define GUMSTIX_PEPPER 0x30000200 /* 1st gen */ 720 #define GUMSTIX_PEPPER_DVI 0x31000200 /* DVI and newer */ 721 unsigned char revision; 722 unsigned char content; 723 char fab_revision[8]; 724 char env_var[16]; 725 char env_setting[64]; 726 } id; 727 const vaddr_t i2c_base = PEPPER_PRCM_VBASE + 0xb000; 728 const uint8_t eeprom = 0x50; 729 const uint8_t len = sizeof(id); 730 int rv; 731 732 rv = read_i2c_device(i2c_base, eeprom, 0x00, len, (void *)&id); 733 if (rv == 0) 734 if (id.device_vendor == GUMSTIX_PEPPER) { 735 printf("configure auto detected expansion" 736 " (pepper)\n"); 737 pepper_config(); 738 return; 739 } 740 } 741 #endif 742 743 /* 744 * Now proceed to configure the default expansion if one was 745 * specified (and found) or return. 746 */ 747 const char *toconfigure; 748 if (i < 0) { 749 #ifdef GXIO_DEFAULT_EXPANSION 750 if (d == -1) { 751 printf("default expansion (%s) not found\n", 752 GXIO_DEFAULT_EXPANSION); 753 return; 754 } 755 expansion = GXIO_DEFAULT_EXPANSION; 756 i = d; 757 toconfigure = "default"; 758 #else 759 return; 760 #endif 761 } else 762 toconfigure = "specified"; 763 764 printf("configure %s expansion (%s)\n", toconfigure, expansion); 765 gxioconflist[i].config(); 766 } 767 768 769 #if defined(GUMSTIX) 770 771 static void 772 basix_config(void) 773 { 774 775 pxa2x0_gpio_set_function(8, GPIO_ALT_FN_1_OUT); /* MMCCS0 */ 776 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_1_OUT); /* MMCCLK */ 777 #if 0 778 /* this configuration set by gxmci.c::pxamci_attach() */ 779 pxa2x0_gpio_set_function(11, GPIO_IN); /* nSD_DETECT */ 780 pxa2x0_gpio_set_function(22, GPIO_IN); /* nSD_WP */ 781 #endif 782 } 783 784 static void 785 cfstix_config(void) 786 { 787 u_int gpio, npoe_fn; 788 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 789 int bvd = (CPU_IS_PXA250) ? 4 : 111; 790 #else 791 #if defined(CPU_XSCALE_PXA270) 792 const int bvd = 111; 793 #else 794 const int bvd = 4; 795 #endif 796 #endif 797 798 if (CPU_IS_PXA250) { 799 gxpcic_slot_irqs[0].valid = 1; 800 gxpcic_slot_irqs[0].cd = 11; 801 gxpcic_slot_irqs[0].prdy = 26; 802 gxpcic_gpio_reset = 8; 803 } else { 804 gxpcic_slot_irqs[0].valid = 1; 805 gxpcic_slot_irqs[0].cd = 104; 806 gxpcic_slot_irqs[0].prdy = 96; 807 gxpcic_gpio_reset = 97; 808 } 809 810 #if 1 811 /* PCD/PRDY set by pxa2x0_pcic.c::pxapcic_attach_common() */ 812 #else 813 pxa2x0_gpio_set_function(11, GPIO_IN); /* PCD1 */ 814 pxa2x0_gpio_set_function(26, GPIO_IN); /* PRDY1/~IRQ1 */ 815 #endif 816 pxa2x0_gpio_set_function(bvd, GPIO_IN); /* BVD1/~STSCHG1 */ 817 818 for (gpio = 48, npoe_fn = 0; gpio <= 53 ; gpio++) 819 npoe_fn |= pxa2x0_gpio_get_function(gpio); 820 npoe_fn &= GPIO_SET; 821 822 pxa2x0_gpio_set_function(48, GPIO_ALT_FN_2_OUT | npoe_fn); /* nPOE */ 823 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 824 pxa2x0_gpio_set_function(50, GPIO_ALT_FN_2_OUT); /* nPIOR */ 825 pxa2x0_gpio_set_function(51, GPIO_ALT_FN_2_OUT); /* nPIOW */ 826 if (CPU_IS_PXA250) { 827 pxa2x0_gpio_set_function(52, GPIO_ALT_FN_2_OUT); /* nPCE1 */ 828 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_2_OUT); /* nPCE2 */ 829 pxa2x0_gpio_set_function(54, GPIO_ALT_FN_2_OUT); /* pSKTSEL */ 830 } else { 831 pxa2x0_gpio_set_function(102, GPIO_ALT_FN_1_OUT); /* nPCE1 */ 832 pxa2x0_gpio_set_function(105, GPIO_ALT_FN_1_OUT); /* nPCE2 */ 833 pxa2x0_gpio_set_function(79, GPIO_ALT_FN_1_OUT); /* pSKTSEL */ 834 } 835 pxa2x0_gpio_set_function(55, GPIO_ALT_FN_2_OUT); /* nPREG */ 836 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); /* nPWAIT */ 837 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); /* nIOIS16 */ 838 } 839 840 static void 841 etherstix_config(void) 842 { 843 extern struct cfdata cfdata[]; 844 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 845 int rst = (CPU_IS_PXA250) ? 80 : 32; 846 int irq = (CPU_IS_PXA250) ? 36 : 99; 847 #else 848 #if defined(CPU_XSCALE_PXA270) 849 const int rst = 32, irq = 99; 850 #else 851 const int rst = 80, irq = 36; 852 #endif 853 #endif 854 int i; 855 856 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 857 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 858 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_SET); /* RESET 1 */ 859 delay(1); 860 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_CLR); 861 delay(50000); 862 863 for (i = 0; cfdata[i].cf_name != NULL; i++) 864 if (strcmp(cfdata[i].cf_name, "sm") == 0 && 865 strcmp(cfdata[i].cf_atname, "sm_gxio") == 0 && 866 cfdata[i].cf_loc[GXIOCF_ADDR] == 0x04000300 && 867 cfdata[i].cf_loc[GXIOCF_GPIRQ] == GXIOCF_GPIRQ_DEFAULT) 868 cfdata[i].cf_loc[GXIOCF_GPIRQ] = irq; 869 } 870 871 static void 872 netcf_config(void) 873 { 874 875 etherstix_config(); 876 cfstix_config(); 877 } 878 879 static void 880 netcf_vx_config(void) 881 { 882 883 /* 884 * XXXX: More power is necessary for NIC and USB??? 885 * (no document. from Linux) 886 */ 887 888 pxa2x0_gpio_set_function(27, GPIO_IN); 889 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); 890 pxa2x0_gpio_set_function(118, GPIO_ALT_FN_1_IN | GPIO_CLR); 891 892 etherstix_config(); 893 cfstix_config(); 894 if (CPU_IS_PXA270) { 895 /* Overwrite */ 896 gxpcic_slot_irqs[0].cd = 104; 897 gxpcic_slot_irqs[0].prdy = 109; 898 gxpcic_gpio_reset = 110; 899 }; 900 } 901 902 static void 903 netduommc_config(void) 904 { 905 906 netduo_config(); 907 basix_config(); 908 } 909 910 static void 911 netduo_config(void) 912 { 913 914 etherstix_config(); 915 916 pxa2x0_gpio_set_function(78, GPIO_ALT_FN_2_OUT); /* nCS 2 */ 917 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_SET); /* RESET 2 */ 918 delay(1); 919 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_CLR); 920 delay(50000); 921 } 922 923 static void 924 netmicrosd_config(void) 925 { 926 927 /* MicroSD(mci) always configure on PXA270 */ 928 929 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 930 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 931 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); /* RESET 1 */ 932 delay(hz / 2); 933 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_SET); 934 delay(50000); 935 } 936 937 static void 938 netwifimicrosd_config(void) 939 { 940 941 netmicrosd_config(); 942 943 cfstix_config(); 944 /* However use pxamci. */ 945 pxa2x0_gpio_set_function(111, GPIO_CLR | GPIO_ALT_FN_1_IN); 946 /* Power to Marvell 88W8385 */ 947 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 948 } 949 950 static void 951 netmmc_config(void) 952 { 953 954 etherstix_config(); 955 basix_config(); 956 } 957 958 static void 959 wifistix_config(void) 960 { 961 962 cfstix_config(); 963 964 /* Power to Marvell 88W8385 */ 965 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 966 } 967 968 static void 969 wifistix_cf_config(void) 970 { 971 972 gxpcic_slot_irqs[1].valid = 1; 973 gxpcic_slot_irqs[1].cd = 36; 974 gxpcic_slot_irqs[1].prdy = 27; 975 976 #if 1 977 /* this configuration set by pxa2x0_pcic.c::pxapcic_attach_common() */ 978 #else 979 pxa2x0_gpio_set_function(36, GPIO_IN); /* PCD2 */ 980 pxa2x0_gpio_set_function(27, GPIO_IN); /* PRDY2/~IRQ2 */ 981 #endif 982 pxa2x0_gpio_set_function(18, GPIO_IN); /* BVD2/~STSCHG2 */ 983 984 cfstix_config(); 985 986 /* Power to Marvell 88W8385 */ 987 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 988 } 989 990 #elif defined(OVERO) 991 992 static void 993 eth0_config(void) 994 { 995 /* 996 * ETH0 connects via CS5. It use GPIO 176 for IRQ. 997 * Also GPIO 64 is NRESET. 998 */ 999 1000 smsh_config(NULL, 176, 64); 1001 } 1002 1003 static void 1004 eth1_config(void) 1005 { 1006 struct omap_mux_conf eth1_mux_conf[] = { 1007 { 0x0d2, MUXMODE(4) | INPUTENABLE }, 1008 { -1 } 1009 }; 1010 1011 /* 1012 * ETH1 connects via CS4. It use GPIO 65 for IRQ. 1013 */ 1014 1015 smsh_config(eth1_mux_conf, 65, 64); 1016 } 1017 1018 static void 1019 dvi_config(void) 1020 { 1021 static const struct omap_mux_conf overo_mux_dvi_conf[] = { 1022 { 0x0d4, MUXMODE(0) }, /* dss_pclk */ 1023 { 0x0d6, MUXMODE(0) }, /* dss_pclk */ 1024 { 0x0d8, MUXMODE(0) }, /* dss_pclk */ 1025 { 0x0da, MUXMODE(0) }, /* dss_pclk */ 1026 { 0x0dc, MUXMODE(0) }, /* dss_pclk */ 1027 { 0x0de, MUXMODE(0) }, /* dss_pclk */ 1028 { 0x0e0, MUXMODE(0) }, /* dss_pclk */ 1029 { 0x0e2, MUXMODE(0) }, /* dss_pclk */ 1030 { 0x0e4, MUXMODE(0) }, /* dss_pclk */ 1031 { 0x0e6, MUXMODE(0) }, /* dss_pclk */ 1032 { 0x0e8, MUXMODE(0) }, /* dss_pclk */ 1033 { 0x0ea, MUXMODE(0) }, /* dss_pclk */ 1034 { 0x0ec, MUXMODE(0) }, /* dss_pclk */ 1035 { 0x0ee, MUXMODE(0) }, /* dss_pclk */ 1036 { 0x0f0, MUXMODE(0) }, /* dss_pclk */ 1037 { 0x0f2, MUXMODE(0) }, /* dss_pclk */ 1038 { 0x0f4, MUXMODE(0) }, /* dss_pclk */ 1039 { 0x0f6, MUXMODE(0) }, /* dss_pclk */ 1040 { 0x0f8, MUXMODE(0) }, /* dss_pclk */ 1041 { 0x0fa, MUXMODE(0) }, /* dss_pclk */ 1042 { 0x0fc, MUXMODE(0) }, /* dss_pclk */ 1043 { 0x0fe, MUXMODE(0) }, /* dss_pclk */ 1044 { 0x100, MUXMODE(0) }, /* dss_pclk */ 1045 { 0x102, MUXMODE(0) }, /* dss_pclk */ 1046 { 0x104, MUXMODE(0) }, /* dss_pclk */ 1047 { 0x106, MUXMODE(0) }, /* dss_pclk */ 1048 { 0x108, MUXMODE(0) }, /* dss_pclk */ 1049 { 0x10a, MUXMODE(0) }, /* dss_pclk */ 1050 { -1 } 1051 }; 1052 1053 gxio_omap_mux_config(overo_mux_dvi_conf); 1054 } 1055 1056 static void 1057 lcd_config(char type) 1058 { 1059 static const struct omap_mux_conf overo_mux_mcspi1_conf[] = { 1060 { 0x1c8, MUXMODE(0) | INPUTENABLE }, /* mcspi1_clk */ 1061 { 0x1ca, MUXMODE(0) | INPUTENABLE }, /* mcspi1_simo*/ 1062 { 0x1cc, MUXMODE(0) | INPUTENABLE }, /* mcspi1_somi*/ 1063 { 0x1ce, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs0 */ 1064 { 0x1d0, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs1 */ 1065 { -1 } 1066 }; 1067 static const struct omap_mux_conf overo_mux_ads7846_conf[] = { 1068 { 0x138, /* gpio_114: NPENIRQ */ 1069 MUXMODE(4) | PULLUDENABLE | INPUTENABLE }, 1070 { -1 } 1071 }; 1072 static const struct omap_mux_conf overo_mux_lcd_conf[] = { 1073 { 0x174, MUXMODE(4) }, /* gpio_144: DISPLAY_EN */ 1074 { 0x176, MUXMODE(4) }, /* gpio_145: Brightness */ 1075 { -1 } 1076 }; 1077 1078 static const struct omap_gpio_conf overo_gpio_lcd_conf[] = { 1079 { 144, conf_output_0 }, /* DISPLAY_EN */ 1080 { 145, conf_output_0 }, /* Brightness */ 1081 { -1 } 1082 }; 1083 1084 dvi_config(); 1085 if (type != 'C') { 1086 gxio_omap_mux_config(overo_mux_mcspi1_conf); 1087 gxio_omap_mux_config(overo_mux_ads7846_conf); 1088 } 1089 gxio_omap_mux_config(overo_mux_lcd_conf); 1090 1091 gxio_omap_gpio_config(overo_gpio_lcd_conf); 1092 } 1093 1094 enum { 1095 uart1_if_exists = 0, 1096 force_uart1 1097 }; 1098 static void 1099 header_40pin_config(int uart1) 1100 { 1101 static const struct omap_mux_conf overo_mux_40pin_header_conf[] = { 1102 /* 1103 * 1: GND 1104 * 2: VCC_3.3 1105 * 3: GPIO171_SPI1_CLK 1106 * 4: GPIO114_SPI1_NIRQ 1107 * 5: GPIO172_SPI1_MOSI 1108 * 6: GPIO174_SPI1_CS0 1109 * 7: GPIO173_SPI1_MISO 1110 * 8: GPIO175_SPI1_CS1 1111 * 9: GPIO151_RXD1 1112 * 10: GPIO148_TXD1 1113 * 11: SYS_EN 1114 * 12: VBACKUP 1115 * 13: GPIO0_WAKEUP 1116 * 14: POWERON 1117 * 15: GND 1118 * 16: VCC_1.8 1119 * 17: GPIO128_GPS_PPS 1120 * 18: GPIO127_TS_IRQ 1121 * 19: GPIO170_HDQ_1WIRE 1122 * 20: GPIO163_IR_CTS3 1123 * 21: GPIO165_IR_RXD3 (console) 1124 * 22: GPIO166_IR_TXD3 (console) 1125 * 23: GPIO184_SCL3 (system eeprom) 1126 * 24: GPIO185_SDA3 (system eeprom) 1127 * 25: GND 1128 * 26: VCC_1.8 1129 * 27: GPIO146_PWM11 1130 * 28: GPIO145_PWM10 1131 * 29: GPIO147_PWM8 1132 * 30: GPIO144_PWM9 1133 * 31: PWM0 (TPS65950) 1134 * 32: PWM1 (TPS65950) 1135 * 33: ADCIN7 (TPS65950) 1136 * 34: ADCIN2 (TPS65950) 1137 * 35: ADCIN6 (TPS65950) 1138 * 36: ADCIN5 (TPS65950) 1139 * 37: AGND (TPS65950) 1140 * 38: ADCIN3 (TPS65950) 1141 * 39: ADCIN4 (TPS65950) 1142 * 40: VIN (TPS65950) 1143 */ 1144 1145 { 0x152, MUXMODE(4) | INPUTENABLE }, /* gpio_127 */ 1146 { 0x154, MUXMODE(4) | INPUTENABLE }, /* gpio_128 */ 1147 { 0x174, MUXMODE(4) | INPUTENABLE }, /* gpio_144 */ 1148 { 0x176, MUXMODE(4) | INPUTENABLE }, /* gpio_145 */ 1149 { 0x178, MUXMODE(4) | INPUTENABLE }, /* gpio_146 */ 1150 { 0x17a, MUXMODE(4) | INPUTENABLE }, /* gpio_147 */ 1151 { 0x19a, MUXMODE(4) | INPUTENABLE }, /* gpio_163 */ 1152 { -1 } 1153 }; 1154 static const struct omap_mux_conf overo_mux_uart1_conf[] = { 1155 { 0x17c, MUXMODE(0) }, /* uart1_tx */ 1156 { 0x182, MUXMODE(0) | INPUTENABLE }, /* uart1_rx */ 1157 { -1 } 1158 }; 1159 static const struct omap_mux_conf overo_mux_no_uart1_conf[] = { 1160 { 0x17c, MUXMODE(4) | INPUTENABLE }, /* gpio_148 */ 1161 { 0x182, MUXMODE(4) | INPUTENABLE }, /* gpio_151 */ 1162 { -1 } 1163 }; 1164 static const struct omap_mux_conf overo_mux_hdq_conf[] = { 1165 #if 0 1166 { 0x1c4, MUXMODE(0) | ??? | INPUTENABLE }, /* hdq_sio */ 1167 #endif 1168 { -1 } 1169 }; 1170 static const struct omap_mux_conf overo_mux_no_hdq_conf[] = { 1171 { 0x1c4, MUXMODE(4) | INPUTENABLE }, /* gpio_170 */ 1172 { -1 } 1173 }; 1174 1175 gxio_omap_mux_config(overo_mux_40pin_header_conf); 1176 if (uart1 == force_uart1) 1177 gxio_omap_mux_config(overo_mux_uart1_conf); 1178 else 1179 gxio_omap_mux_config_address("com", 0x4806a000, 1180 overo_mux_uart1_conf, overo_mux_no_uart1_conf); 1181 gxio_omap_mux_config_address("hdq", 0x480b2000, 1182 overo_mux_hdq_conf, overo_mux_no_hdq_conf); 1183 } 1184 1185 static void 1186 chestnut_config(void) 1187 { 1188 static const struct omap_mux_conf chestnut_mux_conf[] = { 1189 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1190 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1191 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1192 { -1 } 1193 }; 1194 1195 eth0_config(); 1196 lcd_config('R'); 1197 1198 header_40pin_config(uart1_if_exists); 1199 gxio_omap_mux_config(chestnut_mux_conf); 1200 } 1201 1202 static void 1203 gallop_config(void) 1204 { 1205 static const struct omap_mux_conf gallop43_mux_conf[] = { 1206 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1207 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1208 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1209 { -1 } 1210 }; 1211 1212 lcd_config('R'); 1213 1214 header_40pin_config(force_uart1); 1215 gxio_omap_mux_config(gallop43_mux_conf); 1216 } 1217 1218 static void 1219 summit_config(void) 1220 { 1221 1222 dvi_config(); 1223 1224 header_40pin_config(uart1_if_exists); 1225 } 1226 1227 static void 1228 tobi_config(void) 1229 { 1230 1231 eth0_config(); 1232 dvi_config(); 1233 1234 header_40pin_config(uart1_if_exists); 1235 } 1236 1237 static void 1238 tobiduo_config(void) 1239 { 1240 1241 eth0_config(); 1242 eth1_config(); 1243 } 1244 1245 #elif defined(DUOVERO) 1246 1247 static void 1248 ehci_config(void) 1249 { 1250 uint32_t val; 1251 1252 #define SCRM_ALTCLKSRC 0xa110 1253 #define ALTCLKSRC_ENABLE_EXT (1 << 3) 1254 #define ALTCLKSRC_ENABLE_INT (1 << 2) 1255 #define ALTCLKSRC_MODE_MASK (3 << 0) 1256 #define ALTCLKSRC_MODE_POWERDOWN (0 << 0) 1257 #define ALTCLKSRC_MODE_ACTIVE (1 << 0) 1258 #define ALTCLKSRC_MODE_BYPASS (2 << 0) 1259 #define SCRM_AUXCLK3 0xa31c 1260 #define AUXCLK3_CLKDIV(n) (((n) - 1) << 16) 1261 #define AUXCLK3_CLKDIV_MASK (0xf << 16) 1262 #define AUXCLK3_ENABLE (1 << 8) 1263 #define AUXCLK3_SRCSELECT_MASK (3 << 1) 1264 #define AUXCLK3_SRCSELECT_SYSCLK (0 << 1) 1265 #define AUXCLK3_SRCSELECT_CORE (1 << 1) 1266 #define AUXCLK3_SRCSELECT_PERDPLL (2 << 1) 1267 #define AUXCLK3_SRCSELECT_ALTCLK (3 << 1) 1268 #define AUXCLK3_POLARITY_LOW (0 << 0) 1269 #define AUXCLK3_POLARITY_HIGH (1 << 0) 1270 1271 /* Use the 1/2 auxiliary clock #3 of system clock. */ 1272 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3); 1273 val &= ~(AUXCLK3_CLKDIV_MASK | AUXCLK3_SRCSELECT_MASK); 1274 val |= (AUXCLK3_CLKDIV(2) | AUXCLK3_ENABLE | AUXCLK3_SRCSELECT_SYSCLK); 1275 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3, val); 1276 1277 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC); 1278 val &= ~ALTCLKSRC_MODE_MASK; 1279 val |= ALTCLKSRC_MODE_ACTIVE; 1280 val |= (ALTCLKSRC_ENABLE_EXT | ALTCLKSRC_ENABLE_INT); 1281 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC, val); 1282 } 1283 1284 static void 1285 parlor_config(void) 1286 { 1287 #if 0 1288 static const struct omap_mux_conf parlor_mux_40pin_header_conf[] = { 1289 /* 1290 * 1: GND 1291 * 2: GND 1292 * 3: MCSPI1_CLK or GPIO 134 1293 * 4: MCSPI1_CS0 or GPIO 137 1294 * 5: MCSPI1_SIMO or GPIO 136 1295 * 6: MCSPI1_CS1 or GPIO 138 1296 * 7: MCSPI1_SOMI or GPIO 135 1297 * 8: MCSPI1_CS2 or GPIO 139 1298 * 9: HDQ_SIO or GPIO 127 1299 * 10: MCSPI1_CS3 or GPIO 140 1300 * 11: SDMMC3_CMD or GPIO ??? 1301 * 12: I2C2_SCL or GPIO 128 1302 * 13: SDMMC3_CLK or GPIO ??? 1303 * 14: I2C2_SDA or GPIO 129 1304 * 15: UART2_TX or SDMMC3_DAT1 or GPIO 126 1305 * 16: PMIC_PWM2 (TWL6030) 1306 * 17: UART2_RX or SDMMC3_DAT0 or GPIO 125 1307 * 18: PMIC_PWM1 (TWL6030) 1308 * 19: BSP2_CLKX or GPIO 110 1309 * 20: BSP2_FSX or GPIO 113 1310 * 21: BSP2_DX or GPIO 112 1311 * 22: BSP2_DR or GPIO 111 1312 * 23: BSP2_CLKS or GPIO 118 1313 * 24: FREF1 1314 * 25: MCSPI4_SOMI or GPIO 153 1315 * 26: PMIC_NRESWARN 1316 * 27: MCSPI4_SIMO or GPIO 152 1317 * 28: SYSEN 1318 * 29: MCSPI4_CLK or GPIO 151 1319 * 30: PWRON 1320 * 31: MCSPI4_CS0 or GPIO 154 1321 * 32: REGEN1 1322 * 33: ADCIN3 (TWL6030) 1323 * 34: VCC_1.0 1324 * 35: ADCIN4_VREF (TWL6030) 1325 * 36: VDD_VAUX2 1326 * 37: ADCIN4 (TWL6030) 1327 * 38: VCC_3.3 1328 * 39: ADCIN5 (TWL6030) 1329 * 40: V_BATT_5 1330 */ 1331 { -1 } 1332 }; 1333 #endif 1334 static const struct omap_mux_conf parlor_mux_mcspi1_conf[] = { 1335 #if 0 1336 { 0x132, /* 3: MCSPI1_CLK */ 1337 MUXMODE(0) | ??? }, 1338 { 0x138, /* 4: MCSPI1_CS0 */ 1339 MUXMODE(0) | ??? }, 1340 { 0x136, /* 5: MCSPI1_SIMO */ 1341 MUXMODE(0) | ??? }, 1342 { 0x13a, /* 6: MCSPI1_CS1 */ 1343 MUXMODE(0) | ??? }, 1344 { 0x134, /* 7: MCSPI1_SOMI */ 1345 MUXMODE(0) | ??? | INPUTENABLE }, 1346 { 0x13c, /* 8: MCSPI1_CS2 */ 1347 MUXMODE(0) | ??? }, 1348 { 0x13e, /* 10: MCSPI1_CS3 */ 1349 MUXMODE(0) | ??? }, 1350 #endif 1351 { -1 } 1352 }; 1353 static const struct omap_mux_conf parlor_mux_no_mcspi1_conf[] = { 1354 { 0x132, /* 3: GPIO 134 */ 1355 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1356 { 0x138, /* 4: GPIO 137 */ 1357 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1358 { 0x136, /* 5: GPIO 136 */ 1359 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1360 { 0x13a, /* 6: GPIO 138 */ 1361 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1362 { 0x134, /* 7: GPIO 135 */ 1363 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1364 { 0x13c, /* 8: GPIO 139 */ 1365 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1366 { 0x13e, /* 10: GPIO 140 */ 1367 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1368 { -1 } 1369 }; 1370 static const struct omap_mux_conf parlor_mux_hdq_conf[] = { 1371 #if 0 1372 { 0x120, /* 9: HDQ_SIO */ 1373 MUXMODE(0) | ??? | INPUTENABLE }, 1374 #endif 1375 { -1 } 1376 }; 1377 static const struct omap_mux_conf parlor_mux_no_hdq_conf[] = { 1378 { 0x120, /* 9: GPIO_127 */ 1379 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1380 { -1 } 1381 }; 1382 static const struct omap_mux_conf parlor_mux_i2c2_conf[] = { 1383 { 0x126, /* 12: I2C2_SCL */ 1384 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1385 { 0x128, /* 14: I2C2_SDA */ 1386 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1387 { -1 } 1388 }; 1389 static const struct omap_mux_conf parlor_mux_no_i2c2_conf[] = { 1390 { 0x126, /* 12: GPIO 128 */ 1391 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1392 { 0x128, /* 14: GPIO 129 */ 1393 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1394 { -1 } 1395 }; 1396 static const struct omap_mux_conf parlor_mux_sdmmc3_conf[] = { 1397 #if 0 1398 11 SDMMC3_CMD DuoVero J2 A15 <- omap pin AG10 1399 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1400 13 SDMMC3_CLK DuoVero J2 A16 <- omap pin AE9 1401 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1402 #endif 1403 { 0x11c, /* 17: SDMMC3_DAT0 */ 1404 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1405 { 0x11e, /* 15: SDMMC3_DAT1 */ 1406 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1407 { -1 } 1408 }; 1409 static const struct omap_mux_conf parlor_mux_uart2_conf[] = { 1410 { 0x11c, /* 17: UART2_RX */ 1411 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1412 { 0x11e, 1413 MUXMODE(0) | PULLUDENABLE }, /* 15: UART2_TX */ 1414 { -1 } 1415 }; 1416 static const struct omap_mux_conf parlor_mux_no_uart2_conf[] = { 1417 { 0x11c, /* 17: GPIO 125 */ 1418 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1419 { 0x11e, /* 15: GPIO 126 */ 1420 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1421 { -1 } 1422 }; 1423 static const struct omap_mux_conf parlor_mux_bsp2_conf[] = { 1424 { 0x0f6, /* 19: BSP2_CLKX */ 1425 MUXMODE(0) | INPUTENABLE }, 1426 { 0x0fc, /* 20: BSP2_FSX */ 1427 MUXMODE(0) | INPUTENABLE }, 1428 { 0x0fa, /* 21: BSP2_DX */ 1429 MUXMODE(0) | PULLUDENABLE }, 1430 { 0x0f8, /* 22: BSP2_DR */ 1431 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1432 { 0x10e, /* 23: BSP2_CLKS */ 1433 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1434 { -1 } 1435 }; 1436 static const struct omap_mux_conf parlor_mux_no_bsp2_conf[] = { 1437 { 0x0f6, /* 19: GPIO 110 */ 1438 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1439 { 0x0fc, /* 20: GPIO 113 */ 1440 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1441 { 0x0fa, /* 21: GPIO 112 */ 1442 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1443 { 0x0f8, /* 22: GPIO 111 */ 1444 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1445 { 0x10e, /* 23: GPIO 118 */ 1446 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1447 { -1 } 1448 }; 1449 static const struct omap_mux_conf parlor_mux_mcspi4_conf[] = { 1450 #if 0 1451 { 0x158, /* 25: MCSPI4_SOMI */ 1452 MUXMODE(0) | ??? | INPUTENABLE }, 1453 { 0x156, /* 27: MCSPI4_SIMO */ 1454 MUXMODE(0) | ??? }, 1455 { 0x154, /* 29: MCSPI4_CLK */ 1456 MUXMODE(0) | ??? }, 1457 { 0x15a, /* 31: MCSPI4_CS0 */ 1458 MUXMODE(0) | ??? }, 1459 #endif 1460 { -1 } 1461 }; 1462 static const struct omap_mux_conf parlor_mux_no_mcspi4_conf[] = { 1463 { 0x158, /* 25: GPIO 153 */ 1464 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1465 { 0x156, /* 27: GPIO 152 */ 1466 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1467 { 0x154, /* 29: GPIO 151 */ 1468 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1469 { 0x15a, /* 31: GPIO 154 */ 1470 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1471 { -1 } 1472 }; 1473 1474 /* 1475 * ETH0 connects via CS5. It use GPIO 44 for IRQ. 1476 * Also GPIO 45 is NRESET. 1477 */ 1478 smsh_config(NULL, 44, 45); 1479 1480 ehci_config(); 1481 1482 gxio_omap_mux_config_address("mcspi", 0x48098000, 1483 parlor_mux_mcspi1_conf, parlor_mux_no_mcspi1_conf); 1484 gxio_omap_mux_config_address("hdq", 0x480b2000, 1485 parlor_mux_hdq_conf, parlor_mux_no_hdq_conf); 1486 gxio_omap_mux_config_address("tiiic", 0x48072000, 1487 parlor_mux_i2c2_conf, parlor_mux_no_i2c2_conf); 1488 if (gxio_omap_mux_config_address("sdhc", 0x480ad000, 1489 parlor_mux_sdmmc3_conf, NULL) != 0) 1490 gxio_omap_mux_config_address("com", 0x4806c000, 1491 parlor_mux_uart2_conf, parlor_mux_no_uart2_conf); 1492 gxio_omap_mux_config_address("mcbsp", 0x49024000, 1493 parlor_mux_bsp2_conf, parlor_mux_no_bsp2_conf); 1494 gxio_omap_mux_config_address("mcspi", 0x480ba000, 1495 parlor_mux_mcspi4_conf, parlor_mux_no_mcspi4_conf); 1496 } 1497 1498 #elif defined(PEPPER) 1499 1500 static void 1501 lcd_config(void) 1502 { 1503 static const struct tifb_panel_info panel_lcd = { 1504 .panel_tft = 1, 1505 .panel_mono = false, 1506 .panel_bpp = 24, 1507 1508 .panel_pxl_clk = 18400000, 1509 .panel_width = 480, 1510 .panel_height = 272, 1511 .panel_hfp = 8, 1512 .panel_hbp = 4, 1513 .panel_hsw = 41, 1514 .panel_vfp = 4, 1515 .panel_vbp = 2, 1516 .panel_vsw = 10, 1517 .panel_invert_hsync = 0, 1518 .panel_invert_vsync = 0, 1519 1520 .panel_ac_bias = 255, 1521 .panel_ac_bias_intrpt = 0, 1522 .panel_dma_burst_sz = 16, 1523 .panel_fdd = 0x80, 1524 .panel_sync_edge = 0, 1525 .panel_sync_ctrl = 1, 1526 .panel_tft_alt_mode = 0, 1527 .panel_invert_pxl_clk = 0, 1528 }; 1529 static const struct omap_mux_conf pepper_mux_lcd_conf[] = { 1530 /* 1531 * LCD_DATA[0-23] configures in tifb.c 1532 */ 1533 1534 { 0x8e0, MMODE(0) | PUDEN }, /* LCD_VSYNC */ 1535 { 0x8e4, MMODE(0) | PUDEN }, /* LCD_HSYNC */ 1536 { 0x8e8, MMODE(0) | PUDEN }, /* LCD_PCLK */ 1537 { 0x8ec, MMODE(0) | PUDEN }, /* LCD_AC_BIAS_EN */ 1538 1539 { 0x86c, MMODE(7) | PUTYPESEL }, /* GPIO 59: Enable */ 1540 { -1 } 1541 }; 1542 1543 if (gxio_omap_mux_config_address("tifb", 0x4830e000, 1544 pepper_mux_lcd_conf, NULL) == 0) { 1545 extern const struct tifb_panel_info *tifb_panel_info; 1546 extern bool use_tps65217_wled; 1547 1548 tifb_panel_info = &panel_lcd; 1549 use_tps65217_wled = true; 1550 } 1551 } 1552 1553 static void 1554 pepper43_config(void) 1555 { 1556 static const struct omap_mux_conf pepper43_mux_wilink8_conf[] = { 1557 /* TI WiLink 8 */ 1558 { 0x800, MMODE(7) | PUTYPESEL }, /* GPIO 32: Bluetooth */ 1559 { 0x804, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 33: irq */ 1560 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: WiFi */ 1561 { -1 } 1562 }; 1563 static const struct omap_mux_conf pepper43_mux_i2c1_conf[] = { 1564 { 0x968, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1565 { 0x96c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1566 { -1 } 1567 }; 1568 static const struct omap_mux_conf pepper43_mpu9150_conf[] = { 1569 /* MPU9150 at I2C1 */ 1570 { 0x808, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 34: IRQ */ 1571 { 0x898, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 68 */ 1572 { 0x870, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 30 */ 1573 { -1 } 1574 }; 1575 static const struct omap_mux_conf pepper43_mux_20pin_header_conf[] = { 1576 { 0x85c, MMODE(7) | PUDEN | RXACTIVE }, /* 1: GPIO 55 */ 1577 { 0x80c, MMODE(7) | PUDEN | RXACTIVE }, /* 2: GPIO 35 */ 1578 { 0x810, MMODE(7) | PUDEN | RXACTIVE }, /* 3: GPIO 36 */ 1579 { 0x814, MMODE(7) | PUDEN | RXACTIVE }, /* 4: GPIO 37 */ 1580 { 0x818, MMODE(7) | PUDEN | RXACTIVE }, /* 5: GPIO 38 */ 1581 { 0x81c, MMODE(7) | PUDEN | RXACTIVE }, /* 6: GPIO 39 */ 1582 { 0x87c, MMODE(7) | PUDEN | RXACTIVE }, /* 7: GPIO 61 */ 1583 { 0x880, MMODE(7) | PUDEN | RXACTIVE }, /* 8: GPIO 62 */ 1584 { 0x884, MMODE(7) | PUDEN | RXACTIVE }, /* 9: GPIO 63 */ 1585 { 0x9e4, MMODE(7) | PUDEN | RXACTIVE }, /* 10: GPIO 103 */ 1586 { 0x9e8, MMODE(7) | PUDEN | RXACTIVE }, /* 11: GPIO 104 */ 1587 { 0x9b0, MMODE(7) | PUDEN | RXACTIVE }, /* 12: GPIO 19 */ 1588 #if 0 /* UART3 or GPIO */ 1589 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* 13: GPIO 7 */ 1590 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* 14: GPIO 6 */ 1591 #endif 1592 #if 0 /* UART2 or GPIO */ 1593 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* 15: GPIO 98 */ 1594 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* 16: GPIO 97 */ 1595 #endif 1596 /* 17: VCC 5v */ 1597 /* 18: VCC 3.3v */ 1598 /* 19: GND */ 1599 /* 20: GND */ 1600 { -1 } 1601 }; 1602 static const struct omap_mux_conf pepper43_mux_uart2_conf[] = { 1603 { 0x90c, MMODE(6) | PUTYPESEL | RXACTIVE }, /* UART2_RXD */ 1604 { 0x910, MMODE(6) | PUDEN }, /* UART2_TXD */ 1605 { -1 } 1606 }; 1607 static const struct omap_mux_conf pepper43_mux_no_uart2_conf[] = { 1608 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 97 */ 1609 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 98 */ 1610 { -1 } 1611 }; 1612 static const struct omap_mux_conf pepper43_mux_uart3_conf[] = { 1613 { 0x960, MMODE(1) | PUTYPESEL | RXACTIVE }, /* UART3_RXD */ 1614 { 0x964, MMODE(1) | PUDEN }, /* UART3_TXD */ 1615 { -1 } 1616 }; 1617 static const struct omap_mux_conf pepper43_mux_no_uart3_conf[] = { 1618 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 6 */ 1619 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 7 */ 1620 { -1 } 1621 }; 1622 1623 static const struct omap_mux_conf *pepper43_mux_conf[] = { 1624 pepper43_mux_wilink8_conf, 1625 pepper43_mux_i2c1_conf, 1626 pepper43_mpu9150_conf, 1627 pepper43_mux_20pin_header_conf, 1628 }; 1629 1630 static const struct omap_gpio_conf pepper43_gpio_wl18xx_conf[] = { 1631 { 32, conf_output_0 }, /* #Reset: Bluetooth */ 1632 { 56, conf_output_0 }, /* #Reset: WiFi */ 1633 { -1 } 1634 }; 1635 int i; 1636 1637 lcd_config(); 1638 1639 for (i = 0; i < __arraycount(pepper43_mux_conf); i++) 1640 gxio_omap_mux_config(pepper43_mux_conf[i]); 1641 gxio_omap_gpio_config(pepper43_gpio_wl18xx_conf); 1642 1643 #if 0 1644 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 52 (Blue) */ 1645 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 20)); 1646 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1647 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 20)); 1648 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 53 (Red) */ 1649 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 21)); 1650 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1651 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 21)); 1652 #endif 1653 1654 gxio_omap_mux_config_address("com", 0x48024000, 1655 pepper43_mux_uart2_conf, pepper43_mux_no_uart2_conf); 1656 gxio_omap_mux_config_address("com", 0x481a6000, 1657 pepper43_mux_uart3_conf, pepper43_mux_no_uart3_conf); 1658 } 1659 1660 static void 1661 pepper_config(void) 1662 { 1663 static const struct omap_mux_conf pepper_mux_button2_conf[] = { 1664 { 0x85c, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 55 */ 1665 { -1 } 1666 }; 1667 static const struct omap_mux_conf pepper_mux_i2c1_conf[] = { 1668 { 0x90c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1669 { 0x910, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1670 { -1 } 1671 }; 1672 static const struct omap_mux_conf pepper_mux_wi2wi_conf[] = { 1673 { 0x9b4, MMODE(3) | PUDEN }, /* CLKOUT2 */ 1674 /* Wi2Wi */ 1675 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: nReset */ 1676 { 0x870, MMODE(7) | PUTYPESEL }, /* GPIO 30: nPower */ 1677 { -1 } 1678 }; 1679 static const struct omap_mux_conf pepper_mux_uart1_conf[] = { 1680 { 0x978, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_CTSn */ 1681 { 0x97c, MMODE(0) }, /* UART1_RTSn */ 1682 { 0x980, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_RXD */ 1683 { 0x984, MMODE(0) }, /* UART1_TXD */ 1684 { -1 } 1685 }; 1686 static const struct omap_mux_conf pepper_mux_no_uart1_conf[] = { 1687 { 0x978, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 12 */ 1688 { 0x97c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 13 */ 1689 { 0x980, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 14 */ 1690 { 0x984, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 15 */ 1691 { -1 } 1692 }; 1693 static const struct omap_mux_conf *pepper_mux_conf[] = { 1694 pepper_mux_button2_conf, 1695 pepper_mux_i2c1_conf, 1696 pepper_mux_wi2wi_conf, 1697 }; 1698 1699 int i; 1700 1701 lcd_config(); 1702 1703 for (i = 0; i < __arraycount(pepper_mux_conf); i++) 1704 gxio_omap_mux_config(pepper_mux_conf[i]); 1705 gxio_omap_mux_config_address("com", 0x48022000, 1706 pepper_mux_uart1_conf, pepper_mux_no_uart1_conf); 1707 } 1708 1709 static void 1710 c_config(void) 1711 { 1712 static const struct omap_mux_conf pepper43c_mux_ft5306_conf[] = { 1713 /* FT5306 at I2C2 */ 1714 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20 */ 1715 { 0x95c, MMODE(7) | PUDEN }, /* GPIO 5 */ 1716 { -1 } 1717 }; 1718 static const struct omap_mux_conf pepper43c_mux_i2c2_conf[] = { 1719 { 0x950, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SDA */ 1720 { 0x954, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SCL */ 1721 { -1 } 1722 }; 1723 static const struct omap_mux_conf *pepper43c_mux_conf[] = { 1724 pepper43c_mux_ft5306_conf, 1725 pepper43c_mux_i2c2_conf, 1726 }; 1727 1728 static const struct omap_gpio_conf pepper43c_gpio_ft5306_conf[] = { 1729 { 5, conf_output_0 }, /* #Reset */ 1730 { -1 } 1731 }; 1732 int i; 1733 1734 pepper43_config(); 1735 1736 for (i = 0; i < __arraycount(pepper43c_mux_conf); i++) 1737 gxio_omap_mux_config(pepper43c_mux_conf[i]); 1738 gxio_omap_gpio_config(pepper43c_gpio_ft5306_conf); 1739 } 1740 1741 static void 1742 dvi_config(void) 1743 { 1744 /* XXXX: hmm... mismatch found in Linux's dts and pubs.gumstix.org... */ 1745 1746 extern struct cfdata cfdata[]; 1747 extern const struct tifb_panel_info *tifb_panel_info; 1748 1749 static const struct tifb_panel_info panel_dvi = { 1750 .panel_tft = 1, 1751 .panel_mono = false, 1752 .panel_bpp = 16, 1753 1754 .panel_pxl_clk = 63500000, 1755 .panel_width = 1024, 1756 .panel_height = 768, 1757 .panel_hfp = 8, 1758 .panel_hbp = 4, 1759 .panel_hsw = 41, 1760 .panel_vfp = 4, 1761 .panel_vbp = 2, 1762 .panel_vsw = 10, 1763 .panel_invert_hsync = 0, 1764 .panel_invert_vsync = 0, 1765 1766 .panel_ac_bias = 255, 1767 .panel_ac_bias_intrpt = 0, 1768 .panel_dma_burst_sz = 16, 1769 .panel_fdd = 0x80, 1770 .panel_sync_edge = 0, 1771 .panel_sync_ctrl = 1, 1772 .panel_invert_pxl_clk = 0, 1773 }; 1774 cfdata_t cf = &cfdata[0]; 1775 1776 /* Disable wireless module. */ 1777 while (cf->cf_name != NULL) { 1778 if (strcmp(cf->cf_name, "sdhc") == 0 && 1779 strcmp(cf->cf_atname, "mainbus") == 0 && 1780 cf->cf_loc[MAINBUSCF_BASE] == 0x47810000) { 1781 if (cf->cf_fstate == FSTATE_NOTFOUND) 1782 cf->cf_fstate = FSTATE_DNOTFOUND; 1783 else if (cf->cf_fstate == FSTATE_STAR) 1784 cf->cf_fstate = FSTATE_DSTAR; 1785 } 1786 cf++; 1787 } 1788 1789 tifb_panel_info = &panel_dvi; 1790 } 1791 1792 static void 1793 r_config(void) 1794 { 1795 static const struct omap_mux_conf pepper43r_mux_ads7846_conf[] = { 1796 /* ADS7846 at McSPI0 */ 1797 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20: IRQ */ 1798 { -1 } 1799 }; 1800 static const struct omap_mux_conf pepper43r_mux_spi0_conf[] = { 1801 { 0x950, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_SCLK */ 1802 { 0x954, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D0 */ 1803 { 0x958, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D1 */ 1804 { 0x95c, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_CS0 */ 1805 { -1 } 1806 }; 1807 static const struct omap_mux_conf *pepper43r_mux_conf[] = { 1808 pepper43r_mux_ads7846_conf, 1809 pepper43r_mux_spi0_conf, 1810 }; 1811 int i; 1812 1813 pepper43_config(); 1814 1815 for (i = 0; i < __arraycount(pepper43r_mux_conf); i++) 1816 gxio_omap_mux_config(pepper43r_mux_conf[i]); 1817 } 1818 1819 #endif 1820 1821 #if defined(OVERO) || defined(DUOVERO) 1822 static void 1823 smsh_config(struct omap_mux_conf *smsh_mux_conf, int intr, int nreset) 1824 { 1825 struct omap_gpio_conf smsh_gpio_conf[] = { 1826 { intr, conf_input }, 1827 { nreset, conf_output_0 }, 1828 { -1 } 1829 }; 1830 1831 /* 1832 * Basically use current settings by U-Boot. 1833 * However remap physical address to configured address. 1834 */ 1835 1836 if (smsh_mux_conf != NULL) 1837 gxio_omap_mux_config(smsh_mux_conf); 1838 gxio_omap_gpio_config(smsh_gpio_conf); 1839 __udelay(100000); 1840 gxio_omap_gpio_write(nreset, 1); 1841 } 1842 #endif 1843 1844 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1845 /* 1846 * The delay for configuration time. 1847 * This function use initialized timer by U-Boot. 1848 */ 1849 static void 1850 __udelay(unsigned int usec) 1851 { 1852 #if defined(OVERO) || defined(DUOVERO) 1853 #define V_SCLK (26000000 >> 1) 1854 #define TCRR 0x28 1855 #elif defined(PEPPER) 1856 #define V_SCLK 24000000 1857 #define TCRR 0x3c 1858 #endif 1859 #define SYS_PTV 2 1860 #define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV)) 1861 1862 const vaddr_t timer_base = 1863 #if defined(OVERO) 1864 OVERO_L4_PERIPHERAL_VBASE + 0x32000; 1865 #elif defined(DUOVERO) 1866 DUOVERO_L4_PERIPHERAL_VBASE + 0x32000; 1867 #elif defined(PEPPER) 1868 PEPPER_L4_PERIPHERAL_VBASE + 0x40000; 1869 #endif 1870 long timo = usec * (TIMER_CLOCK / 1000) / 1000; 1871 uint32_t now, last; 1872 1873 last = ioreg_read(timer_base + TCRR); 1874 while (timo > 0) { 1875 now = ioreg_read(timer_base + TCRR); 1876 if (last > now) 1877 timo -= __BITS(0, 31) - last + now + 1; 1878 else 1879 timo -= now - last; 1880 last = now; 1881 } 1882 } 1883 #endif 1884 1885 #if defined(PEPPER) 1886 static int 1887 read_i2c_device(const vaddr_t i2c_base, uint16_t sa, uint8_t addr, int len, 1888 uint8_t *buf) 1889 { 1890 uint16_t v; 1891 int aok = 0, cnt = 0; 1892 1893 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1894 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1895 while (v & I2C_IRQSTATUS_BB) { 1896 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, v); 1897 __udelay(20); 1898 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1899 } 1900 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1901 1902 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1903 ioreg16_write(i2c_base + OMAP2_I2C_CNT, sizeof(addr)); 1904 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1905 I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STP | I2C_CON_STT); 1906 while (1 /*CONSTCOND*/) { 1907 __udelay(20); 1908 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1909 if ((v & I2C_IRQSTATUS_XRDY) && aok == 0) { 1910 aok = 1; 1911 ioreg16_write(i2c_base + OMAP2_I2C_DATA, addr); 1912 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1913 I2C_IRQSTATUS_XRDY); 1914 } 1915 if (v & I2C_IRQSTATUS_ARDY) { 1916 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1917 I2C_IRQSTATUS_ARDY); 1918 break; 1919 } 1920 } 1921 1922 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1923 ioreg16_write(i2c_base + OMAP2_I2C_CNT, len); 1924 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1925 I2C_CON_EN | I2C_CON_MST | I2C_CON_STP | I2C_CON_STT); 1926 while (1 /*CONSTCOND*/) { 1927 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1928 if (v & I2C_IRQSTATUS_RRDY && 1929 cnt < len) { 1930 buf[cnt++] = ioreg16_read(i2c_base + OMAP2_I2C_DATA); 1931 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1932 I2C_IRQSTATUS_RRDY); 1933 } 1934 if (v & I2C_IRQSTATUS_ARDY) { 1935 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1936 I2C_IRQSTATUS_ARDY); 1937 break; 1938 } 1939 } 1940 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1941 return 0; 1942 } 1943 #endif 1944
Indexes created Tue Oct 28 12:10:06 GMT 2025