gxio.c revision 1.26.16.1
1 /* $NetBSD: gxio.c,v 1.26.16.1 2021/03/20 19:33:33 thorpej Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: gxio.c,v 1.26.16.1 2021/03/20 19:33:33 thorpej Exp $"); 35 36 #include "opt_cputypes.h" 37 #include "opt_gumstix.h" 38 #include "opt_gxio.h" 39 #if defined(OVERO) 40 #include "opt_omap.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/device.h> 45 #include <sys/errno.h> 46 #include <sys/kernel.h> 47 48 #include <sys/systm.h> 49 50 #include <machine/bootconfig.h> 51 52 #include <arm/omap/omap2_gpmcreg.h> 53 #if defined(OMAP2) 54 #include <arm/omap/omap2_reg.h> 55 #if defined(OMAP3530) 56 #include <arm/omap/omap2_intr.h> 57 #endif 58 #endif 59 #include <arm/omap/omap_var.h> 60 #include <arm/omap/ti_iicreg.h> 61 #include <arm/omap/tifbvar.h> 62 #if defined(CPU_XSCALE) 63 #include <arm/xscale/pxa2x0cpu.h> 64 #endif 65 #include <arm/xscale/pxa2x0reg.h> 66 #include <arm/xscale/pxa2x0var.h> 67 #include <arm/xscale/pxa2x0_gpio.h> 68 #include <evbarm/gumstix/gumstixreg.h> 69 #include <evbarm/gumstix/gumstixvar.h> 70 71 #include "ioconf.h" 72 #include "locators.h" 73 74 75 struct gxioconf { 76 const char *name; 77 void (*config)(void); 78 }; 79 80 #if defined(GUMSTIX) 81 static int gxiomatch(device_t, cfdata_t, void *); 82 static void gxioattach(device_t, device_t, void *); 83 static int gxiosearch(device_t, cfdata_t, const int *, void *); 84 static int gxioprint(void *, const char *); 85 86 CFATTACH_DECL_NEW(gxio, sizeof(struct gxio_softc), 87 gxiomatch, gxioattach, NULL, NULL); 88 #endif 89 90 void gxio_config(void); 91 void gxio_config_expansion(const char *); 92 #if defined(GUMSTIX) 93 static void basix_config(void); 94 static void cfstix_config(void); 95 static void etherstix_config(void); 96 static void netcf_config(void); 97 static void netcf_vx_config(void); 98 static void netduommc_config(void); 99 static void netduo_config(void); 100 static void netmicrosd_config(void); 101 static void netwifimicrosd_config(void); 102 static void netmmc_config(void); 103 static void wifistix_config(void); 104 static void wifistix_cf_config(void); 105 #elif defined(OVERO) 106 static void eth0_config(void); 107 static void eth1_config(void); 108 static void dvi_config(void); 109 static void lcd_config(char); 110 static void header_40pin_config(int); 111 112 static void chestnut_config(void); 113 static void gallop_config(void); 114 static void summit_config(void); 115 static void tobi_config(void); 116 static void tobiduo_config(void); 117 #elif defined(DUOVERO) 118 static void ehci_config(void); 119 120 static void parlor_config(void); 121 #elif defined(PEPPER) 122 static void lcd_config(void); 123 static void pepper43_config(void); 124 125 static void pepper_config(void); 126 static void c_config(void); 127 static void dvi_config(void); 128 static void r_config(void); 129 #endif 130 #if defined(OVERO) || defined(DUOVERO) 131 struct omap_mux_conf; 132 static void smsh_config(struct omap_mux_conf *, int, int); 133 #endif 134 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 135 static void __udelay(unsigned int); 136 #endif 137 #if defined(PEPPER) 138 static int read_i2c_device(const vaddr_t, uint16_t, uint8_t, int, uint8_t *); 139 #endif 140 141 #if defined(CPU_XSCALE_PXA250) 142 143 static struct pxa2x0_gpioconf pxa255dep_gpioconf[] = { 144 /* Bluetooth module configuration */ 145 { 7, GPIO_OUT | GPIO_SET }, /* power on */ 146 { 12, GPIO_ALT_FN_1_OUT }, /* 32kHz out. required by SingleStone */ 147 148 /* AC97 configuration */ 149 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 150 151 /* FFUART configuration */ 152 { 35, GPIO_ALT_FN_1_IN }, /* CTS */ 153 { 41, GPIO_ALT_FN_2_OUT }, /* RTS */ 154 155 #ifndef GXIO_BLUETOOTH_ON_HWUART 156 /* BTUART configuration */ 157 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 158 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 159 #else 160 /* HWUART configuration */ 161 { 42, GPIO_ALT_FN_3_IN }, /* HWRXD */ 162 { 43, GPIO_ALT_FN_3_OUT }, /* HWTXD */ 163 { 44, GPIO_ALT_FN_3_IN }, /* HWCTS */ 164 { 45, GPIO_ALT_FN_3_OUT }, /* HWRTS */ 165 #endif 166 167 #ifndef GXIO_BLUETOOTH_ON_HWUART 168 /* HWUART configuration */ 169 { 48, GPIO_ALT_FN_1_OUT }, /* HWTXD */ 170 { 49, GPIO_ALT_FN_1_IN }, /* HWRXD */ 171 { 50, GPIO_ALT_FN_1_IN }, /* HWCTS */ 172 { 51, GPIO_ALT_FN_1_OUT }, /* HWRTS */ 173 #endif 174 175 { -1 } 176 }; 177 #endif 178 #if defined(CPU_XSCALE_PXA270) 179 static struct pxa2x0_gpioconf verdexdep_gpioconf[] = { 180 /* Bluetooth module configuration */ 181 { 9, GPIO_ALT_FN_3_OUT }, /* CHOUT<0> */ 182 { 12, GPIO_OUT | GPIO_SET }, 183 184 /* LCD configuration */ 185 { 17, GPIO_IN }, /* backlight on */ 186 187 /* FFUART configuration */ 188 { 34, GPIO_ALT_FN_1_IN }, /* FFRXD */ 189 { 39, GPIO_ALT_FN_2_OUT }, /* FFTXD */ 190 191 /* BTUART configuration */ 192 { 42, GPIO_ALT_FN_1_IN }, /* BTRXD */ 193 { 43, GPIO_ALT_FN_2_OUT }, /* BTTXD */ 194 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 195 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 196 197 /* AC97 configuration */ 198 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 199 200 { -1 } 201 }; 202 203 #elif defined(OMAP2) 204 205 struct omap_mux_conf { 206 int offset; 207 uint32_t value; 208 /* OMAP3/4 register values */ 209 #define WAKEUPEVENT (1 << 15) 210 #define WAKEUPENABLE (1 << 14) 211 #define OFFMODEPULLTYPESELECT (1 << 13) 212 #define OFFMODEPULLUDENABLE (1 << 12) 213 #define OFFMODEOUTVALUE (1 << 11) 214 #define OFFMODEOUTENABLE (1 << 10) 215 #define OFFMODEENABLE (1 << 9) 216 #define INPUTENABLE (1 << 8) 217 #define PULLTYPESELECT (1 << 4) 218 #define PULLUDENABLE (1 << 3) 219 #define MUXMODE(n) ((n) & 0x7) 220 221 /* Sitara AM3xxx register values */ 222 #define SLEWCTRL (1 << 6) 223 #define RXACTIVE (1 << 5) 224 #define PUTYPESEL (1 << 4) 225 #define PUDEN (1 << 3) 226 #define MMODE(n) ((n) & 0x7) 227 }; 228 struct omap_gpio_conf { 229 int pin; 230 enum { 231 conf_input = -1, 232 conf_output_0, 233 conf_output_1, 234 } conf; 235 }; 236 237 static void gxio_omap_mux_config(const struct omap_mux_conf []); 238 static int gxio_omap_mux_config_address(const char *, unsigned long, 239 const struct omap_mux_conf[], 240 const struct omap_mux_conf[]); 241 static void gxio_omap_gpio_config(const struct omap_gpio_conf[]); 242 void gxio_omap_gpio_write(int, int); 243 244 #if defined(OVERO) 245 static const struct omap_mux_conf overo_mux_i2c3_conf[] = { 246 { 0x1c2, MUXMODE(0) | INPUTENABLE }, /* i2c3_scl */ 247 { 0x1c4, MUXMODE(0) | INPUTENABLE }, /* i2c3_sda */ 248 { -1 } 249 }; 250 #endif 251 #if defined(OVERO) 252 static const struct omap_mux_conf overo_mux_mmchs2_conf[] = { 253 { 0x158, /* mmc2_clk */ 254 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 255 { 0x15a, /* mmc2_cmd */ 256 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 257 { 0x15c, /* mmc2_dat0 */ 258 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 259 { 0x15e, /* mmc2_dat1 */ 260 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 261 { 0x160, /* mmc2_dat2 */ 262 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 263 { 0x162, /* mmc2_dat3 */ 264 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 265 { -1 } 266 }; 267 #endif 268 #if defined(OVERO) 269 static const struct omap_mux_conf overo_mux_wireless_conf[] = { 270 { 0x0b4, MUXMODE(4) }, /* gpio_54:BT_nPOWERON*/ 271 { 0x0bc, MUXMODE(4) | INPUTENABLE }, /* gpio_58: WIFI_IRQ */ 272 { 0x19c, MUXMODE(4) }, /* gpio_164:BT_nRESET */ 273 { 0x5e0, MUXMODE(4) }, /* gpio_16: W2W_nRESET*/ 274 { -1 } 275 }; 276 277 #elif defined(DUOVERO) 278 static const struct omap_mux_conf duovero_mux_led_conf[] = { 279 { 0x116, MUXMODE(3) }, /* GPIO 122 */ 280 { -1 } 281 }; 282 static const struct omap_mux_conf duovero_mux_button_conf[] = { 283 { 0x114, /* GPIO 121 */ 284 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 285 { -1 } 286 }; 287 288 #elif defined(PEPPER) 289 static const struct omap_mux_conf pepper_mux_led_conf[] = { 290 { 0x850, MMODE(7) | PUDEN }, /* GPIO 52: Blue */ 291 { 0x854, MMODE(7) | PUDEN }, /* GPIO 53: Red */ 292 { -1 } 293 }; 294 static const struct omap_mux_conf pepper_mux_button_conf[] = { 295 { 0x858, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 54 */ 296 { -1 } 297 }; 298 static const struct omap_mux_conf pepper_mux_mmchs3_conf[] = { 299 { 0x844, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT0 */ 300 { 0x848, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT1 */ 301 { 0x84c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT2 */ 302 { 0x878, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT3 */ 303 { 0x888, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CMD */ 304 { 0x88c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CLK */ 305 { -1 } 306 }; 307 static const struct omap_mux_conf pepper_mux_audio_codec_conf[] = { 308 { 0x840, MMODE(7) | PUDEN }, /* GPIO 48: #Reset */ 309 { -1 } 310 }; 311 #endif 312 313 #endif 314 315 static const struct gxioconf gxioconflist[] = { 316 #if defined(GUMSTIX) 317 { "basix", basix_config }, 318 { "cfstix", cfstix_config }, 319 { "etherstix", etherstix_config }, 320 { "netcf", netcf_config }, 321 { "netcf-vx", netcf_vx_config }, 322 { "netduo-mmc", netduommc_config }, 323 { "netduo", netduo_config }, 324 { "netmicrosd", netmicrosd_config }, 325 { "netmicrosd-vx", netmicrosd_config }, 326 { "netwifimicrosd", netwifimicrosd_config }, 327 { "netmmc", netmmc_config }, 328 { "netpro-vx", netwifimicrosd_config }, 329 { "wifistix-cf", wifistix_cf_config }, 330 { "wifistix", wifistix_config }, 331 #elif defined(OVERO) 332 { "chestnut43", chestnut_config }, 333 { "gallop43", gallop_config }, 334 { "summit", summit_config }, 335 { "tobi", tobi_config }, 336 { "tobi-duo", tobiduo_config }, 337 #elif defined(DUOVERO) 338 { "parlor", parlor_config }, 339 #elif defined(PEPPER) 340 { "43c", c_config }, 341 { "43r", r_config }, 342 { "dvi", dvi_config }, 343 #endif 344 { NULL } 345 }; 346 347 int gxpcic_gpio_reset; 348 struct gxpcic_slot_irqs gxpcic_slot_irqs[2] = { { 0, -1, -1 }, { 0, -1, -1 } }; 349 350 351 #if defined(GUMSTIX) 352 /* ARGSUSED */ 353 static int 354 gxiomatch(device_t parent, cfdata_t match, void *aux) 355 { 356 357 struct pxaip_attach_args *pxa = aux; 358 bus_space_tag_t iot = &pxa2x0_bs_tag; 359 bus_space_handle_t ioh; 360 361 if (strcmp(pxa->pxa_name, match->cf_name) != 0 || 362 pxa->pxa_addr != PXAIPCF_ADDR_DEFAULT) 363 return 0; 364 365 if (bus_space_map(iot, 366 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &ioh)) 367 return 0; 368 bus_space_unmap(iot, ioh, PXA2X0_MEMCTL_SIZE); 369 370 /* nothing */ 371 return 1; 372 } 373 374 /* ARGSUSED */ 375 static void 376 gxioattach(device_t parent, device_t self, void *aux) 377 { 378 struct gxio_softc *sc = device_private(self); 379 380 aprint_normal("\n"); 381 aprint_naive("\n"); 382 383 sc->sc_dev = self; 384 sc->sc_iot = &pxa2x0_bs_tag; 385 386 if (bus_space_map(sc->sc_iot, 387 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &sc->sc_ioh)) 388 return; 389 390 /* 391 * Attach each gumstix(busheader)/overo expansion board devices. 392 */ 393 config_search(self, NULL, 394 CFARG_SUBMATCH, gxiosearch, 395 CFARG_IATTR, "gxio", 396 CFARG_EOL); 397 } 398 399 /* ARGSUSED */ 400 static int 401 gxiosearch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 402 { 403 struct gxio_softc *sc = device_private(parent); 404 struct gxio_attach_args gxa; 405 406 gxa.gxa_sc = sc; 407 gxa.gxa_iot = sc->sc_iot; 408 gxa.gxa_addr = cf->cf_loc[GXIOCF_ADDR]; 409 gxa.gxa_gpirq = cf->cf_loc[GXIOCF_GPIRQ]; 410 411 if (config_match(parent, cf, &gxa)) 412 config_attach(parent, cf, &gxa, gxioprint); 413 414 return 0; 415 } 416 417 /* ARGSUSED */ 418 static int 419 gxioprint(void *aux, const char *name) 420 { 421 struct gxio_attach_args *gxa = (struct gxio_attach_args *)aux; 422 423 if (gxa->gxa_addr != GXIOCF_ADDR_DEFAULT) 424 printf(" addr 0x%lx", gxa->gxa_addr); 425 if (gxa->gxa_gpirq > 0) 426 printf(" gpirq %d", gxa->gxa_gpirq); 427 return UNCONF; 428 } 429 #endif 430 431 432 #if defined(GUMSTIX) 433 /* 434 * configure for GPIO pin and expansion boards. 435 */ 436 void 437 gxio_config(void) 438 { 439 #if defined(CPU_XSCALE_PXA250) 440 struct pxa2x0_gpioconf *gumstix_gpioconf[] = { 441 pxa25x_com_ffuart_gpioconf, 442 pxa25x_com_stuart_gpioconf, 443 #ifndef GXIO_BLUETOOTH_ON_HWUART 444 pxa25x_com_btuart_gpioconf, 445 #endif 446 pxa25x_com_hwuart_gpioconf, 447 pxa25x_i2c_gpioconf, 448 pxa25x_pxaacu_gpioconf, 449 pxa255dep_gpioconf, 450 NULL 451 }; 452 #endif 453 #if defined(CPU_XSCALE_PXA270) 454 struct pxa2x0_gpioconf *verdex_gpioconf[] = { 455 pxa27x_com_ffuart_gpioconf, 456 pxa27x_com_stuart_gpioconf, 457 pxa27x_com_btuart_gpioconf, 458 pxa27x_i2c_gpioconf, 459 pxa27x_pxaacu_gpioconf, 460 pxa27x_pxamci_gpioconf, 461 pxa27x_ohci_gpioconf, 462 verdexdep_gpioconf, 463 NULL 464 }; 465 #endif 466 467 /* XXX: turn off for power of bluetooth module */ 468 #if defined(CPU_XSCALE_PXA250) 469 pxa2x0_gpio_set_function(7, GPIO_OUT | GPIO_CLR); 470 #elif defined(CPU_XSCALE_PXA270) 471 pxa2x0_gpio_set_function(12, GPIO_OUT | GPIO_CLR); 472 #endif 473 delay(100); 474 475 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 476 pxa2x0_gpio_config( 477 (CPU_IS_PXA250) ? gumstix_gpioconf : verdex_gpioconf); 478 #elif defined(CPU_XSCALE_PXA270) || defined(CPU_XSCALE_PXA250) 479 #if defined(CPU_XSCALE_PXA270) 480 pxa2x0_gpio_config(verdex_gpioconf); 481 #else 482 pxa2x0_gpio_config(gumstix_gpioconf); 483 #endif 484 #endif 485 } 486 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 487 static void 488 gxio_omap_mux_config(const struct omap_mux_conf mux_conf[]) 489 { 490 #if defined(OVERO) 491 const vaddr_t ctrlmod_base = OVERO_L4_CORE_VBASE + 0x2000; 492 #elif defined(DUOVERO) 493 const vaddr_t ctrlmod_base = DUOVERO_L4_CM_VBASE; 494 #elif defined(PEPPER) 495 const vaddr_t ctrlmod_base = PEPPER_PRCM_VBASE + 0x10000; 496 #endif 497 int i; 498 499 for (i = 0; mux_conf[i].offset != -1; i++) 500 #if !defined(TI_AM335X) 501 ioreg16_write(ctrlmod_base + mux_conf[i].offset, 502 mux_conf[i].value); 503 #else 504 ioreg_write(ctrlmod_base + mux_conf[i].offset, 505 mux_conf[i].value); 506 #endif 507 } 508 509 static int 510 gxio_omap_mux_config_address(const char *name, unsigned long address, 511 const struct omap_mux_conf mux_conf[], 512 const struct omap_mux_conf not_mux_conf[]) 513 { 514 extern struct cfdata cfdata[]; 515 cfdata_t cf = &cfdata[0]; 516 517 while (cf->cf_name != NULL) { 518 if (strcmp(name, cf->cf_name) == 0 && 519 address == cf->cf_loc[OBIOCF_ADDR]) { 520 gxio_omap_mux_config(mux_conf); 521 return 0; 522 } 523 cf++; 524 } 525 526 if (not_mux_conf == NULL) 527 return -1; 528 529 gxio_omap_mux_config(not_mux_conf); 530 return 0; 531 } 532 533 #if defined(OVERO) 534 #define gpio_reg_read ioreg_read 535 #define gpio_reg_write ioreg_write 536 #elif defined(DUOVERO) || defined(PEPPER) 537 #define gpio_reg_read(a) ioreg_read((a) + GPIO_SIZE2) 538 #define gpio_reg_write(a, v) ioreg_write((a) + GPIO_SIZE2, (v)) 539 #endif 540 541 static const vaddr_t gpio_bases[] = { 542 #if defined(OVERO) 543 #define OVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 544 #define GPIO(n) GPIO ## n ## _BASE_3530 545 #define BASE(a, n) \ 546 (OVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP3530_L4_ ## a ## _BASE)) 547 548 GPIO1_BASE_3530, 549 GPIO2_BASE_3530, 550 GPIO3_BASE_3530, 551 GPIO4_BASE_3530, 552 GPIO5_BASE_3530, 553 GPIO6_BASE_3530, 554 555 #elif defined(DUOVERO) 556 #define DUOVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 557 #define GPIO(n) GPIO ## n ## _BASE_4430 558 #define BASE(a, n) \ 559 (DUOVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP4430_L4_ ## a ## _BASE)) 560 561 DUOVERO_GPIO_VBASE(1), 562 DUOVERO_GPIO_VBASE(2), 563 DUOVERO_GPIO_VBASE(3), 564 DUOVERO_GPIO_VBASE(4), 565 DUOVERO_GPIO_VBASE(5), 566 567 #elif defined(PEPPER) 568 #define PEPPER_GPIO_VBASE(n) ((n) == 0 ? WAKEUP(n) : PERIPHERAL(n)) 569 #define GPIO(n) GPIO ## n ## _BASE_TI_AM335X 570 #define WAKEUP(n) (PEPPER_PRCM_VBASE + (GPIO(n) - OMAP2_CM_BASE)) 571 #define PERIPHERAL(n) \ 572 (PEPPER_L4_PERIPHERAL_VBASE + (GPIO(n) - TI_AM335X_L4_PERIPHERAL_BASE)) 573 574 PEPPER_GPIO_VBASE(0), 575 PEPPER_GPIO_VBASE(1), 576 PEPPER_GPIO_VBASE(2), 577 PEPPER_GPIO_VBASE(3), 578 #endif 579 }; 580 581 static void 582 gxio_omap_gpio_config(const struct omap_gpio_conf gpio_conf[]) 583 { 584 vaddr_t gpio_base; 585 int mask, i; 586 587 for (i = 0; gpio_conf[i].pin != -1; i++) { 588 gpio_base = gpio_bases[gpio_conf[i].pin / 32]; 589 mask = 1 << (gpio_conf[i].pin % 32); 590 switch (gpio_conf[i].conf) { 591 case conf_input: 592 ioreg_write(gpio_base + GPIO_OE, 593 ioreg_read(gpio_base + GPIO_OE) | mask); 594 break; 595 case conf_output_0: 596 ioreg_write(gpio_base + GPIO_OE, 597 ioreg_read(gpio_base + GPIO_OE) | ~mask); 598 #if 0 599 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 600 #else 601 ioreg_write(gpio_base + GPIO_DATAOUT, 602 ioreg_read(gpio_base + GPIO_DATAOUT) & ~mask); 603 #endif 604 break; 605 case conf_output_1: 606 ioreg_write(gpio_base + GPIO_OE, 607 ioreg_read(gpio_base + GPIO_OE) | ~mask); 608 #if 0 609 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 610 #else 611 ioreg_write(gpio_base + GPIO_DATAOUT, 612 ioreg_read(gpio_base + GPIO_DATAOUT) | mask); 613 #endif 614 break; 615 } 616 } 617 } 618 619 void 620 gxio_omap_gpio_write(int pin, int val) 621 { 622 vaddr_t gpio_base; 623 int mask; 624 625 KASSERT(pin / 32 < __arraycount(gpio_bases)); 626 627 gpio_base = gpio_bases[pin / 32]; 628 mask = 1 << (pin % 32); 629 if (val == 0) 630 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 631 else 632 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 633 } 634 635 /* 636 * configure for MUX, GPIO. 637 */ 638 void 639 gxio_config(void) 640 { 641 const struct omap_mux_conf *mux_conf[] = { 642 #if defined(OVERO) 643 overo_mux_i2c3_conf, 644 overo_mux_mmchs2_conf, 645 overo_mux_wireless_conf, 646 #elif defined(DUOVERO) 647 duovero_mux_led_conf, 648 duovero_mux_button_conf, 649 #elif defined(PEPPER) 650 pepper_mux_led_conf, 651 pepper_mux_button_conf, 652 pepper_mux_mmchs3_conf, 653 pepper_mux_audio_codec_conf, 654 #endif 655 }; 656 const struct omap_gpio_conf gpio_conf[] = { 657 #if defined(OVERO) 658 { 16, conf_output_0 }, /* Wireless: #Reset */ 659 #elif defined(PEPPER) 660 { 48, conf_output_0 }, /* Audio Codec: #Reset */ 661 #endif 662 { -1 } 663 }; 664 int i; 665 666 for (i = 0; i < __arraycount(mux_conf); i++) 667 gxio_omap_mux_config(mux_conf[i]); 668 gxio_omap_gpio_config(gpio_conf); 669 } 670 #endif 671 672 static int 673 gxio_find_default_expansion(void) 674 { 675 #ifdef GXIO_DEFAULT_EXPANSION 676 int i; 677 678 /* Find out the default expansion */ 679 for (i = 0; gxioconflist[i].name != NULL; i++) 680 if (strncasecmp(gxioconflist[i].name, GXIO_DEFAULT_EXPANSION, 681 strlen(gxioconflist[i].name) + 1) == 0) 682 break; 683 return gxioconflist[i].name == NULL ? -1 : i; 684 #else 685 return -1; 686 #endif 687 } 688 689 void 690 gxio_config_expansion(const char *expansion) 691 { 692 int i, d; 693 694 d = gxio_find_default_expansion(); 695 696 /* Print information about expansions */ 697 printf("supported expansions:\n"); 698 for (i = 0; gxioconflist[i].name != NULL; i++) 699 printf(" %s%s\n", gxioconflist[i].name, 700 i == d ? " (DEFAULT)" : ""); 701 702 703 if (expansion == NULL) { 704 printf("not specified 'expansion=' in the boot args.\n"); 705 i = -1; 706 } else { 707 for (i = 0; gxioconflist[i].name != NULL; i++) 708 if (strncasecmp(gxioconflist[i].name, expansion, 709 strlen(gxioconflist[i].name) + 1) == 0) 710 break; 711 if (gxioconflist[i].name == NULL) { 712 printf("unknown expansion specified: %s\n", expansion); 713 i = -1; 714 } 715 } 716 717 /* Do some magic stuff for PEPPER */ 718 #if defined(PEPPER) 719 if (i < 0) { 720 struct pepper_board_id { 721 unsigned int device_vendor; 722 #define GUMSTIX_PEPPER 0x30000200 /* 1st gen */ 723 #define GUMSTIX_PEPPER_DVI 0x31000200 /* DVI and newer */ 724 unsigned char revision; 725 unsigned char content; 726 char fab_revision[8]; 727 char env_var[16]; 728 char env_setting[64]; 729 } id; 730 const vaddr_t i2c_base = PEPPER_PRCM_VBASE + 0xb000; 731 const uint8_t eeprom = 0x50; 732 const uint8_t len = sizeof(id); 733 int rv; 734 735 rv = read_i2c_device(i2c_base, eeprom, 0x00, len, (void *)&id); 736 if (rv == 0) 737 if (id.device_vendor == GUMSTIX_PEPPER) { 738 printf("configure auto detected expansion" 739 " (pepper)\n"); 740 pepper_config(); 741 return; 742 } 743 } 744 #endif 745 746 /* 747 * Now proceed to configure the default expansion if one was 748 * specified (and found) or return. 749 */ 750 const char *toconfigure; 751 if (i < 0) { 752 #ifdef GXIO_DEFAULT_EXPANSION 753 if (d == -1) { 754 printf("default expansion (%s) not found\n", 755 GXIO_DEFAULT_EXPANSION); 756 return; 757 } 758 expansion = GXIO_DEFAULT_EXPANSION; 759 i = d; 760 toconfigure = "default"; 761 #else 762 return; 763 #endif 764 } else 765 toconfigure = "specified"; 766 767 printf("configure %s expansion (%s)\n", toconfigure, expansion); 768 gxioconflist[i].config(); 769 } 770 771 772 #if defined(GUMSTIX) 773 774 static void 775 basix_config(void) 776 { 777 778 pxa2x0_gpio_set_function(8, GPIO_ALT_FN_1_OUT); /* MMCCS0 */ 779 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_1_OUT); /* MMCCLK */ 780 #if 0 781 /* this configuration set by gxmci.c::pxamci_attach() */ 782 pxa2x0_gpio_set_function(11, GPIO_IN); /* nSD_DETECT */ 783 pxa2x0_gpio_set_function(22, GPIO_IN); /* nSD_WP */ 784 #endif 785 } 786 787 static void 788 cfstix_config(void) 789 { 790 u_int gpio, npoe_fn; 791 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 792 int bvd = (CPU_IS_PXA250) ? 4 : 111; 793 #else 794 #if defined(CPU_XSCALE_PXA270) 795 const int bvd = 111; 796 #else 797 const int bvd = 4; 798 #endif 799 #endif 800 801 if (CPU_IS_PXA250) { 802 gxpcic_slot_irqs[0].valid = 1; 803 gxpcic_slot_irqs[0].cd = 11; 804 gxpcic_slot_irqs[0].prdy = 26; 805 gxpcic_gpio_reset = 8; 806 } else { 807 gxpcic_slot_irqs[0].valid = 1; 808 gxpcic_slot_irqs[0].cd = 104; 809 gxpcic_slot_irqs[0].prdy = 96; 810 gxpcic_gpio_reset = 97; 811 } 812 813 #if 1 814 /* PCD/PRDY set by pxa2x0_pcic.c::pxapcic_attach_common() */ 815 #else 816 pxa2x0_gpio_set_function(11, GPIO_IN); /* PCD1 */ 817 pxa2x0_gpio_set_function(26, GPIO_IN); /* PRDY1/~IRQ1 */ 818 #endif 819 pxa2x0_gpio_set_function(bvd, GPIO_IN); /* BVD1/~STSCHG1 */ 820 821 for (gpio = 48, npoe_fn = 0; gpio <= 53 ; gpio++) 822 npoe_fn |= pxa2x0_gpio_get_function(gpio); 823 npoe_fn &= GPIO_SET; 824 825 pxa2x0_gpio_set_function(48, GPIO_ALT_FN_2_OUT | npoe_fn); /* nPOE */ 826 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 827 pxa2x0_gpio_set_function(50, GPIO_ALT_FN_2_OUT); /* nPIOR */ 828 pxa2x0_gpio_set_function(51, GPIO_ALT_FN_2_OUT); /* nPIOW */ 829 if (CPU_IS_PXA250) { 830 pxa2x0_gpio_set_function(52, GPIO_ALT_FN_2_OUT); /* nPCE1 */ 831 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_2_OUT); /* nPCE2 */ 832 pxa2x0_gpio_set_function(54, GPIO_ALT_FN_2_OUT); /* pSKTSEL */ 833 } else { 834 pxa2x0_gpio_set_function(102, GPIO_ALT_FN_1_OUT); /* nPCE1 */ 835 pxa2x0_gpio_set_function(105, GPIO_ALT_FN_1_OUT); /* nPCE2 */ 836 pxa2x0_gpio_set_function(79, GPIO_ALT_FN_1_OUT); /* pSKTSEL */ 837 } 838 pxa2x0_gpio_set_function(55, GPIO_ALT_FN_2_OUT); /* nPREG */ 839 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); /* nPWAIT */ 840 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); /* nIOIS16 */ 841 } 842 843 static void 844 etherstix_config(void) 845 { 846 extern struct cfdata cfdata[]; 847 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 848 int rst = (CPU_IS_PXA250) ? 80 : 32; 849 int irq = (CPU_IS_PXA250) ? 36 : 99; 850 #else 851 #if defined(CPU_XSCALE_PXA270) 852 const int rst = 32, irq = 99; 853 #else 854 const int rst = 80, irq = 36; 855 #endif 856 #endif 857 int i; 858 859 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 860 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 861 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_SET); /* RESET 1 */ 862 delay(1); 863 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_CLR); 864 delay(50000); 865 866 for (i = 0; cfdata[i].cf_name != NULL; i++) 867 if (strcmp(cfdata[i].cf_name, "sm") == 0 && 868 strcmp(cfdata[i].cf_atname, "sm_gxio") == 0 && 869 cfdata[i].cf_loc[GXIOCF_ADDR] == 0x04000300 && 870 cfdata[i].cf_loc[GXIOCF_GPIRQ] == GXIOCF_GPIRQ_DEFAULT) 871 cfdata[i].cf_loc[GXIOCF_GPIRQ] = irq; 872 } 873 874 static void 875 netcf_config(void) 876 { 877 878 etherstix_config(); 879 cfstix_config(); 880 } 881 882 static void 883 netcf_vx_config(void) 884 { 885 886 /* 887 * XXXX: More power is necessary for NIC and USB??? 888 * (no document. from Linux) 889 */ 890 891 pxa2x0_gpio_set_function(27, GPIO_IN); 892 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); 893 pxa2x0_gpio_set_function(118, GPIO_ALT_FN_1_IN | GPIO_CLR); 894 895 etherstix_config(); 896 cfstix_config(); 897 if (CPU_IS_PXA270) { 898 /* Overwrite */ 899 gxpcic_slot_irqs[0].cd = 104; 900 gxpcic_slot_irqs[0].prdy = 109; 901 gxpcic_gpio_reset = 110; 902 }; 903 } 904 905 static void 906 netduommc_config(void) 907 { 908 909 netduo_config(); 910 basix_config(); 911 } 912 913 static void 914 netduo_config(void) 915 { 916 917 etherstix_config(); 918 919 pxa2x0_gpio_set_function(78, GPIO_ALT_FN_2_OUT); /* nCS 2 */ 920 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_SET); /* RESET 2 */ 921 delay(1); 922 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_CLR); 923 delay(50000); 924 } 925 926 static void 927 netmicrosd_config(void) 928 { 929 930 /* MicroSD(mci) always configure on PXA270 */ 931 932 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 933 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 934 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); /* RESET 1 */ 935 delay(hz / 2); 936 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_SET); 937 delay(50000); 938 } 939 940 static void 941 netwifimicrosd_config(void) 942 { 943 944 netmicrosd_config(); 945 946 cfstix_config(); 947 /* However use pxamci. */ 948 pxa2x0_gpio_set_function(111, GPIO_CLR | GPIO_ALT_FN_1_IN); 949 /* Power to Marvell 88W8385 */ 950 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 951 } 952 953 static void 954 netmmc_config(void) 955 { 956 957 etherstix_config(); 958 basix_config(); 959 } 960 961 static void 962 wifistix_config(void) 963 { 964 965 cfstix_config(); 966 967 /* Power to Marvell 88W8385 */ 968 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 969 } 970 971 static void 972 wifistix_cf_config(void) 973 { 974 975 gxpcic_slot_irqs[1].valid = 1; 976 gxpcic_slot_irqs[1].cd = 36; 977 gxpcic_slot_irqs[1].prdy = 27; 978 979 #if 1 980 /* this configuration set by pxa2x0_pcic.c::pxapcic_attach_common() */ 981 #else 982 pxa2x0_gpio_set_function(36, GPIO_IN); /* PCD2 */ 983 pxa2x0_gpio_set_function(27, GPIO_IN); /* PRDY2/~IRQ2 */ 984 #endif 985 pxa2x0_gpio_set_function(18, GPIO_IN); /* BVD2/~STSCHG2 */ 986 987 cfstix_config(); 988 989 /* Power to Marvell 88W8385 */ 990 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 991 } 992 993 #elif defined(OVERO) 994 995 static void 996 eth0_config(void) 997 { 998 /* 999 * ETH0 connects via CS5. It use GPIO 176 for IRQ. 1000 * Also GPIO 64 is NRESET. 1001 */ 1002 1003 smsh_config(NULL, 176, 64); 1004 } 1005 1006 static void 1007 eth1_config(void) 1008 { 1009 struct omap_mux_conf eth1_mux_conf[] = { 1010 { 0x0d2, MUXMODE(4) | INPUTENABLE }, 1011 { -1 } 1012 }; 1013 1014 /* 1015 * ETH1 connects via CS4. It use GPIO 65 for IRQ. 1016 */ 1017 1018 smsh_config(eth1_mux_conf, 65, 64); 1019 } 1020 1021 static void 1022 dvi_config(void) 1023 { 1024 static const struct omap_mux_conf overo_mux_dvi_conf[] = { 1025 { 0x0d4, MUXMODE(0) }, /* dss_pclk */ 1026 { 0x0d6, MUXMODE(0) }, /* dss_pclk */ 1027 { 0x0d8, MUXMODE(0) }, /* dss_pclk */ 1028 { 0x0da, MUXMODE(0) }, /* dss_pclk */ 1029 { 0x0dc, MUXMODE(0) }, /* dss_pclk */ 1030 { 0x0de, MUXMODE(0) }, /* dss_pclk */ 1031 { 0x0e0, MUXMODE(0) }, /* dss_pclk */ 1032 { 0x0e2, MUXMODE(0) }, /* dss_pclk */ 1033 { 0x0e4, MUXMODE(0) }, /* dss_pclk */ 1034 { 0x0e6, MUXMODE(0) }, /* dss_pclk */ 1035 { 0x0e8, MUXMODE(0) }, /* dss_pclk */ 1036 { 0x0ea, MUXMODE(0) }, /* dss_pclk */ 1037 { 0x0ec, MUXMODE(0) }, /* dss_pclk */ 1038 { 0x0ee, MUXMODE(0) }, /* dss_pclk */ 1039 { 0x0f0, MUXMODE(0) }, /* dss_pclk */ 1040 { 0x0f2, MUXMODE(0) }, /* dss_pclk */ 1041 { 0x0f4, MUXMODE(0) }, /* dss_pclk */ 1042 { 0x0f6, MUXMODE(0) }, /* dss_pclk */ 1043 { 0x0f8, MUXMODE(0) }, /* dss_pclk */ 1044 { 0x0fa, MUXMODE(0) }, /* dss_pclk */ 1045 { 0x0fc, MUXMODE(0) }, /* dss_pclk */ 1046 { 0x0fe, MUXMODE(0) }, /* dss_pclk */ 1047 { 0x100, MUXMODE(0) }, /* dss_pclk */ 1048 { 0x102, MUXMODE(0) }, /* dss_pclk */ 1049 { 0x104, MUXMODE(0) }, /* dss_pclk */ 1050 { 0x106, MUXMODE(0) }, /* dss_pclk */ 1051 { 0x108, MUXMODE(0) }, /* dss_pclk */ 1052 { 0x10a, MUXMODE(0) }, /* dss_pclk */ 1053 { -1 } 1054 }; 1055 1056 gxio_omap_mux_config(overo_mux_dvi_conf); 1057 } 1058 1059 static void 1060 lcd_config(char type) 1061 { 1062 static const struct omap_mux_conf overo_mux_mcspi1_conf[] = { 1063 { 0x1c8, MUXMODE(0) | INPUTENABLE }, /* mcspi1_clk */ 1064 { 0x1ca, MUXMODE(0) | INPUTENABLE }, /* mcspi1_simo*/ 1065 { 0x1cc, MUXMODE(0) | INPUTENABLE }, /* mcspi1_somi*/ 1066 { 0x1ce, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs0 */ 1067 { 0x1d0, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs1 */ 1068 { -1 } 1069 }; 1070 static const struct omap_mux_conf overo_mux_ads7846_conf[] = { 1071 { 0x138, /* gpio_114: NPENIRQ */ 1072 MUXMODE(4) | PULLUDENABLE | INPUTENABLE }, 1073 { -1 } 1074 }; 1075 static const struct omap_mux_conf overo_mux_lcd_conf[] = { 1076 { 0x174, MUXMODE(4) }, /* gpio_144: DISPLAY_EN */ 1077 { 0x176, MUXMODE(4) }, /* gpio_145: Brightness */ 1078 { -1 } 1079 }; 1080 1081 static const struct omap_gpio_conf overo_gpio_lcd_conf[] = { 1082 { 144, conf_output_0 }, /* DISPLAY_EN */ 1083 { 145, conf_output_0 }, /* Brightness */ 1084 { -1 } 1085 }; 1086 1087 dvi_config(); 1088 if (type != 'C') { 1089 gxio_omap_mux_config(overo_mux_mcspi1_conf); 1090 gxio_omap_mux_config(overo_mux_ads7846_conf); 1091 } 1092 gxio_omap_mux_config(overo_mux_lcd_conf); 1093 1094 gxio_omap_gpio_config(overo_gpio_lcd_conf); 1095 } 1096 1097 enum { 1098 uart1_if_exists = 0, 1099 force_uart1 1100 }; 1101 static void 1102 header_40pin_config(int uart1) 1103 { 1104 static const struct omap_mux_conf overo_mux_40pin_header_conf[] = { 1105 /* 1106 * 1: GND 1107 * 2: VCC_3.3 1108 * 3: GPIO171_SPI1_CLK 1109 * 4: GPIO114_SPI1_NIRQ 1110 * 5: GPIO172_SPI1_MOSI 1111 * 6: GPIO174_SPI1_CS0 1112 * 7: GPIO173_SPI1_MISO 1113 * 8: GPIO175_SPI1_CS1 1114 * 9: GPIO151_RXD1 1115 * 10: GPIO148_TXD1 1116 * 11: SYS_EN 1117 * 12: VBACKUP 1118 * 13: GPIO0_WAKEUP 1119 * 14: POWERON 1120 * 15: GND 1121 * 16: VCC_1.8 1122 * 17: GPIO128_GPS_PPS 1123 * 18: GPIO127_TS_IRQ 1124 * 19: GPIO170_HDQ_1WIRE 1125 * 20: GPIO163_IR_CTS3 1126 * 21: GPIO165_IR_RXD3 (console) 1127 * 22: GPIO166_IR_TXD3 (console) 1128 * 23: GPIO184_SCL3 (system eeprom) 1129 * 24: GPIO185_SDA3 (system eeprom) 1130 * 25: GND 1131 * 26: VCC_1.8 1132 * 27: GPIO146_PWM11 1133 * 28: GPIO145_PWM10 1134 * 29: GPIO147_PWM8 1135 * 30: GPIO144_PWM9 1136 * 31: PWM0 (TPS65950) 1137 * 32: PWM1 (TPS65950) 1138 * 33: ADCIN7 (TPS65950) 1139 * 34: ADCIN2 (TPS65950) 1140 * 35: ADCIN6 (TPS65950) 1141 * 36: ADCIN5 (TPS65950) 1142 * 37: AGND (TPS65950) 1143 * 38: ADCIN3 (TPS65950) 1144 * 39: ADCIN4 (TPS65950) 1145 * 40: VIN (TPS65950) 1146 */ 1147 1148 { 0x152, MUXMODE(4) | INPUTENABLE }, /* gpio_127 */ 1149 { 0x154, MUXMODE(4) | INPUTENABLE }, /* gpio_128 */ 1150 { 0x174, MUXMODE(4) | INPUTENABLE }, /* gpio_144 */ 1151 { 0x176, MUXMODE(4) | INPUTENABLE }, /* gpio_145 */ 1152 { 0x178, MUXMODE(4) | INPUTENABLE }, /* gpio_146 */ 1153 { 0x17a, MUXMODE(4) | INPUTENABLE }, /* gpio_147 */ 1154 { 0x19a, MUXMODE(4) | INPUTENABLE }, /* gpio_163 */ 1155 { -1 } 1156 }; 1157 static const struct omap_mux_conf overo_mux_uart1_conf[] = { 1158 { 0x17c, MUXMODE(0) }, /* uart1_tx */ 1159 { 0x182, MUXMODE(0) | INPUTENABLE }, /* uart1_rx */ 1160 { -1 } 1161 }; 1162 static const struct omap_mux_conf overo_mux_no_uart1_conf[] = { 1163 { 0x17c, MUXMODE(4) | INPUTENABLE }, /* gpio_148 */ 1164 { 0x182, MUXMODE(4) | INPUTENABLE }, /* gpio_151 */ 1165 { -1 } 1166 }; 1167 static const struct omap_mux_conf overo_mux_hdq_conf[] = { 1168 #if 0 1169 { 0x1c4, MUXMODE(0) | ??? | INPUTENABLE }, /* hdq_sio */ 1170 #endif 1171 { -1 } 1172 }; 1173 static const struct omap_mux_conf overo_mux_no_hdq_conf[] = { 1174 { 0x1c4, MUXMODE(4) | INPUTENABLE }, /* gpio_170 */ 1175 { -1 } 1176 }; 1177 1178 gxio_omap_mux_config(overo_mux_40pin_header_conf); 1179 if (uart1 == force_uart1) 1180 gxio_omap_mux_config(overo_mux_uart1_conf); 1181 else 1182 gxio_omap_mux_config_address("com", 0x4806a000, 1183 overo_mux_uart1_conf, overo_mux_no_uart1_conf); 1184 gxio_omap_mux_config_address("hdq", 0x480b2000, 1185 overo_mux_hdq_conf, overo_mux_no_hdq_conf); 1186 } 1187 1188 static void 1189 chestnut_config(void) 1190 { 1191 static const struct omap_mux_conf chestnut_mux_conf[] = { 1192 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1193 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1194 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1195 { -1 } 1196 }; 1197 1198 eth0_config(); 1199 lcd_config('R'); 1200 1201 header_40pin_config(uart1_if_exists); 1202 gxio_omap_mux_config(chestnut_mux_conf); 1203 } 1204 1205 static void 1206 gallop_config(void) 1207 { 1208 static const struct omap_mux_conf gallop43_mux_conf[] = { 1209 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1210 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1211 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1212 { -1 } 1213 }; 1214 1215 lcd_config('R'); 1216 1217 header_40pin_config(force_uart1); 1218 gxio_omap_mux_config(gallop43_mux_conf); 1219 } 1220 1221 static void 1222 summit_config(void) 1223 { 1224 1225 dvi_config(); 1226 1227 header_40pin_config(uart1_if_exists); 1228 } 1229 1230 static void 1231 tobi_config(void) 1232 { 1233 1234 eth0_config(); 1235 dvi_config(); 1236 1237 header_40pin_config(uart1_if_exists); 1238 } 1239 1240 static void 1241 tobiduo_config(void) 1242 { 1243 1244 eth0_config(); 1245 eth1_config(); 1246 } 1247 1248 #elif defined(DUOVERO) 1249 1250 static void 1251 ehci_config(void) 1252 { 1253 uint32_t val; 1254 1255 #define SCRM_ALTCLKSRC 0xa110 1256 #define ALTCLKSRC_ENABLE_EXT (1 << 3) 1257 #define ALTCLKSRC_ENABLE_INT (1 << 2) 1258 #define ALTCLKSRC_MODE_MASK (3 << 0) 1259 #define ALTCLKSRC_MODE_POWERDOWN (0 << 0) 1260 #define ALTCLKSRC_MODE_ACTIVE (1 << 0) 1261 #define ALTCLKSRC_MODE_BYPASS (2 << 0) 1262 #define SCRM_AUXCLK3 0xa31c 1263 #define AUXCLK3_CLKDIV(n) (((n) - 1) << 16) 1264 #define AUXCLK3_CLKDIV_MASK (0xf << 16) 1265 #define AUXCLK3_ENABLE (1 << 8) 1266 #define AUXCLK3_SRCSELECT_MASK (3 << 1) 1267 #define AUXCLK3_SRCSELECT_SYSCLK (0 << 1) 1268 #define AUXCLK3_SRCSELECT_CORE (1 << 1) 1269 #define AUXCLK3_SRCSELECT_PERDPLL (2 << 1) 1270 #define AUXCLK3_SRCSELECT_ALTCLK (3 << 1) 1271 #define AUXCLK3_POLARITY_LOW (0 << 0) 1272 #define AUXCLK3_POLARITY_HIGH (1 << 0) 1273 1274 /* Use the 1/2 auxiliary clock #3 of system clock. */ 1275 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3); 1276 val &= ~(AUXCLK3_CLKDIV_MASK | AUXCLK3_SRCSELECT_MASK); 1277 val |= (AUXCLK3_CLKDIV(2) | AUXCLK3_ENABLE | AUXCLK3_SRCSELECT_SYSCLK); 1278 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3, val); 1279 1280 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC); 1281 val &= ~ALTCLKSRC_MODE_MASK; 1282 val |= ALTCLKSRC_MODE_ACTIVE; 1283 val |= (ALTCLKSRC_ENABLE_EXT | ALTCLKSRC_ENABLE_INT); 1284 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC, val); 1285 } 1286 1287 static void 1288 parlor_config(void) 1289 { 1290 #if 0 1291 static const struct omap_mux_conf parlor_mux_40pin_header_conf[] = { 1292 /* 1293 * 1: GND 1294 * 2: GND 1295 * 3: MCSPI1_CLK or GPIO 134 1296 * 4: MCSPI1_CS0 or GPIO 137 1297 * 5: MCSPI1_SIMO or GPIO 136 1298 * 6: MCSPI1_CS1 or GPIO 138 1299 * 7: MCSPI1_SOMI or GPIO 135 1300 * 8: MCSPI1_CS2 or GPIO 139 1301 * 9: HDQ_SIO or GPIO 127 1302 * 10: MCSPI1_CS3 or GPIO 140 1303 * 11: SDMMC3_CMD or GPIO ??? 1304 * 12: I2C2_SCL or GPIO 128 1305 * 13: SDMMC3_CLK or GPIO ??? 1306 * 14: I2C2_SDA or GPIO 129 1307 * 15: UART2_TX or SDMMC3_DAT1 or GPIO 126 1308 * 16: PMIC_PWM2 (TWL6030) 1309 * 17: UART2_RX or SDMMC3_DAT0 or GPIO 125 1310 * 18: PMIC_PWM1 (TWL6030) 1311 * 19: BSP2_CLKX or GPIO 110 1312 * 20: BSP2_FSX or GPIO 113 1313 * 21: BSP2_DX or GPIO 112 1314 * 22: BSP2_DR or GPIO 111 1315 * 23: BSP2_CLKS or GPIO 118 1316 * 24: FREF1 1317 * 25: MCSPI4_SOMI or GPIO 153 1318 * 26: PMIC_NRESWARN 1319 * 27: MCSPI4_SIMO or GPIO 152 1320 * 28: SYSEN 1321 * 29: MCSPI4_CLK or GPIO 151 1322 * 30: PWRON 1323 * 31: MCSPI4_CS0 or GPIO 154 1324 * 32: REGEN1 1325 * 33: ADCIN3 (TWL6030) 1326 * 34: VCC_1.0 1327 * 35: ADCIN4_VREF (TWL6030) 1328 * 36: VDD_VAUX2 1329 * 37: ADCIN4 (TWL6030) 1330 * 38: VCC_3.3 1331 * 39: ADCIN5 (TWL6030) 1332 * 40: V_BATT_5 1333 */ 1334 { -1 } 1335 }; 1336 #endif 1337 static const struct omap_mux_conf parlor_mux_mcspi1_conf[] = { 1338 #if 0 1339 { 0x132, /* 3: MCSPI1_CLK */ 1340 MUXMODE(0) | ??? }, 1341 { 0x138, /* 4: MCSPI1_CS0 */ 1342 MUXMODE(0) | ??? }, 1343 { 0x136, /* 5: MCSPI1_SIMO */ 1344 MUXMODE(0) | ??? }, 1345 { 0x13a, /* 6: MCSPI1_CS1 */ 1346 MUXMODE(0) | ??? }, 1347 { 0x134, /* 7: MCSPI1_SOMI */ 1348 MUXMODE(0) | ??? | INPUTENABLE }, 1349 { 0x13c, /* 8: MCSPI1_CS2 */ 1350 MUXMODE(0) | ??? }, 1351 { 0x13e, /* 10: MCSPI1_CS3 */ 1352 MUXMODE(0) | ??? }, 1353 #endif 1354 { -1 } 1355 }; 1356 static const struct omap_mux_conf parlor_mux_no_mcspi1_conf[] = { 1357 { 0x132, /* 3: GPIO 134 */ 1358 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1359 { 0x138, /* 4: GPIO 137 */ 1360 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1361 { 0x136, /* 5: GPIO 136 */ 1362 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1363 { 0x13a, /* 6: GPIO 138 */ 1364 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1365 { 0x134, /* 7: GPIO 135 */ 1366 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1367 { 0x13c, /* 8: GPIO 139 */ 1368 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1369 { 0x13e, /* 10: GPIO 140 */ 1370 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1371 { -1 } 1372 }; 1373 static const struct omap_mux_conf parlor_mux_hdq_conf[] = { 1374 #if 0 1375 { 0x120, /* 9: HDQ_SIO */ 1376 MUXMODE(0) | ??? | INPUTENABLE }, 1377 #endif 1378 { -1 } 1379 }; 1380 static const struct omap_mux_conf parlor_mux_no_hdq_conf[] = { 1381 { 0x120, /* 9: GPIO_127 */ 1382 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1383 { -1 } 1384 }; 1385 static const struct omap_mux_conf parlor_mux_i2c2_conf[] = { 1386 { 0x126, /* 12: I2C2_SCL */ 1387 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1388 { 0x128, /* 14: I2C2_SDA */ 1389 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1390 { -1 } 1391 }; 1392 static const struct omap_mux_conf parlor_mux_no_i2c2_conf[] = { 1393 { 0x126, /* 12: GPIO 128 */ 1394 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1395 { 0x128, /* 14: GPIO 129 */ 1396 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1397 { -1 } 1398 }; 1399 static const struct omap_mux_conf parlor_mux_sdmmc3_conf[] = { 1400 #if 0 1401 11 SDMMC3_CMD DuoVero J2 A15 <- omap pin AG10 1402 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1403 13 SDMMC3_CLK DuoVero J2 A16 <- omap pin AE9 1404 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1405 #endif 1406 { 0x11c, /* 17: SDMMC3_DAT0 */ 1407 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1408 { 0x11e, /* 15: SDMMC3_DAT1 */ 1409 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1410 { -1 } 1411 }; 1412 static const struct omap_mux_conf parlor_mux_uart2_conf[] = { 1413 { 0x11c, /* 17: UART2_RX */ 1414 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1415 { 0x11e, 1416 MUXMODE(0) | PULLUDENABLE }, /* 15: UART2_TX */ 1417 { -1 } 1418 }; 1419 static const struct omap_mux_conf parlor_mux_no_uart2_conf[] = { 1420 { 0x11c, /* 17: GPIO 125 */ 1421 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1422 { 0x11e, /* 15: GPIO 126 */ 1423 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1424 { -1 } 1425 }; 1426 static const struct omap_mux_conf parlor_mux_bsp2_conf[] = { 1427 { 0x0f6, /* 19: BSP2_CLKX */ 1428 MUXMODE(0) | INPUTENABLE }, 1429 { 0x0fc, /* 20: BSP2_FSX */ 1430 MUXMODE(0) | INPUTENABLE }, 1431 { 0x0fa, /* 21: BSP2_DX */ 1432 MUXMODE(0) | PULLUDENABLE }, 1433 { 0x0f8, /* 22: BSP2_DR */ 1434 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1435 { 0x10e, /* 23: BSP2_CLKS */ 1436 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1437 { -1 } 1438 }; 1439 static const struct omap_mux_conf parlor_mux_no_bsp2_conf[] = { 1440 { 0x0f6, /* 19: GPIO 110 */ 1441 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1442 { 0x0fc, /* 20: GPIO 113 */ 1443 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1444 { 0x0fa, /* 21: GPIO 112 */ 1445 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1446 { 0x0f8, /* 22: GPIO 111 */ 1447 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1448 { 0x10e, /* 23: GPIO 118 */ 1449 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1450 { -1 } 1451 }; 1452 static const struct omap_mux_conf parlor_mux_mcspi4_conf[] = { 1453 #if 0 1454 { 0x158, /* 25: MCSPI4_SOMI */ 1455 MUXMODE(0) | ??? | INPUTENABLE }, 1456 { 0x156, /* 27: MCSPI4_SIMO */ 1457 MUXMODE(0) | ??? }, 1458 { 0x154, /* 29: MCSPI4_CLK */ 1459 MUXMODE(0) | ??? }, 1460 { 0x15a, /* 31: MCSPI4_CS0 */ 1461 MUXMODE(0) | ??? }, 1462 #endif 1463 { -1 } 1464 }; 1465 static const struct omap_mux_conf parlor_mux_no_mcspi4_conf[] = { 1466 { 0x158, /* 25: GPIO 153 */ 1467 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1468 { 0x156, /* 27: GPIO 152 */ 1469 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1470 { 0x154, /* 29: GPIO 151 */ 1471 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1472 { 0x15a, /* 31: GPIO 154 */ 1473 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1474 { -1 } 1475 }; 1476 1477 /* 1478 * ETH0 connects via CS5. It use GPIO 44 for IRQ. 1479 * Also GPIO 45 is NRESET. 1480 */ 1481 smsh_config(NULL, 44, 45); 1482 1483 ehci_config(); 1484 1485 gxio_omap_mux_config_address("mcspi", 0x48098000, 1486 parlor_mux_mcspi1_conf, parlor_mux_no_mcspi1_conf); 1487 gxio_omap_mux_config_address("hdq", 0x480b2000, 1488 parlor_mux_hdq_conf, parlor_mux_no_hdq_conf); 1489 gxio_omap_mux_config_address("tiiic", 0x48072000, 1490 parlor_mux_i2c2_conf, parlor_mux_no_i2c2_conf); 1491 if (gxio_omap_mux_config_address("sdhc", 0x480ad000, 1492 parlor_mux_sdmmc3_conf, NULL) != 0) 1493 gxio_omap_mux_config_address("com", 0x4806c000, 1494 parlor_mux_uart2_conf, parlor_mux_no_uart2_conf); 1495 gxio_omap_mux_config_address("mcbsp", 0x49024000, 1496 parlor_mux_bsp2_conf, parlor_mux_no_bsp2_conf); 1497 gxio_omap_mux_config_address("mcspi", 0x480ba000, 1498 parlor_mux_mcspi4_conf, parlor_mux_no_mcspi4_conf); 1499 } 1500 1501 #elif defined(PEPPER) 1502 1503 static void 1504 lcd_config(void) 1505 { 1506 static const struct tifb_panel_info panel_lcd = { 1507 .panel_tft = 1, 1508 .panel_mono = false, 1509 .panel_bpp = 24, 1510 1511 .panel_pxl_clk = 18400000, 1512 .panel_width = 480, 1513 .panel_height = 272, 1514 .panel_hfp = 8, 1515 .panel_hbp = 4, 1516 .panel_hsw = 41, 1517 .panel_vfp = 4, 1518 .panel_vbp = 2, 1519 .panel_vsw = 10, 1520 .panel_invert_hsync = 0, 1521 .panel_invert_vsync = 0, 1522 1523 .panel_ac_bias = 255, 1524 .panel_ac_bias_intrpt = 0, 1525 .panel_dma_burst_sz = 16, 1526 .panel_fdd = 0x80, 1527 .panel_sync_edge = 0, 1528 .panel_sync_ctrl = 1, 1529 .panel_tft_alt_mode = 0, 1530 .panel_invert_pxl_clk = 0, 1531 }; 1532 static const struct omap_mux_conf pepper_mux_lcd_conf[] = { 1533 /* 1534 * LCD_DATA[0-23] configures in tifb.c 1535 */ 1536 1537 { 0x8e0, MMODE(0) | PUDEN }, /* LCD_VSYNC */ 1538 { 0x8e4, MMODE(0) | PUDEN }, /* LCD_HSYNC */ 1539 { 0x8e8, MMODE(0) | PUDEN }, /* LCD_PCLK */ 1540 { 0x8ec, MMODE(0) | PUDEN }, /* LCD_AC_BIAS_EN */ 1541 1542 { 0x86c, MMODE(7) | PUTYPESEL }, /* GPIO 59: Enable */ 1543 { -1 } 1544 }; 1545 1546 if (gxio_omap_mux_config_address("tifb", 0x4830e000, 1547 pepper_mux_lcd_conf, NULL) == 0) { 1548 extern const struct tifb_panel_info *tifb_panel_info; 1549 extern bool use_tps65217_wled; 1550 1551 tifb_panel_info = &panel_lcd; 1552 use_tps65217_wled = true; 1553 } 1554 } 1555 1556 static void 1557 pepper43_config(void) 1558 { 1559 static const struct omap_mux_conf pepper43_mux_wilink8_conf[] = { 1560 /* TI WiLink 8 */ 1561 { 0x800, MMODE(7) | PUTYPESEL }, /* GPIO 32: Bluetooth */ 1562 { 0x804, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 33: irq */ 1563 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: WiFi */ 1564 { -1 } 1565 }; 1566 static const struct omap_mux_conf pepper43_mux_i2c1_conf[] = { 1567 { 0x968, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1568 { 0x96c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1569 { -1 } 1570 }; 1571 static const struct omap_mux_conf pepper43_mpu9150_conf[] = { 1572 /* MPU9150 at I2C1 */ 1573 { 0x808, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 34: IRQ */ 1574 { 0x898, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 68 */ 1575 { 0x870, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 30 */ 1576 { -1 } 1577 }; 1578 static const struct omap_mux_conf pepper43_mux_20pin_header_conf[] = { 1579 { 0x85c, MMODE(7) | PUDEN | RXACTIVE }, /* 1: GPIO 55 */ 1580 { 0x80c, MMODE(7) | PUDEN | RXACTIVE }, /* 2: GPIO 35 */ 1581 { 0x810, MMODE(7) | PUDEN | RXACTIVE }, /* 3: GPIO 36 */ 1582 { 0x814, MMODE(7) | PUDEN | RXACTIVE }, /* 4: GPIO 37 */ 1583 { 0x818, MMODE(7) | PUDEN | RXACTIVE }, /* 5: GPIO 38 */ 1584 { 0x81c, MMODE(7) | PUDEN | RXACTIVE }, /* 6: GPIO 39 */ 1585 { 0x87c, MMODE(7) | PUDEN | RXACTIVE }, /* 7: GPIO 61 */ 1586 { 0x880, MMODE(7) | PUDEN | RXACTIVE }, /* 8: GPIO 62 */ 1587 { 0x884, MMODE(7) | PUDEN | RXACTIVE }, /* 9: GPIO 63 */ 1588 { 0x9e4, MMODE(7) | PUDEN | RXACTIVE }, /* 10: GPIO 103 */ 1589 { 0x9e8, MMODE(7) | PUDEN | RXACTIVE }, /* 11: GPIO 104 */ 1590 { 0x9b0, MMODE(7) | PUDEN | RXACTIVE }, /* 12: GPIO 19 */ 1591 #if 0 /* UART3 or GPIO */ 1592 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* 13: GPIO 7 */ 1593 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* 14: GPIO 6 */ 1594 #endif 1595 #if 0 /* UART2 or GPIO */ 1596 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* 15: GPIO 98 */ 1597 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* 16: GPIO 97 */ 1598 #endif 1599 /* 17: VCC 5v */ 1600 /* 18: VCC 3.3v */ 1601 /* 19: GND */ 1602 /* 20: GND */ 1603 { -1 } 1604 }; 1605 static const struct omap_mux_conf pepper43_mux_uart2_conf[] = { 1606 { 0x90c, MMODE(6) | PUTYPESEL | RXACTIVE }, /* UART2_RXD */ 1607 { 0x910, MMODE(6) | PUDEN }, /* UART2_TXD */ 1608 { -1 } 1609 }; 1610 static const struct omap_mux_conf pepper43_mux_no_uart2_conf[] = { 1611 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 97 */ 1612 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 98 */ 1613 { -1 } 1614 }; 1615 static const struct omap_mux_conf pepper43_mux_uart3_conf[] = { 1616 { 0x960, MMODE(1) | PUTYPESEL | RXACTIVE }, /* UART3_RXD */ 1617 { 0x964, MMODE(1) | PUDEN }, /* UART3_TXD */ 1618 { -1 } 1619 }; 1620 static const struct omap_mux_conf pepper43_mux_no_uart3_conf[] = { 1621 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 6 */ 1622 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 7 */ 1623 { -1 } 1624 }; 1625 1626 static const struct omap_mux_conf *pepper43_mux_conf[] = { 1627 pepper43_mux_wilink8_conf, 1628 pepper43_mux_i2c1_conf, 1629 pepper43_mpu9150_conf, 1630 pepper43_mux_20pin_header_conf, 1631 }; 1632 1633 static const struct omap_gpio_conf pepper43_gpio_wl18xx_conf[] = { 1634 { 32, conf_output_0 }, /* #Reset: Bluetooth */ 1635 { 56, conf_output_0 }, /* #Reset: WiFi */ 1636 { -1 } 1637 }; 1638 int i; 1639 1640 lcd_config(); 1641 1642 for (i = 0; i < __arraycount(pepper43_mux_conf); i++) 1643 gxio_omap_mux_config(pepper43_mux_conf[i]); 1644 gxio_omap_gpio_config(pepper43_gpio_wl18xx_conf); 1645 1646 #if 0 1647 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 52 (Blue) */ 1648 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 20)); 1649 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1650 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 20)); 1651 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 53 (Red) */ 1652 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 21)); 1653 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1654 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 21)); 1655 #endif 1656 1657 gxio_omap_mux_config_address("com", 0x48024000, 1658 pepper43_mux_uart2_conf, pepper43_mux_no_uart2_conf); 1659 gxio_omap_mux_config_address("com", 0x481a6000, 1660 pepper43_mux_uart3_conf, pepper43_mux_no_uart3_conf); 1661 } 1662 1663 static void 1664 pepper_config(void) 1665 { 1666 static const struct omap_mux_conf pepper_mux_button2_conf[] = { 1667 { 0x85c, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 55 */ 1668 { -1 } 1669 }; 1670 static const struct omap_mux_conf pepper_mux_i2c1_conf[] = { 1671 { 0x90c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1672 { 0x910, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1673 { -1 } 1674 }; 1675 static const struct omap_mux_conf pepper_mux_wi2wi_conf[] = { 1676 { 0x9b4, MMODE(3) | PUDEN }, /* CLKOUT2 */ 1677 /* Wi2Wi */ 1678 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: nReset */ 1679 { 0x870, MMODE(7) | PUTYPESEL }, /* GPIO 30: nPower */ 1680 { -1 } 1681 }; 1682 static const struct omap_mux_conf pepper_mux_uart1_conf[] = { 1683 { 0x978, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_CTSn */ 1684 { 0x97c, MMODE(0) }, /* UART1_RTSn */ 1685 { 0x980, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_RXD */ 1686 { 0x984, MMODE(0) }, /* UART1_TXD */ 1687 { -1 } 1688 }; 1689 static const struct omap_mux_conf pepper_mux_no_uart1_conf[] = { 1690 { 0x978, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 12 */ 1691 { 0x97c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 13 */ 1692 { 0x980, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 14 */ 1693 { 0x984, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 15 */ 1694 { -1 } 1695 }; 1696 static const struct omap_mux_conf *pepper_mux_conf[] = { 1697 pepper_mux_button2_conf, 1698 pepper_mux_i2c1_conf, 1699 pepper_mux_wi2wi_conf, 1700 }; 1701 1702 int i; 1703 1704 lcd_config(); 1705 1706 for (i = 0; i < __arraycount(pepper_mux_conf); i++) 1707 gxio_omap_mux_config(pepper_mux_conf[i]); 1708 gxio_omap_mux_config_address("com", 0x48022000, 1709 pepper_mux_uart1_conf, pepper_mux_no_uart1_conf); 1710 } 1711 1712 static void 1713 c_config(void) 1714 { 1715 static const struct omap_mux_conf pepper43c_mux_ft5306_conf[] = { 1716 /* FT5306 at I2C2 */ 1717 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20 */ 1718 { 0x95c, MMODE(7) | PUDEN }, /* GPIO 5 */ 1719 { -1 } 1720 }; 1721 static const struct omap_mux_conf pepper43c_mux_i2c2_conf[] = { 1722 { 0x950, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SDA */ 1723 { 0x954, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SCL */ 1724 { -1 } 1725 }; 1726 static const struct omap_mux_conf *pepper43c_mux_conf[] = { 1727 pepper43c_mux_ft5306_conf, 1728 pepper43c_mux_i2c2_conf, 1729 }; 1730 1731 static const struct omap_gpio_conf pepper43c_gpio_ft5306_conf[] = { 1732 { 5, conf_output_0 }, /* #Reset */ 1733 { -1 } 1734 }; 1735 int i; 1736 1737 pepper43_config(); 1738 1739 for (i = 0; i < __arraycount(pepper43c_mux_conf); i++) 1740 gxio_omap_mux_config(pepper43c_mux_conf[i]); 1741 gxio_omap_gpio_config(pepper43c_gpio_ft5306_conf); 1742 } 1743 1744 static void 1745 dvi_config(void) 1746 { 1747 /* XXXX: hmm... mismatch found in Linux's dts and pubs.gumstix.org... */ 1748 1749 extern struct cfdata cfdata[]; 1750 extern const struct tifb_panel_info *tifb_panel_info; 1751 1752 static const struct tifb_panel_info panel_dvi = { 1753 .panel_tft = 1, 1754 .panel_mono = false, 1755 .panel_bpp = 16, 1756 1757 .panel_pxl_clk = 63500000, 1758 .panel_width = 1024, 1759 .panel_height = 768, 1760 .panel_hfp = 8, 1761 .panel_hbp = 4, 1762 .panel_hsw = 41, 1763 .panel_vfp = 4, 1764 .panel_vbp = 2, 1765 .panel_vsw = 10, 1766 .panel_invert_hsync = 0, 1767 .panel_invert_vsync = 0, 1768 1769 .panel_ac_bias = 255, 1770 .panel_ac_bias_intrpt = 0, 1771 .panel_dma_burst_sz = 16, 1772 .panel_fdd = 0x80, 1773 .panel_sync_edge = 0, 1774 .panel_sync_ctrl = 1, 1775 .panel_invert_pxl_clk = 0, 1776 }; 1777 cfdata_t cf = &cfdata[0]; 1778 1779 /* Disable wireless module. */ 1780 while (cf->cf_name != NULL) { 1781 if (strcmp(cf->cf_name, "sdhc") == 0 && 1782 strcmp(cf->cf_atname, "mainbus") == 0 && 1783 cf->cf_loc[MAINBUSCF_BASE] == 0x47810000) { 1784 if (cf->cf_fstate == FSTATE_NOTFOUND) 1785 cf->cf_fstate = FSTATE_DNOTFOUND; 1786 else if (cf->cf_fstate == FSTATE_STAR) 1787 cf->cf_fstate = FSTATE_DSTAR; 1788 } 1789 cf++; 1790 } 1791 1792 tifb_panel_info = &panel_dvi; 1793 } 1794 1795 static void 1796 r_config(void) 1797 { 1798 static const struct omap_mux_conf pepper43r_mux_ads7846_conf[] = { 1799 /* ADS7846 at McSPI0 */ 1800 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20: IRQ */ 1801 { -1 } 1802 }; 1803 static const struct omap_mux_conf pepper43r_mux_spi0_conf[] = { 1804 { 0x950, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_SCLK */ 1805 { 0x954, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D0 */ 1806 { 0x958, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D1 */ 1807 { 0x95c, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_CS0 */ 1808 { -1 } 1809 }; 1810 static const struct omap_mux_conf *pepper43r_mux_conf[] = { 1811 pepper43r_mux_ads7846_conf, 1812 pepper43r_mux_spi0_conf, 1813 }; 1814 int i; 1815 1816 pepper43_config(); 1817 1818 for (i = 0; i < __arraycount(pepper43r_mux_conf); i++) 1819 gxio_omap_mux_config(pepper43r_mux_conf[i]); 1820 } 1821 1822 #endif 1823 1824 #if defined(OVERO) || defined(DUOVERO) 1825 static void 1826 smsh_config(struct omap_mux_conf *smsh_mux_conf, int intr, int nreset) 1827 { 1828 struct omap_gpio_conf smsh_gpio_conf[] = { 1829 { intr, conf_input }, 1830 { nreset, conf_output_0 }, 1831 { -1 } 1832 }; 1833 1834 /* 1835 * Basically use current settings by U-Boot. 1836 * However remap physical address to configured address. 1837 */ 1838 1839 if (smsh_mux_conf != NULL) 1840 gxio_omap_mux_config(smsh_mux_conf); 1841 gxio_omap_gpio_config(smsh_gpio_conf); 1842 __udelay(100000); 1843 gxio_omap_gpio_write(nreset, 1); 1844 } 1845 #endif 1846 1847 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1848 /* 1849 * The delay for configuration time. 1850 * This function use initialized timer by U-Boot. 1851 */ 1852 static void 1853 __udelay(unsigned int usec) 1854 { 1855 #if defined(OVERO) || defined(DUOVERO) 1856 #define V_SCLK (26000000 >> 1) 1857 #define TCRR 0x28 1858 #elif defined(PEPPER) 1859 #define V_SCLK 24000000 1860 #define TCRR 0x3c 1861 #endif 1862 #define SYS_PTV 2 1863 #define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV)) 1864 1865 const vaddr_t timer_base = 1866 #if defined(OVERO) 1867 OVERO_L4_PERIPHERAL_VBASE + 0x32000; 1868 #elif defined(DUOVERO) 1869 DUOVERO_L4_PERIPHERAL_VBASE + 0x32000; 1870 #elif defined(PEPPER) 1871 PEPPER_L4_PERIPHERAL_VBASE + 0x40000; 1872 #endif 1873 long timo = usec * (TIMER_CLOCK / 1000) / 1000; 1874 uint32_t now, last; 1875 1876 last = ioreg_read(timer_base + TCRR); 1877 while (timo > 0) { 1878 now = ioreg_read(timer_base + TCRR); 1879 if (last > now) 1880 timo -= __BITS(0, 31) - last + now + 1; 1881 else 1882 timo -= now - last; 1883 last = now; 1884 } 1885 } 1886 #endif 1887 1888 #if defined(PEPPER) 1889 static int 1890 read_i2c_device(const vaddr_t i2c_base, uint16_t sa, uint8_t addr, int len, 1891 uint8_t *buf) 1892 { 1893 uint16_t v; 1894 int aok = 0, cnt = 0; 1895 1896 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1897 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1898 while (v & I2C_IRQSTATUS_BB) { 1899 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, v); 1900 __udelay(20); 1901 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1902 } 1903 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1904 1905 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1906 ioreg16_write(i2c_base + OMAP2_I2C_CNT, sizeof(addr)); 1907 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1908 I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STP | I2C_CON_STT); 1909 while (1 /*CONSTCOND*/) { 1910 __udelay(20); 1911 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1912 if ((v & I2C_IRQSTATUS_XRDY) && aok == 0) { 1913 aok = 1; 1914 ioreg16_write(i2c_base + OMAP2_I2C_DATA, addr); 1915 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1916 I2C_IRQSTATUS_XRDY); 1917 } 1918 if (v & I2C_IRQSTATUS_ARDY) { 1919 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1920 I2C_IRQSTATUS_ARDY); 1921 break; 1922 } 1923 } 1924 1925 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1926 ioreg16_write(i2c_base + OMAP2_I2C_CNT, len); 1927 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1928 I2C_CON_EN | I2C_CON_MST | I2C_CON_STP | I2C_CON_STT); 1929 while (1 /*CONSTCOND*/) { 1930 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1931 if (v & I2C_IRQSTATUS_RRDY && 1932 cnt < len) { 1933 buf[cnt++] = ioreg16_read(i2c_base + OMAP2_I2C_DATA); 1934 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1935 I2C_IRQSTATUS_RRDY); 1936 } 1937 if (v & I2C_IRQSTATUS_ARDY) { 1938 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1939 I2C_IRQSTATUS_ARDY); 1940 break; 1941 } 1942 } 1943 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1944 return 0; 1945 } 1946 #endif 1947
Indexes created Mon Oct 27 08:10:08 GMT 2025