gxio.c revision 1.27
1 /* $NetBSD: gxio.c,v 1.27 2021/04/24 23:36:32 thorpej Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: gxio.c,v 1.27 2021/04/24 23:36:32 thorpej Exp $"); 35 36 #include "opt_cputypes.h" 37 #include "opt_gumstix.h" 38 #include "opt_gxio.h" 39 #if defined(OVERO) 40 #include "opt_omap.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/device.h> 45 #include <sys/errno.h> 46 #include <sys/kernel.h> 47 48 #include <sys/systm.h> 49 50 #include <machine/bootconfig.h> 51 52 #include <arm/omap/omap2_gpmcreg.h> 53 #if defined(OMAP2) 54 #include <arm/omap/omap2_reg.h> 55 #if defined(OMAP3530) 56 #include <arm/omap/omap2_intr.h> 57 #endif 58 #endif 59 #include <arm/omap/omap_var.h> 60 #include <arm/omap/ti_iicreg.h> 61 #include <arm/omap/tifbvar.h> 62 #if defined(CPU_XSCALE) 63 #include <arm/xscale/pxa2x0cpu.h> 64 #endif 65 #include <arm/xscale/pxa2x0reg.h> 66 #include <arm/xscale/pxa2x0var.h> 67 #include <arm/xscale/pxa2x0_gpio.h> 68 #include <evbarm/gumstix/gumstixreg.h> 69 #include <evbarm/gumstix/gumstixvar.h> 70 71 #include "ioconf.h" 72 #include "locators.h" 73 74 75 struct gxioconf { 76 const char *name; 77 void (*config)(void); 78 }; 79 80 #if defined(GUMSTIX) 81 static int gxiomatch(device_t, cfdata_t, void *); 82 static void gxioattach(device_t, device_t, void *); 83 static int gxiosearch(device_t, cfdata_t, const int *, void *); 84 static int gxioprint(void *, const char *); 85 86 CFATTACH_DECL_NEW(gxio, sizeof(struct gxio_softc), 87 gxiomatch, gxioattach, NULL, NULL); 88 #endif 89 90 void gxio_config(void); 91 void gxio_config_expansion(const char *); 92 #if defined(GUMSTIX) 93 static void basix_config(void); 94 static void cfstix_config(void); 95 static void etherstix_config(void); 96 static void netcf_config(void); 97 static void netcf_vx_config(void); 98 static void netduommc_config(void); 99 static void netduo_config(void); 100 static void netmicrosd_config(void); 101 static void netwifimicrosd_config(void); 102 static void netmmc_config(void); 103 static void wifistix_config(void); 104 static void wifistix_cf_config(void); 105 #elif defined(OVERO) 106 static void eth0_config(void); 107 static void eth1_config(void); 108 static void dvi_config(void); 109 static void lcd_config(char); 110 static void header_40pin_config(int); 111 112 static void chestnut_config(void); 113 static void gallop_config(void); 114 static void summit_config(void); 115 static void tobi_config(void); 116 static void tobiduo_config(void); 117 #elif defined(DUOVERO) 118 static void ehci_config(void); 119 120 static void parlor_config(void); 121 #elif defined(PEPPER) 122 static void lcd_config(void); 123 static void pepper43_config(void); 124 125 static void pepper_config(void); 126 static void c_config(void); 127 static void dvi_config(void); 128 static void r_config(void); 129 #endif 130 #if defined(OVERO) || defined(DUOVERO) 131 struct omap_mux_conf; 132 static void smsh_config(struct omap_mux_conf *, int, int); 133 #endif 134 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 135 static void __udelay(unsigned int); 136 #endif 137 #if defined(PEPPER) 138 static int read_i2c_device(const vaddr_t, uint16_t, uint8_t, int, uint8_t *); 139 #endif 140 141 #if defined(CPU_XSCALE_PXA250) 142 143 static struct pxa2x0_gpioconf pxa255dep_gpioconf[] = { 144 /* Bluetooth module configuration */ 145 { 7, GPIO_OUT | GPIO_SET }, /* power on */ 146 { 12, GPIO_ALT_FN_1_OUT }, /* 32kHz out. required by SingleStone */ 147 148 /* AC97 configuration */ 149 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 150 151 /* FFUART configuration */ 152 { 35, GPIO_ALT_FN_1_IN }, /* CTS */ 153 { 41, GPIO_ALT_FN_2_OUT }, /* RTS */ 154 155 #ifndef GXIO_BLUETOOTH_ON_HWUART 156 /* BTUART configuration */ 157 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 158 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 159 #else 160 /* HWUART configuration */ 161 { 42, GPIO_ALT_FN_3_IN }, /* HWRXD */ 162 { 43, GPIO_ALT_FN_3_OUT }, /* HWTXD */ 163 { 44, GPIO_ALT_FN_3_IN }, /* HWCTS */ 164 { 45, GPIO_ALT_FN_3_OUT }, /* HWRTS */ 165 #endif 166 167 #ifndef GXIO_BLUETOOTH_ON_HWUART 168 /* HWUART configuration */ 169 { 48, GPIO_ALT_FN_1_OUT }, /* HWTXD */ 170 { 49, GPIO_ALT_FN_1_IN }, /* HWRXD */ 171 { 50, GPIO_ALT_FN_1_IN }, /* HWCTS */ 172 { 51, GPIO_ALT_FN_1_OUT }, /* HWRTS */ 173 #endif 174 175 { -1 } 176 }; 177 #endif 178 #if defined(CPU_XSCALE_PXA270) 179 static struct pxa2x0_gpioconf verdexdep_gpioconf[] = { 180 /* Bluetooth module configuration */ 181 { 9, GPIO_ALT_FN_3_OUT }, /* CHOUT<0> */ 182 { 12, GPIO_OUT | GPIO_SET }, 183 184 /* LCD configuration */ 185 { 17, GPIO_IN }, /* backlight on */ 186 187 /* FFUART configuration */ 188 { 34, GPIO_ALT_FN_1_IN }, /* FFRXD */ 189 { 39, GPIO_ALT_FN_2_OUT }, /* FFTXD */ 190 191 /* BTUART configuration */ 192 { 42, GPIO_ALT_FN_1_IN }, /* BTRXD */ 193 { 43, GPIO_ALT_FN_2_OUT }, /* BTTXD */ 194 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 195 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 196 197 /* AC97 configuration */ 198 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 199 200 { -1 } 201 }; 202 203 #elif defined(OMAP2) 204 205 struct omap_mux_conf { 206 int offset; 207 uint32_t value; 208 /* OMAP3/4 register values */ 209 #define WAKEUPEVENT (1 << 15) 210 #define WAKEUPENABLE (1 << 14) 211 #define OFFMODEPULLTYPESELECT (1 << 13) 212 #define OFFMODEPULLUDENABLE (1 << 12) 213 #define OFFMODEOUTVALUE (1 << 11) 214 #define OFFMODEOUTENABLE (1 << 10) 215 #define OFFMODEENABLE (1 << 9) 216 #define INPUTENABLE (1 << 8) 217 #define PULLTYPESELECT (1 << 4) 218 #define PULLUDENABLE (1 << 3) 219 #define MUXMODE(n) ((n) & 0x7) 220 221 /* Sitara AM3xxx register values */ 222 #define SLEWCTRL (1 << 6) 223 #define RXACTIVE (1 << 5) 224 #define PUTYPESEL (1 << 4) 225 #define PUDEN (1 << 3) 226 #define MMODE(n) ((n) & 0x7) 227 }; 228 struct omap_gpio_conf { 229 int pin; 230 enum { 231 conf_input = -1, 232 conf_output_0, 233 conf_output_1, 234 } conf; 235 }; 236 237 static void gxio_omap_mux_config(const struct omap_mux_conf []); 238 static int gxio_omap_mux_config_address(const char *, unsigned long, 239 const struct omap_mux_conf[], 240 const struct omap_mux_conf[]); 241 static void gxio_omap_gpio_config(const struct omap_gpio_conf[]); 242 void gxio_omap_gpio_write(int, int); 243 244 #if defined(OVERO) 245 static const struct omap_mux_conf overo_mux_i2c3_conf[] = { 246 { 0x1c2, MUXMODE(0) | INPUTENABLE }, /* i2c3_scl */ 247 { 0x1c4, MUXMODE(0) | INPUTENABLE }, /* i2c3_sda */ 248 { -1 } 249 }; 250 #endif 251 #if defined(OVERO) 252 static const struct omap_mux_conf overo_mux_mmchs2_conf[] = { 253 { 0x158, /* mmc2_clk */ 254 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 255 { 0x15a, /* mmc2_cmd */ 256 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 257 { 0x15c, /* mmc2_dat0 */ 258 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 259 { 0x15e, /* mmc2_dat1 */ 260 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 261 { 0x160, /* mmc2_dat2 */ 262 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 263 { 0x162, /* mmc2_dat3 */ 264 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 265 { -1 } 266 }; 267 #endif 268 #if defined(OVERO) 269 static const struct omap_mux_conf overo_mux_wireless_conf[] = { 270 { 0x0b4, MUXMODE(4) }, /* gpio_54:BT_nPOWERON*/ 271 { 0x0bc, MUXMODE(4) | INPUTENABLE }, /* gpio_58: WIFI_IRQ */ 272 { 0x19c, MUXMODE(4) }, /* gpio_164:BT_nRESET */ 273 { 0x5e0, MUXMODE(4) }, /* gpio_16: W2W_nRESET*/ 274 { -1 } 275 }; 276 277 #elif defined(DUOVERO) 278 static const struct omap_mux_conf duovero_mux_led_conf[] = { 279 { 0x116, MUXMODE(3) }, /* GPIO 122 */ 280 { -1 } 281 }; 282 static const struct omap_mux_conf duovero_mux_button_conf[] = { 283 { 0x114, /* GPIO 121 */ 284 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 285 { -1 } 286 }; 287 288 #elif defined(PEPPER) 289 static const struct omap_mux_conf pepper_mux_led_conf[] = { 290 { 0x850, MMODE(7) | PUDEN }, /* GPIO 52: Blue */ 291 { 0x854, MMODE(7) | PUDEN }, /* GPIO 53: Red */ 292 { -1 } 293 }; 294 static const struct omap_mux_conf pepper_mux_button_conf[] = { 295 { 0x858, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 54 */ 296 { -1 } 297 }; 298 static const struct omap_mux_conf pepper_mux_mmchs3_conf[] = { 299 { 0x844, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT0 */ 300 { 0x848, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT1 */ 301 { 0x84c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT2 */ 302 { 0x878, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT3 */ 303 { 0x888, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CMD */ 304 { 0x88c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CLK */ 305 { -1 } 306 }; 307 static const struct omap_mux_conf pepper_mux_audio_codec_conf[] = { 308 { 0x840, MMODE(7) | PUDEN }, /* GPIO 48: #Reset */ 309 { -1 } 310 }; 311 #endif 312 313 #endif 314 315 static const struct gxioconf gxioconflist[] = { 316 #if defined(GUMSTIX) 317 { "basix", basix_config }, 318 { "cfstix", cfstix_config }, 319 { "etherstix", etherstix_config }, 320 { "netcf", netcf_config }, 321 { "netcf-vx", netcf_vx_config }, 322 { "netduo-mmc", netduommc_config }, 323 { "netduo", netduo_config }, 324 { "netmicrosd", netmicrosd_config }, 325 { "netmicrosd-vx", netmicrosd_config }, 326 { "netwifimicrosd", netwifimicrosd_config }, 327 { "netmmc", netmmc_config }, 328 { "netpro-vx", netwifimicrosd_config }, 329 { "wifistix-cf", wifistix_cf_config }, 330 { "wifistix", wifistix_config }, 331 #elif defined(OVERO) 332 { "chestnut43", chestnut_config }, 333 { "gallop43", gallop_config }, 334 { "summit", summit_config }, 335 { "tobi", tobi_config }, 336 { "tobi-duo", tobiduo_config }, 337 #elif defined(DUOVERO) 338 { "parlor", parlor_config }, 339 #elif defined(PEPPER) 340 { "43c", c_config }, 341 { "43r", r_config }, 342 { "dvi", dvi_config }, 343 #endif 344 { NULL } 345 }; 346 347 int gxpcic_gpio_reset; 348 struct gxpcic_slot_irqs gxpcic_slot_irqs[2] = { { 0, -1, -1 }, { 0, -1, -1 } }; 349 350 351 #if defined(GUMSTIX) 352 /* ARGSUSED */ 353 static int 354 gxiomatch(device_t parent, cfdata_t match, void *aux) 355 { 356 357 struct pxaip_attach_args *pxa = aux; 358 bus_space_tag_t iot = &pxa2x0_bs_tag; 359 bus_space_handle_t ioh; 360 361 if (strcmp(pxa->pxa_name, match->cf_name) != 0 || 362 pxa->pxa_addr != PXAIPCF_ADDR_DEFAULT) 363 return 0; 364 365 if (bus_space_map(iot, 366 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &ioh)) 367 return 0; 368 bus_space_unmap(iot, ioh, PXA2X0_MEMCTL_SIZE); 369 370 /* nothing */ 371 return 1; 372 } 373 374 /* ARGSUSED */ 375 static void 376 gxioattach(device_t parent, device_t self, void *aux) 377 { 378 struct gxio_softc *sc = device_private(self); 379 380 aprint_normal("\n"); 381 aprint_naive("\n"); 382 383 sc->sc_dev = self; 384 sc->sc_iot = &pxa2x0_bs_tag; 385 386 if (bus_space_map(sc->sc_iot, 387 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &sc->sc_ioh)) 388 return; 389 390 /* 391 * Attach each gumstix(busheader)/overo expansion board devices. 392 */ 393 config_search(self, NULL, 394 CFARG_SEARCH, gxiosearch, 395 CFARG_EOL); 396 } 397 398 /* ARGSUSED */ 399 static int 400 gxiosearch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 401 { 402 struct gxio_softc *sc = device_private(parent); 403 struct gxio_attach_args gxa; 404 405 gxa.gxa_sc = sc; 406 gxa.gxa_iot = sc->sc_iot; 407 gxa.gxa_addr = cf->cf_loc[GXIOCF_ADDR]; 408 gxa.gxa_gpirq = cf->cf_loc[GXIOCF_GPIRQ]; 409 410 if (config_probe(parent, cf, &gxa)) 411 config_attach(parent, cf, &gxa, gxioprint, CFARG_EOL); 412 413 return 0; 414 } 415 416 /* ARGSUSED */ 417 static int 418 gxioprint(void *aux, const char *name) 419 { 420 struct gxio_attach_args *gxa = (struct gxio_attach_args *)aux; 421 422 if (gxa->gxa_addr != GXIOCF_ADDR_DEFAULT) 423 printf(" addr 0x%lx", gxa->gxa_addr); 424 if (gxa->gxa_gpirq > 0) 425 printf(" gpirq %d", gxa->gxa_gpirq); 426 return UNCONF; 427 } 428 #endif 429 430 431 #if defined(GUMSTIX) 432 /* 433 * configure for GPIO pin and expansion boards. 434 */ 435 void 436 gxio_config(void) 437 { 438 #if defined(CPU_XSCALE_PXA250) 439 struct pxa2x0_gpioconf *gumstix_gpioconf[] = { 440 pxa25x_com_ffuart_gpioconf, 441 pxa25x_com_stuart_gpioconf, 442 #ifndef GXIO_BLUETOOTH_ON_HWUART 443 pxa25x_com_btuart_gpioconf, 444 #endif 445 pxa25x_com_hwuart_gpioconf, 446 pxa25x_i2c_gpioconf, 447 pxa25x_pxaacu_gpioconf, 448 pxa255dep_gpioconf, 449 NULL 450 }; 451 #endif 452 #if defined(CPU_XSCALE_PXA270) 453 struct pxa2x0_gpioconf *verdex_gpioconf[] = { 454 pxa27x_com_ffuart_gpioconf, 455 pxa27x_com_stuart_gpioconf, 456 pxa27x_com_btuart_gpioconf, 457 pxa27x_i2c_gpioconf, 458 pxa27x_pxaacu_gpioconf, 459 pxa27x_pxamci_gpioconf, 460 pxa27x_ohci_gpioconf, 461 verdexdep_gpioconf, 462 NULL 463 }; 464 #endif 465 466 /* XXX: turn off for power of bluetooth module */ 467 #if defined(CPU_XSCALE_PXA250) 468 pxa2x0_gpio_set_function(7, GPIO_OUT | GPIO_CLR); 469 #elif defined(CPU_XSCALE_PXA270) 470 pxa2x0_gpio_set_function(12, GPIO_OUT | GPIO_CLR); 471 #endif 472 delay(100); 473 474 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 475 pxa2x0_gpio_config( 476 (CPU_IS_PXA250) ? gumstix_gpioconf : verdex_gpioconf); 477 #elif defined(CPU_XSCALE_PXA270) || defined(CPU_XSCALE_PXA250) 478 #if defined(CPU_XSCALE_PXA270) 479 pxa2x0_gpio_config(verdex_gpioconf); 480 #else 481 pxa2x0_gpio_config(gumstix_gpioconf); 482 #endif 483 #endif 484 } 485 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 486 static void 487 gxio_omap_mux_config(const struct omap_mux_conf mux_conf[]) 488 { 489 #if defined(OVERO) 490 const vaddr_t ctrlmod_base = OVERO_L4_CORE_VBASE + 0x2000; 491 #elif defined(DUOVERO) 492 const vaddr_t ctrlmod_base = DUOVERO_L4_CM_VBASE; 493 #elif defined(PEPPER) 494 const vaddr_t ctrlmod_base = PEPPER_PRCM_VBASE + 0x10000; 495 #endif 496 int i; 497 498 for (i = 0; mux_conf[i].offset != -1; i++) 499 #if !defined(TI_AM335X) 500 ioreg16_write(ctrlmod_base + mux_conf[i].offset, 501 mux_conf[i].value); 502 #else 503 ioreg_write(ctrlmod_base + mux_conf[i].offset, 504 mux_conf[i].value); 505 #endif 506 } 507 508 static int 509 gxio_omap_mux_config_address(const char *name, unsigned long address, 510 const struct omap_mux_conf mux_conf[], 511 const struct omap_mux_conf not_mux_conf[]) 512 { 513 extern struct cfdata cfdata[]; 514 cfdata_t cf = &cfdata[0]; 515 516 while (cf->cf_name != NULL) { 517 if (strcmp(name, cf->cf_name) == 0 && 518 address == cf->cf_loc[OBIOCF_ADDR]) { 519 gxio_omap_mux_config(mux_conf); 520 return 0; 521 } 522 cf++; 523 } 524 525 if (not_mux_conf == NULL) 526 return -1; 527 528 gxio_omap_mux_config(not_mux_conf); 529 return 0; 530 } 531 532 #if defined(OVERO) 533 #define gpio_reg_read ioreg_read 534 #define gpio_reg_write ioreg_write 535 #elif defined(DUOVERO) || defined(PEPPER) 536 #define gpio_reg_read(a) ioreg_read((a) + GPIO_SIZE2) 537 #define gpio_reg_write(a, v) ioreg_write((a) + GPIO_SIZE2, (v)) 538 #endif 539 540 static const vaddr_t gpio_bases[] = { 541 #if defined(OVERO) 542 #define OVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 543 #define GPIO(n) GPIO ## n ## _BASE_3530 544 #define BASE(a, n) \ 545 (OVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP3530_L4_ ## a ## _BASE)) 546 547 GPIO1_BASE_3530, 548 GPIO2_BASE_3530, 549 GPIO3_BASE_3530, 550 GPIO4_BASE_3530, 551 GPIO5_BASE_3530, 552 GPIO6_BASE_3530, 553 554 #elif defined(DUOVERO) 555 #define DUOVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 556 #define GPIO(n) GPIO ## n ## _BASE_4430 557 #define BASE(a, n) \ 558 (DUOVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP4430_L4_ ## a ## _BASE)) 559 560 DUOVERO_GPIO_VBASE(1), 561 DUOVERO_GPIO_VBASE(2), 562 DUOVERO_GPIO_VBASE(3), 563 DUOVERO_GPIO_VBASE(4), 564 DUOVERO_GPIO_VBASE(5), 565 566 #elif defined(PEPPER) 567 #define PEPPER_GPIO_VBASE(n) ((n) == 0 ? WAKEUP(n) : PERIPHERAL(n)) 568 #define GPIO(n) GPIO ## n ## _BASE_TI_AM335X 569 #define WAKEUP(n) (PEPPER_PRCM_VBASE + (GPIO(n) - OMAP2_CM_BASE)) 570 #define PERIPHERAL(n) \ 571 (PEPPER_L4_PERIPHERAL_VBASE + (GPIO(n) - TI_AM335X_L4_PERIPHERAL_BASE)) 572 573 PEPPER_GPIO_VBASE(0), 574 PEPPER_GPIO_VBASE(1), 575 PEPPER_GPIO_VBASE(2), 576 PEPPER_GPIO_VBASE(3), 577 #endif 578 }; 579 580 static void 581 gxio_omap_gpio_config(const struct omap_gpio_conf gpio_conf[]) 582 { 583 vaddr_t gpio_base; 584 int mask, i; 585 586 for (i = 0; gpio_conf[i].pin != -1; i++) { 587 gpio_base = gpio_bases[gpio_conf[i].pin / 32]; 588 mask = 1 << (gpio_conf[i].pin % 32); 589 switch (gpio_conf[i].conf) { 590 case conf_input: 591 ioreg_write(gpio_base + GPIO_OE, 592 ioreg_read(gpio_base + GPIO_OE) | mask); 593 break; 594 case conf_output_0: 595 ioreg_write(gpio_base + GPIO_OE, 596 ioreg_read(gpio_base + GPIO_OE) | ~mask); 597 #if 0 598 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 599 #else 600 ioreg_write(gpio_base + GPIO_DATAOUT, 601 ioreg_read(gpio_base + GPIO_DATAOUT) & ~mask); 602 #endif 603 break; 604 case conf_output_1: 605 ioreg_write(gpio_base + GPIO_OE, 606 ioreg_read(gpio_base + GPIO_OE) | ~mask); 607 #if 0 608 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 609 #else 610 ioreg_write(gpio_base + GPIO_DATAOUT, 611 ioreg_read(gpio_base + GPIO_DATAOUT) | mask); 612 #endif 613 break; 614 } 615 } 616 } 617 618 void 619 gxio_omap_gpio_write(int pin, int val) 620 { 621 vaddr_t gpio_base; 622 int mask; 623 624 KASSERT(pin / 32 < __arraycount(gpio_bases)); 625 626 gpio_base = gpio_bases[pin / 32]; 627 mask = 1 << (pin % 32); 628 if (val == 0) 629 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 630 else 631 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 632 } 633 634 /* 635 * configure for MUX, GPIO. 636 */ 637 void 638 gxio_config(void) 639 { 640 const struct omap_mux_conf *mux_conf[] = { 641 #if defined(OVERO) 642 overo_mux_i2c3_conf, 643 overo_mux_mmchs2_conf, 644 overo_mux_wireless_conf, 645 #elif defined(DUOVERO) 646 duovero_mux_led_conf, 647 duovero_mux_button_conf, 648 #elif defined(PEPPER) 649 pepper_mux_led_conf, 650 pepper_mux_button_conf, 651 pepper_mux_mmchs3_conf, 652 pepper_mux_audio_codec_conf, 653 #endif 654 }; 655 const struct omap_gpio_conf gpio_conf[] = { 656 #if defined(OVERO) 657 { 16, conf_output_0 }, /* Wireless: #Reset */ 658 #elif defined(PEPPER) 659 { 48, conf_output_0 }, /* Audio Codec: #Reset */ 660 #endif 661 { -1 } 662 }; 663 int i; 664 665 for (i = 0; i < __arraycount(mux_conf); i++) 666 gxio_omap_mux_config(mux_conf[i]); 667 gxio_omap_gpio_config(gpio_conf); 668 } 669 #endif 670 671 static int 672 gxio_find_default_expansion(void) 673 { 674 #ifdef GXIO_DEFAULT_EXPANSION 675 int i; 676 677 /* Find out the default expansion */ 678 for (i = 0; gxioconflist[i].name != NULL; i++) 679 if (strncasecmp(gxioconflist[i].name, GXIO_DEFAULT_EXPANSION, 680 strlen(gxioconflist[i].name) + 1) == 0) 681 break; 682 return gxioconflist[i].name == NULL ? -1 : i; 683 #else 684 return -1; 685 #endif 686 } 687 688 void 689 gxio_config_expansion(const char *expansion) 690 { 691 int i, d; 692 693 d = gxio_find_default_expansion(); 694 695 /* Print information about expansions */ 696 printf("supported expansions:\n"); 697 for (i = 0; gxioconflist[i].name != NULL; i++) 698 printf(" %s%s\n", gxioconflist[i].name, 699 i == d ? " (DEFAULT)" : ""); 700 701 702 if (expansion == NULL) { 703 printf("not specified 'expansion=' in the boot args.\n"); 704 i = -1; 705 } else { 706 for (i = 0; gxioconflist[i].name != NULL; i++) 707 if (strncasecmp(gxioconflist[i].name, expansion, 708 strlen(gxioconflist[i].name) + 1) == 0) 709 break; 710 if (gxioconflist[i].name == NULL) { 711 printf("unknown expansion specified: %s\n", expansion); 712 i = -1; 713 } 714 } 715 716 /* Do some magic stuff for PEPPER */ 717 #if defined(PEPPER) 718 if (i < 0) { 719 struct pepper_board_id { 720 unsigned int device_vendor; 721 #define GUMSTIX_PEPPER 0x30000200 /* 1st gen */ 722 #define GUMSTIX_PEPPER_DVI 0x31000200 /* DVI and newer */ 723 unsigned char revision; 724 unsigned char content; 725 char fab_revision[8]; 726 char env_var[16]; 727 char env_setting[64]; 728 } id; 729 const vaddr_t i2c_base = PEPPER_PRCM_VBASE + 0xb000; 730 const uint8_t eeprom = 0x50; 731 const uint8_t len = sizeof(id); 732 int rv; 733 734 rv = read_i2c_device(i2c_base, eeprom, 0x00, len, (void *)&id); 735 if (rv == 0) 736 if (id.device_vendor == GUMSTIX_PEPPER) { 737 printf("configure auto detected expansion" 738 " (pepper)\n"); 739 pepper_config(); 740 return; 741 } 742 } 743 #endif 744 745 /* 746 * Now proceed to configure the default expansion if one was 747 * specified (and found) or return. 748 */ 749 const char *toconfigure; 750 if (i < 0) { 751 #ifdef GXIO_DEFAULT_EXPANSION 752 if (d == -1) { 753 printf("default expansion (%s) not found\n", 754 GXIO_DEFAULT_EXPANSION); 755 return; 756 } 757 expansion = GXIO_DEFAULT_EXPANSION; 758 i = d; 759 toconfigure = "default"; 760 #else 761 return; 762 #endif 763 } else 764 toconfigure = "specified"; 765 766 printf("configure %s expansion (%s)\n", toconfigure, expansion); 767 gxioconflist[i].config(); 768 } 769 770 771 #if defined(GUMSTIX) 772 773 static void 774 basix_config(void) 775 { 776 777 pxa2x0_gpio_set_function(8, GPIO_ALT_FN_1_OUT); /* MMCCS0 */ 778 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_1_OUT); /* MMCCLK */ 779 #if 0 780 /* this configuration set by gxmci.c::pxamci_attach() */ 781 pxa2x0_gpio_set_function(11, GPIO_IN); /* nSD_DETECT */ 782 pxa2x0_gpio_set_function(22, GPIO_IN); /* nSD_WP */ 783 #endif 784 } 785 786 static void 787 cfstix_config(void) 788 { 789 u_int gpio, npoe_fn; 790 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 791 int bvd = (CPU_IS_PXA250) ? 4 : 111; 792 #else 793 #if defined(CPU_XSCALE_PXA270) 794 const int bvd = 111; 795 #else 796 const int bvd = 4; 797 #endif 798 #endif 799 800 if (CPU_IS_PXA250) { 801 gxpcic_slot_irqs[0].valid = 1; 802 gxpcic_slot_irqs[0].cd = 11; 803 gxpcic_slot_irqs[0].prdy = 26; 804 gxpcic_gpio_reset = 8; 805 } else { 806 gxpcic_slot_irqs[0].valid = 1; 807 gxpcic_slot_irqs[0].cd = 104; 808 gxpcic_slot_irqs[0].prdy = 96; 809 gxpcic_gpio_reset = 97; 810 } 811 812 #if 1 813 /* PCD/PRDY set by pxa2x0_pcic.c::pxapcic_attach_common() */ 814 #else 815 pxa2x0_gpio_set_function(11, GPIO_IN); /* PCD1 */ 816 pxa2x0_gpio_set_function(26, GPIO_IN); /* PRDY1/~IRQ1 */ 817 #endif 818 pxa2x0_gpio_set_function(bvd, GPIO_IN); /* BVD1/~STSCHG1 */ 819 820 for (gpio = 48, npoe_fn = 0; gpio <= 53 ; gpio++) 821 npoe_fn |= pxa2x0_gpio_get_function(gpio); 822 npoe_fn &= GPIO_SET; 823 824 pxa2x0_gpio_set_function(48, GPIO_ALT_FN_2_OUT | npoe_fn); /* nPOE */ 825 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 826 pxa2x0_gpio_set_function(50, GPIO_ALT_FN_2_OUT); /* nPIOR */ 827 pxa2x0_gpio_set_function(51, GPIO_ALT_FN_2_OUT); /* nPIOW */ 828 if (CPU_IS_PXA250) { 829 pxa2x0_gpio_set_function(52, GPIO_ALT_FN_2_OUT); /* nPCE1 */ 830 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_2_OUT); /* nPCE2 */ 831 pxa2x0_gpio_set_function(54, GPIO_ALT_FN_2_OUT); /* pSKTSEL */ 832 } else { 833 pxa2x0_gpio_set_function(102, GPIO_ALT_FN_1_OUT); /* nPCE1 */ 834 pxa2x0_gpio_set_function(105, GPIO_ALT_FN_1_OUT); /* nPCE2 */ 835 pxa2x0_gpio_set_function(79, GPIO_ALT_FN_1_OUT); /* pSKTSEL */ 836 } 837 pxa2x0_gpio_set_function(55, GPIO_ALT_FN_2_OUT); /* nPREG */ 838 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); /* nPWAIT */ 839 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); /* nIOIS16 */ 840 } 841 842 static void 843 etherstix_config(void) 844 { 845 extern struct cfdata cfdata[]; 846 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 847 int rst = (CPU_IS_PXA250) ? 80 : 32; 848 int irq = (CPU_IS_PXA250) ? 36 : 99; 849 #else 850 #if defined(CPU_XSCALE_PXA270) 851 const int rst = 32, irq = 99; 852 #else 853 const int rst = 80, irq = 36; 854 #endif 855 #endif 856 int i; 857 858 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 859 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 860 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_SET); /* RESET 1 */ 861 delay(1); 862 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_CLR); 863 delay(50000); 864 865 for (i = 0; cfdata[i].cf_name != NULL; i++) 866 if (strcmp(cfdata[i].cf_name, "sm") == 0 && 867 strcmp(cfdata[i].cf_atname, "sm_gxio") == 0 && 868 cfdata[i].cf_loc[GXIOCF_ADDR] == 0x04000300 && 869 cfdata[i].cf_loc[GXIOCF_GPIRQ] == GXIOCF_GPIRQ_DEFAULT) 870 cfdata[i].cf_loc[GXIOCF_GPIRQ] = irq; 871 } 872 873 static void 874 netcf_config(void) 875 { 876 877 etherstix_config(); 878 cfstix_config(); 879 } 880 881 static void 882 netcf_vx_config(void) 883 { 884 885 /* 886 * XXXX: More power is necessary for NIC and USB??? 887 * (no document. from Linux) 888 */ 889 890 pxa2x0_gpio_set_function(27, GPIO_IN); 891 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); 892 pxa2x0_gpio_set_function(118, GPIO_ALT_FN_1_IN | GPIO_CLR); 893 894 etherstix_config(); 895 cfstix_config(); 896 if (CPU_IS_PXA270) { 897 /* Overwrite */ 898 gxpcic_slot_irqs[0].cd = 104; 899 gxpcic_slot_irqs[0].prdy = 109; 900 gxpcic_gpio_reset = 110; 901 }; 902 } 903 904 static void 905 netduommc_config(void) 906 { 907 908 netduo_config(); 909 basix_config(); 910 } 911 912 static void 913 netduo_config(void) 914 { 915 916 etherstix_config(); 917 918 pxa2x0_gpio_set_function(78, GPIO_ALT_FN_2_OUT); /* nCS 2 */ 919 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_SET); /* RESET 2 */ 920 delay(1); 921 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_CLR); 922 delay(50000); 923 } 924 925 static void 926 netmicrosd_config(void) 927 { 928 929 /* MicroSD(mci) always configure on PXA270 */ 930 931 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 932 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 933 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); /* RESET 1 */ 934 delay(hz / 2); 935 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_SET); 936 delay(50000); 937 } 938 939 static void 940 netwifimicrosd_config(void) 941 { 942 943 netmicrosd_config(); 944 945 cfstix_config(); 946 /* However use pxamci. */ 947 pxa2x0_gpio_set_function(111, GPIO_CLR | GPIO_ALT_FN_1_IN); 948 /* Power to Marvell 88W8385 */ 949 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 950 } 951 952 static void 953 netmmc_config(void) 954 { 955 956 etherstix_config(); 957 basix_config(); 958 } 959 960 static void 961 wifistix_config(void) 962 { 963 964 cfstix_config(); 965 966 /* Power to Marvell 88W8385 */ 967 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 968 } 969 970 static void 971 wifistix_cf_config(void) 972 { 973 974 gxpcic_slot_irqs[1].valid = 1; 975 gxpcic_slot_irqs[1].cd = 36; 976 gxpcic_slot_irqs[1].prdy = 27; 977 978 #if 1 979 /* this configuration set by pxa2x0_pcic.c::pxapcic_attach_common() */ 980 #else 981 pxa2x0_gpio_set_function(36, GPIO_IN); /* PCD2 */ 982 pxa2x0_gpio_set_function(27, GPIO_IN); /* PRDY2/~IRQ2 */ 983 #endif 984 pxa2x0_gpio_set_function(18, GPIO_IN); /* BVD2/~STSCHG2 */ 985 986 cfstix_config(); 987 988 /* Power to Marvell 88W8385 */ 989 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 990 } 991 992 #elif defined(OVERO) 993 994 static void 995 eth0_config(void) 996 { 997 /* 998 * ETH0 connects via CS5. It use GPIO 176 for IRQ. 999 * Also GPIO 64 is NRESET. 1000 */ 1001 1002 smsh_config(NULL, 176, 64); 1003 } 1004 1005 static void 1006 eth1_config(void) 1007 { 1008 struct omap_mux_conf eth1_mux_conf[] = { 1009 { 0x0d2, MUXMODE(4) | INPUTENABLE }, 1010 { -1 } 1011 }; 1012 1013 /* 1014 * ETH1 connects via CS4. It use GPIO 65 for IRQ. 1015 */ 1016 1017 smsh_config(eth1_mux_conf, 65, 64); 1018 } 1019 1020 static void 1021 dvi_config(void) 1022 { 1023 static const struct omap_mux_conf overo_mux_dvi_conf[] = { 1024 { 0x0d4, MUXMODE(0) }, /* dss_pclk */ 1025 { 0x0d6, MUXMODE(0) }, /* dss_pclk */ 1026 { 0x0d8, MUXMODE(0) }, /* dss_pclk */ 1027 { 0x0da, MUXMODE(0) }, /* dss_pclk */ 1028 { 0x0dc, MUXMODE(0) }, /* dss_pclk */ 1029 { 0x0de, MUXMODE(0) }, /* dss_pclk */ 1030 { 0x0e0, MUXMODE(0) }, /* dss_pclk */ 1031 { 0x0e2, MUXMODE(0) }, /* dss_pclk */ 1032 { 0x0e4, MUXMODE(0) }, /* dss_pclk */ 1033 { 0x0e6, MUXMODE(0) }, /* dss_pclk */ 1034 { 0x0e8, MUXMODE(0) }, /* dss_pclk */ 1035 { 0x0ea, MUXMODE(0) }, /* dss_pclk */ 1036 { 0x0ec, MUXMODE(0) }, /* dss_pclk */ 1037 { 0x0ee, MUXMODE(0) }, /* dss_pclk */ 1038 { 0x0f0, MUXMODE(0) }, /* dss_pclk */ 1039 { 0x0f2, MUXMODE(0) }, /* dss_pclk */ 1040 { 0x0f4, MUXMODE(0) }, /* dss_pclk */ 1041 { 0x0f6, MUXMODE(0) }, /* dss_pclk */ 1042 { 0x0f8, MUXMODE(0) }, /* dss_pclk */ 1043 { 0x0fa, MUXMODE(0) }, /* dss_pclk */ 1044 { 0x0fc, MUXMODE(0) }, /* dss_pclk */ 1045 { 0x0fe, MUXMODE(0) }, /* dss_pclk */ 1046 { 0x100, MUXMODE(0) }, /* dss_pclk */ 1047 { 0x102, MUXMODE(0) }, /* dss_pclk */ 1048 { 0x104, MUXMODE(0) }, /* dss_pclk */ 1049 { 0x106, MUXMODE(0) }, /* dss_pclk */ 1050 { 0x108, MUXMODE(0) }, /* dss_pclk */ 1051 { 0x10a, MUXMODE(0) }, /* dss_pclk */ 1052 { -1 } 1053 }; 1054 1055 gxio_omap_mux_config(overo_mux_dvi_conf); 1056 } 1057 1058 static void 1059 lcd_config(char type) 1060 { 1061 static const struct omap_mux_conf overo_mux_mcspi1_conf[] = { 1062 { 0x1c8, MUXMODE(0) | INPUTENABLE }, /* mcspi1_clk */ 1063 { 0x1ca, MUXMODE(0) | INPUTENABLE }, /* mcspi1_simo*/ 1064 { 0x1cc, MUXMODE(0) | INPUTENABLE }, /* mcspi1_somi*/ 1065 { 0x1ce, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs0 */ 1066 { 0x1d0, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs1 */ 1067 { -1 } 1068 }; 1069 static const struct omap_mux_conf overo_mux_ads7846_conf[] = { 1070 { 0x138, /* gpio_114: NPENIRQ */ 1071 MUXMODE(4) | PULLUDENABLE | INPUTENABLE }, 1072 { -1 } 1073 }; 1074 static const struct omap_mux_conf overo_mux_lcd_conf[] = { 1075 { 0x174, MUXMODE(4) }, /* gpio_144: DISPLAY_EN */ 1076 { 0x176, MUXMODE(4) }, /* gpio_145: Brightness */ 1077 { -1 } 1078 }; 1079 1080 static const struct omap_gpio_conf overo_gpio_lcd_conf[] = { 1081 { 144, conf_output_0 }, /* DISPLAY_EN */ 1082 { 145, conf_output_0 }, /* Brightness */ 1083 { -1 } 1084 }; 1085 1086 dvi_config(); 1087 if (type != 'C') { 1088 gxio_omap_mux_config(overo_mux_mcspi1_conf); 1089 gxio_omap_mux_config(overo_mux_ads7846_conf); 1090 } 1091 gxio_omap_mux_config(overo_mux_lcd_conf); 1092 1093 gxio_omap_gpio_config(overo_gpio_lcd_conf); 1094 } 1095 1096 enum { 1097 uart1_if_exists = 0, 1098 force_uart1 1099 }; 1100 static void 1101 header_40pin_config(int uart1) 1102 { 1103 static const struct omap_mux_conf overo_mux_40pin_header_conf[] = { 1104 /* 1105 * 1: GND 1106 * 2: VCC_3.3 1107 * 3: GPIO171_SPI1_CLK 1108 * 4: GPIO114_SPI1_NIRQ 1109 * 5: GPIO172_SPI1_MOSI 1110 * 6: GPIO174_SPI1_CS0 1111 * 7: GPIO173_SPI1_MISO 1112 * 8: GPIO175_SPI1_CS1 1113 * 9: GPIO151_RXD1 1114 * 10: GPIO148_TXD1 1115 * 11: SYS_EN 1116 * 12: VBACKUP 1117 * 13: GPIO0_WAKEUP 1118 * 14: POWERON 1119 * 15: GND 1120 * 16: VCC_1.8 1121 * 17: GPIO128_GPS_PPS 1122 * 18: GPIO127_TS_IRQ 1123 * 19: GPIO170_HDQ_1WIRE 1124 * 20: GPIO163_IR_CTS3 1125 * 21: GPIO165_IR_RXD3 (console) 1126 * 22: GPIO166_IR_TXD3 (console) 1127 * 23: GPIO184_SCL3 (system eeprom) 1128 * 24: GPIO185_SDA3 (system eeprom) 1129 * 25: GND 1130 * 26: VCC_1.8 1131 * 27: GPIO146_PWM11 1132 * 28: GPIO145_PWM10 1133 * 29: GPIO147_PWM8 1134 * 30: GPIO144_PWM9 1135 * 31: PWM0 (TPS65950) 1136 * 32: PWM1 (TPS65950) 1137 * 33: ADCIN7 (TPS65950) 1138 * 34: ADCIN2 (TPS65950) 1139 * 35: ADCIN6 (TPS65950) 1140 * 36: ADCIN5 (TPS65950) 1141 * 37: AGND (TPS65950) 1142 * 38: ADCIN3 (TPS65950) 1143 * 39: ADCIN4 (TPS65950) 1144 * 40: VIN (TPS65950) 1145 */ 1146 1147 { 0x152, MUXMODE(4) | INPUTENABLE }, /* gpio_127 */ 1148 { 0x154, MUXMODE(4) | INPUTENABLE }, /* gpio_128 */ 1149 { 0x174, MUXMODE(4) | INPUTENABLE }, /* gpio_144 */ 1150 { 0x176, MUXMODE(4) | INPUTENABLE }, /* gpio_145 */ 1151 { 0x178, MUXMODE(4) | INPUTENABLE }, /* gpio_146 */ 1152 { 0x17a, MUXMODE(4) | INPUTENABLE }, /* gpio_147 */ 1153 { 0x19a, MUXMODE(4) | INPUTENABLE }, /* gpio_163 */ 1154 { -1 } 1155 }; 1156 static const struct omap_mux_conf overo_mux_uart1_conf[] = { 1157 { 0x17c, MUXMODE(0) }, /* uart1_tx */ 1158 { 0x182, MUXMODE(0) | INPUTENABLE }, /* uart1_rx */ 1159 { -1 } 1160 }; 1161 static const struct omap_mux_conf overo_mux_no_uart1_conf[] = { 1162 { 0x17c, MUXMODE(4) | INPUTENABLE }, /* gpio_148 */ 1163 { 0x182, MUXMODE(4) | INPUTENABLE }, /* gpio_151 */ 1164 { -1 } 1165 }; 1166 static const struct omap_mux_conf overo_mux_hdq_conf[] = { 1167 #if 0 1168 { 0x1c4, MUXMODE(0) | ??? | INPUTENABLE }, /* hdq_sio */ 1169 #endif 1170 { -1 } 1171 }; 1172 static const struct omap_mux_conf overo_mux_no_hdq_conf[] = { 1173 { 0x1c4, MUXMODE(4) | INPUTENABLE }, /* gpio_170 */ 1174 { -1 } 1175 }; 1176 1177 gxio_omap_mux_config(overo_mux_40pin_header_conf); 1178 if (uart1 == force_uart1) 1179 gxio_omap_mux_config(overo_mux_uart1_conf); 1180 else 1181 gxio_omap_mux_config_address("com", 0x4806a000, 1182 overo_mux_uart1_conf, overo_mux_no_uart1_conf); 1183 gxio_omap_mux_config_address("hdq", 0x480b2000, 1184 overo_mux_hdq_conf, overo_mux_no_hdq_conf); 1185 } 1186 1187 static void 1188 chestnut_config(void) 1189 { 1190 static const struct omap_mux_conf chestnut_mux_conf[] = { 1191 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1192 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1193 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1194 { -1 } 1195 }; 1196 1197 eth0_config(); 1198 lcd_config('R'); 1199 1200 header_40pin_config(uart1_if_exists); 1201 gxio_omap_mux_config(chestnut_mux_conf); 1202 } 1203 1204 static void 1205 gallop_config(void) 1206 { 1207 static const struct omap_mux_conf gallop43_mux_conf[] = { 1208 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1209 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1210 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1211 { -1 } 1212 }; 1213 1214 lcd_config('R'); 1215 1216 header_40pin_config(force_uart1); 1217 gxio_omap_mux_config(gallop43_mux_conf); 1218 } 1219 1220 static void 1221 summit_config(void) 1222 { 1223 1224 dvi_config(); 1225 1226 header_40pin_config(uart1_if_exists); 1227 } 1228 1229 static void 1230 tobi_config(void) 1231 { 1232 1233 eth0_config(); 1234 dvi_config(); 1235 1236 header_40pin_config(uart1_if_exists); 1237 } 1238 1239 static void 1240 tobiduo_config(void) 1241 { 1242 1243 eth0_config(); 1244 eth1_config(); 1245 } 1246 1247 #elif defined(DUOVERO) 1248 1249 static void 1250 ehci_config(void) 1251 { 1252 uint32_t val; 1253 1254 #define SCRM_ALTCLKSRC 0xa110 1255 #define ALTCLKSRC_ENABLE_EXT (1 << 3) 1256 #define ALTCLKSRC_ENABLE_INT (1 << 2) 1257 #define ALTCLKSRC_MODE_MASK (3 << 0) 1258 #define ALTCLKSRC_MODE_POWERDOWN (0 << 0) 1259 #define ALTCLKSRC_MODE_ACTIVE (1 << 0) 1260 #define ALTCLKSRC_MODE_BYPASS (2 << 0) 1261 #define SCRM_AUXCLK3 0xa31c 1262 #define AUXCLK3_CLKDIV(n) (((n) - 1) << 16) 1263 #define AUXCLK3_CLKDIV_MASK (0xf << 16) 1264 #define AUXCLK3_ENABLE (1 << 8) 1265 #define AUXCLK3_SRCSELECT_MASK (3 << 1) 1266 #define AUXCLK3_SRCSELECT_SYSCLK (0 << 1) 1267 #define AUXCLK3_SRCSELECT_CORE (1 << 1) 1268 #define AUXCLK3_SRCSELECT_PERDPLL (2 << 1) 1269 #define AUXCLK3_SRCSELECT_ALTCLK (3 << 1) 1270 #define AUXCLK3_POLARITY_LOW (0 << 0) 1271 #define AUXCLK3_POLARITY_HIGH (1 << 0) 1272 1273 /* Use the 1/2 auxiliary clock #3 of system clock. */ 1274 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3); 1275 val &= ~(AUXCLK3_CLKDIV_MASK | AUXCLK3_SRCSELECT_MASK); 1276 val |= (AUXCLK3_CLKDIV(2) | AUXCLK3_ENABLE | AUXCLK3_SRCSELECT_SYSCLK); 1277 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3, val); 1278 1279 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC); 1280 val &= ~ALTCLKSRC_MODE_MASK; 1281 val |= ALTCLKSRC_MODE_ACTIVE; 1282 val |= (ALTCLKSRC_ENABLE_EXT | ALTCLKSRC_ENABLE_INT); 1283 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC, val); 1284 } 1285 1286 static void 1287 parlor_config(void) 1288 { 1289 #if 0 1290 static const struct omap_mux_conf parlor_mux_40pin_header_conf[] = { 1291 /* 1292 * 1: GND 1293 * 2: GND 1294 * 3: MCSPI1_CLK or GPIO 134 1295 * 4: MCSPI1_CS0 or GPIO 137 1296 * 5: MCSPI1_SIMO or GPIO 136 1297 * 6: MCSPI1_CS1 or GPIO 138 1298 * 7: MCSPI1_SOMI or GPIO 135 1299 * 8: MCSPI1_CS2 or GPIO 139 1300 * 9: HDQ_SIO or GPIO 127 1301 * 10: MCSPI1_CS3 or GPIO 140 1302 * 11: SDMMC3_CMD or GPIO ??? 1303 * 12: I2C2_SCL or GPIO 128 1304 * 13: SDMMC3_CLK or GPIO ??? 1305 * 14: I2C2_SDA or GPIO 129 1306 * 15: UART2_TX or SDMMC3_DAT1 or GPIO 126 1307 * 16: PMIC_PWM2 (TWL6030) 1308 * 17: UART2_RX or SDMMC3_DAT0 or GPIO 125 1309 * 18: PMIC_PWM1 (TWL6030) 1310 * 19: BSP2_CLKX or GPIO 110 1311 * 20: BSP2_FSX or GPIO 113 1312 * 21: BSP2_DX or GPIO 112 1313 * 22: BSP2_DR or GPIO 111 1314 * 23: BSP2_CLKS or GPIO 118 1315 * 24: FREF1 1316 * 25: MCSPI4_SOMI or GPIO 153 1317 * 26: PMIC_NRESWARN 1318 * 27: MCSPI4_SIMO or GPIO 152 1319 * 28: SYSEN 1320 * 29: MCSPI4_CLK or GPIO 151 1321 * 30: PWRON 1322 * 31: MCSPI4_CS0 or GPIO 154 1323 * 32: REGEN1 1324 * 33: ADCIN3 (TWL6030) 1325 * 34: VCC_1.0 1326 * 35: ADCIN4_VREF (TWL6030) 1327 * 36: VDD_VAUX2 1328 * 37: ADCIN4 (TWL6030) 1329 * 38: VCC_3.3 1330 * 39: ADCIN5 (TWL6030) 1331 * 40: V_BATT_5 1332 */ 1333 { -1 } 1334 }; 1335 #endif 1336 static const struct omap_mux_conf parlor_mux_mcspi1_conf[] = { 1337 #if 0 1338 { 0x132, /* 3: MCSPI1_CLK */ 1339 MUXMODE(0) | ??? }, 1340 { 0x138, /* 4: MCSPI1_CS0 */ 1341 MUXMODE(0) | ??? }, 1342 { 0x136, /* 5: MCSPI1_SIMO */ 1343 MUXMODE(0) | ??? }, 1344 { 0x13a, /* 6: MCSPI1_CS1 */ 1345 MUXMODE(0) | ??? }, 1346 { 0x134, /* 7: MCSPI1_SOMI */ 1347 MUXMODE(0) | ??? | INPUTENABLE }, 1348 { 0x13c, /* 8: MCSPI1_CS2 */ 1349 MUXMODE(0) | ??? }, 1350 { 0x13e, /* 10: MCSPI1_CS3 */ 1351 MUXMODE(0) | ??? }, 1352 #endif 1353 { -1 } 1354 }; 1355 static const struct omap_mux_conf parlor_mux_no_mcspi1_conf[] = { 1356 { 0x132, /* 3: GPIO 134 */ 1357 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1358 { 0x138, /* 4: GPIO 137 */ 1359 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1360 { 0x136, /* 5: GPIO 136 */ 1361 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1362 { 0x13a, /* 6: GPIO 138 */ 1363 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1364 { 0x134, /* 7: GPIO 135 */ 1365 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1366 { 0x13c, /* 8: GPIO 139 */ 1367 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1368 { 0x13e, /* 10: GPIO 140 */ 1369 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1370 { -1 } 1371 }; 1372 static const struct omap_mux_conf parlor_mux_hdq_conf[] = { 1373 #if 0 1374 { 0x120, /* 9: HDQ_SIO */ 1375 MUXMODE(0) | ??? | INPUTENABLE }, 1376 #endif 1377 { -1 } 1378 }; 1379 static const struct omap_mux_conf parlor_mux_no_hdq_conf[] = { 1380 { 0x120, /* 9: GPIO_127 */ 1381 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1382 { -1 } 1383 }; 1384 static const struct omap_mux_conf parlor_mux_i2c2_conf[] = { 1385 { 0x126, /* 12: I2C2_SCL */ 1386 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1387 { 0x128, /* 14: I2C2_SDA */ 1388 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1389 { -1 } 1390 }; 1391 static const struct omap_mux_conf parlor_mux_no_i2c2_conf[] = { 1392 { 0x126, /* 12: GPIO 128 */ 1393 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1394 { 0x128, /* 14: GPIO 129 */ 1395 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1396 { -1 } 1397 }; 1398 static const struct omap_mux_conf parlor_mux_sdmmc3_conf[] = { 1399 #if 0 1400 11 SDMMC3_CMD DuoVero J2 A15 <- omap pin AG10 1401 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1402 13 SDMMC3_CLK DuoVero J2 A16 <- omap pin AE9 1403 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1404 #endif 1405 { 0x11c, /* 17: SDMMC3_DAT0 */ 1406 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1407 { 0x11e, /* 15: SDMMC3_DAT1 */ 1408 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1409 { -1 } 1410 }; 1411 static const struct omap_mux_conf parlor_mux_uart2_conf[] = { 1412 { 0x11c, /* 17: UART2_RX */ 1413 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1414 { 0x11e, 1415 MUXMODE(0) | PULLUDENABLE }, /* 15: UART2_TX */ 1416 { -1 } 1417 }; 1418 static const struct omap_mux_conf parlor_mux_no_uart2_conf[] = { 1419 { 0x11c, /* 17: GPIO 125 */ 1420 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1421 { 0x11e, /* 15: GPIO 126 */ 1422 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1423 { -1 } 1424 }; 1425 static const struct omap_mux_conf parlor_mux_bsp2_conf[] = { 1426 { 0x0f6, /* 19: BSP2_CLKX */ 1427 MUXMODE(0) | INPUTENABLE }, 1428 { 0x0fc, /* 20: BSP2_FSX */ 1429 MUXMODE(0) | INPUTENABLE }, 1430 { 0x0fa, /* 21: BSP2_DX */ 1431 MUXMODE(0) | PULLUDENABLE }, 1432 { 0x0f8, /* 22: BSP2_DR */ 1433 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1434 { 0x10e, /* 23: BSP2_CLKS */ 1435 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1436 { -1 } 1437 }; 1438 static const struct omap_mux_conf parlor_mux_no_bsp2_conf[] = { 1439 { 0x0f6, /* 19: GPIO 110 */ 1440 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1441 { 0x0fc, /* 20: GPIO 113 */ 1442 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1443 { 0x0fa, /* 21: GPIO 112 */ 1444 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1445 { 0x0f8, /* 22: GPIO 111 */ 1446 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1447 { 0x10e, /* 23: GPIO 118 */ 1448 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1449 { -1 } 1450 }; 1451 static const struct omap_mux_conf parlor_mux_mcspi4_conf[] = { 1452 #if 0 1453 { 0x158, /* 25: MCSPI4_SOMI */ 1454 MUXMODE(0) | ??? | INPUTENABLE }, 1455 { 0x156, /* 27: MCSPI4_SIMO */ 1456 MUXMODE(0) | ??? }, 1457 { 0x154, /* 29: MCSPI4_CLK */ 1458 MUXMODE(0) | ??? }, 1459 { 0x15a, /* 31: MCSPI4_CS0 */ 1460 MUXMODE(0) | ??? }, 1461 #endif 1462 { -1 } 1463 }; 1464 static const struct omap_mux_conf parlor_mux_no_mcspi4_conf[] = { 1465 { 0x158, /* 25: GPIO 153 */ 1466 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1467 { 0x156, /* 27: GPIO 152 */ 1468 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1469 { 0x154, /* 29: GPIO 151 */ 1470 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1471 { 0x15a, /* 31: GPIO 154 */ 1472 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1473 { -1 } 1474 }; 1475 1476 /* 1477 * ETH0 connects via CS5. It use GPIO 44 for IRQ. 1478 * Also GPIO 45 is NRESET. 1479 */ 1480 smsh_config(NULL, 44, 45); 1481 1482 ehci_config(); 1483 1484 gxio_omap_mux_config_address("mcspi", 0x48098000, 1485 parlor_mux_mcspi1_conf, parlor_mux_no_mcspi1_conf); 1486 gxio_omap_mux_config_address("hdq", 0x480b2000, 1487 parlor_mux_hdq_conf, parlor_mux_no_hdq_conf); 1488 gxio_omap_mux_config_address("tiiic", 0x48072000, 1489 parlor_mux_i2c2_conf, parlor_mux_no_i2c2_conf); 1490 if (gxio_omap_mux_config_address("sdhc", 0x480ad000, 1491 parlor_mux_sdmmc3_conf, NULL) != 0) 1492 gxio_omap_mux_config_address("com", 0x4806c000, 1493 parlor_mux_uart2_conf, parlor_mux_no_uart2_conf); 1494 gxio_omap_mux_config_address("mcbsp", 0x49024000, 1495 parlor_mux_bsp2_conf, parlor_mux_no_bsp2_conf); 1496 gxio_omap_mux_config_address("mcspi", 0x480ba000, 1497 parlor_mux_mcspi4_conf, parlor_mux_no_mcspi4_conf); 1498 } 1499 1500 #elif defined(PEPPER) 1501 1502 static void 1503 lcd_config(void) 1504 { 1505 static const struct tifb_panel_info panel_lcd = { 1506 .panel_tft = 1, 1507 .panel_mono = false, 1508 .panel_bpp = 24, 1509 1510 .panel_pxl_clk = 18400000, 1511 .panel_width = 480, 1512 .panel_height = 272, 1513 .panel_hfp = 8, 1514 .panel_hbp = 4, 1515 .panel_hsw = 41, 1516 .panel_vfp = 4, 1517 .panel_vbp = 2, 1518 .panel_vsw = 10, 1519 .panel_invert_hsync = 0, 1520 .panel_invert_vsync = 0, 1521 1522 .panel_ac_bias = 255, 1523 .panel_ac_bias_intrpt = 0, 1524 .panel_dma_burst_sz = 16, 1525 .panel_fdd = 0x80, 1526 .panel_sync_edge = 0, 1527 .panel_sync_ctrl = 1, 1528 .panel_tft_alt_mode = 0, 1529 .panel_invert_pxl_clk = 0, 1530 }; 1531 static const struct omap_mux_conf pepper_mux_lcd_conf[] = { 1532 /* 1533 * LCD_DATA[0-23] configures in tifb.c 1534 */ 1535 1536 { 0x8e0, MMODE(0) | PUDEN }, /* LCD_VSYNC */ 1537 { 0x8e4, MMODE(0) | PUDEN }, /* LCD_HSYNC */ 1538 { 0x8e8, MMODE(0) | PUDEN }, /* LCD_PCLK */ 1539 { 0x8ec, MMODE(0) | PUDEN }, /* LCD_AC_BIAS_EN */ 1540 1541 { 0x86c, MMODE(7) | PUTYPESEL }, /* GPIO 59: Enable */ 1542 { -1 } 1543 }; 1544 1545 if (gxio_omap_mux_config_address("tifb", 0x4830e000, 1546 pepper_mux_lcd_conf, NULL) == 0) { 1547 extern const struct tifb_panel_info *tifb_panel_info; 1548 extern bool use_tps65217_wled; 1549 1550 tifb_panel_info = &panel_lcd; 1551 use_tps65217_wled = true; 1552 } 1553 } 1554 1555 static void 1556 pepper43_config(void) 1557 { 1558 static const struct omap_mux_conf pepper43_mux_wilink8_conf[] = { 1559 /* TI WiLink 8 */ 1560 { 0x800, MMODE(7) | PUTYPESEL }, /* GPIO 32: Bluetooth */ 1561 { 0x804, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 33: irq */ 1562 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: WiFi */ 1563 { -1 } 1564 }; 1565 static const struct omap_mux_conf pepper43_mux_i2c1_conf[] = { 1566 { 0x968, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1567 { 0x96c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1568 { -1 } 1569 }; 1570 static const struct omap_mux_conf pepper43_mpu9150_conf[] = { 1571 /* MPU9150 at I2C1 */ 1572 { 0x808, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 34: IRQ */ 1573 { 0x898, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 68 */ 1574 { 0x870, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 30 */ 1575 { -1 } 1576 }; 1577 static const struct omap_mux_conf pepper43_mux_20pin_header_conf[] = { 1578 { 0x85c, MMODE(7) | PUDEN | RXACTIVE }, /* 1: GPIO 55 */ 1579 { 0x80c, MMODE(7) | PUDEN | RXACTIVE }, /* 2: GPIO 35 */ 1580 { 0x810, MMODE(7) | PUDEN | RXACTIVE }, /* 3: GPIO 36 */ 1581 { 0x814, MMODE(7) | PUDEN | RXACTIVE }, /* 4: GPIO 37 */ 1582 { 0x818, MMODE(7) | PUDEN | RXACTIVE }, /* 5: GPIO 38 */ 1583 { 0x81c, MMODE(7) | PUDEN | RXACTIVE }, /* 6: GPIO 39 */ 1584 { 0x87c, MMODE(7) | PUDEN | RXACTIVE }, /* 7: GPIO 61 */ 1585 { 0x880, MMODE(7) | PUDEN | RXACTIVE }, /* 8: GPIO 62 */ 1586 { 0x884, MMODE(7) | PUDEN | RXACTIVE }, /* 9: GPIO 63 */ 1587 { 0x9e4, MMODE(7) | PUDEN | RXACTIVE }, /* 10: GPIO 103 */ 1588 { 0x9e8, MMODE(7) | PUDEN | RXACTIVE }, /* 11: GPIO 104 */ 1589 { 0x9b0, MMODE(7) | PUDEN | RXACTIVE }, /* 12: GPIO 19 */ 1590 #if 0 /* UART3 or GPIO */ 1591 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* 13: GPIO 7 */ 1592 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* 14: GPIO 6 */ 1593 #endif 1594 #if 0 /* UART2 or GPIO */ 1595 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* 15: GPIO 98 */ 1596 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* 16: GPIO 97 */ 1597 #endif 1598 /* 17: VCC 5v */ 1599 /* 18: VCC 3.3v */ 1600 /* 19: GND */ 1601 /* 20: GND */ 1602 { -1 } 1603 }; 1604 static const struct omap_mux_conf pepper43_mux_uart2_conf[] = { 1605 { 0x90c, MMODE(6) | PUTYPESEL | RXACTIVE }, /* UART2_RXD */ 1606 { 0x910, MMODE(6) | PUDEN }, /* UART2_TXD */ 1607 { -1 } 1608 }; 1609 static const struct omap_mux_conf pepper43_mux_no_uart2_conf[] = { 1610 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 97 */ 1611 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 98 */ 1612 { -1 } 1613 }; 1614 static const struct omap_mux_conf pepper43_mux_uart3_conf[] = { 1615 { 0x960, MMODE(1) | PUTYPESEL | RXACTIVE }, /* UART3_RXD */ 1616 { 0x964, MMODE(1) | PUDEN }, /* UART3_TXD */ 1617 { -1 } 1618 }; 1619 static const struct omap_mux_conf pepper43_mux_no_uart3_conf[] = { 1620 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 6 */ 1621 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 7 */ 1622 { -1 } 1623 }; 1624 1625 static const struct omap_mux_conf *pepper43_mux_conf[] = { 1626 pepper43_mux_wilink8_conf, 1627 pepper43_mux_i2c1_conf, 1628 pepper43_mpu9150_conf, 1629 pepper43_mux_20pin_header_conf, 1630 }; 1631 1632 static const struct omap_gpio_conf pepper43_gpio_wl18xx_conf[] = { 1633 { 32, conf_output_0 }, /* #Reset: Bluetooth */ 1634 { 56, conf_output_0 }, /* #Reset: WiFi */ 1635 { -1 } 1636 }; 1637 int i; 1638 1639 lcd_config(); 1640 1641 for (i = 0; i < __arraycount(pepper43_mux_conf); i++) 1642 gxio_omap_mux_config(pepper43_mux_conf[i]); 1643 gxio_omap_gpio_config(pepper43_gpio_wl18xx_conf); 1644 1645 #if 0 1646 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 52 (Blue) */ 1647 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 20)); 1648 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1649 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 20)); 1650 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 53 (Red) */ 1651 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 21)); 1652 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1653 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 21)); 1654 #endif 1655 1656 gxio_omap_mux_config_address("com", 0x48024000, 1657 pepper43_mux_uart2_conf, pepper43_mux_no_uart2_conf); 1658 gxio_omap_mux_config_address("com", 0x481a6000, 1659 pepper43_mux_uart3_conf, pepper43_mux_no_uart3_conf); 1660 } 1661 1662 static void 1663 pepper_config(void) 1664 { 1665 static const struct omap_mux_conf pepper_mux_button2_conf[] = { 1666 { 0x85c, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 55 */ 1667 { -1 } 1668 }; 1669 static const struct omap_mux_conf pepper_mux_i2c1_conf[] = { 1670 { 0x90c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1671 { 0x910, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1672 { -1 } 1673 }; 1674 static const struct omap_mux_conf pepper_mux_wi2wi_conf[] = { 1675 { 0x9b4, MMODE(3) | PUDEN }, /* CLKOUT2 */ 1676 /* Wi2Wi */ 1677 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: nReset */ 1678 { 0x870, MMODE(7) | PUTYPESEL }, /* GPIO 30: nPower */ 1679 { -1 } 1680 }; 1681 static const struct omap_mux_conf pepper_mux_uart1_conf[] = { 1682 { 0x978, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_CTSn */ 1683 { 0x97c, MMODE(0) }, /* UART1_RTSn */ 1684 { 0x980, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_RXD */ 1685 { 0x984, MMODE(0) }, /* UART1_TXD */ 1686 { -1 } 1687 }; 1688 static const struct omap_mux_conf pepper_mux_no_uart1_conf[] = { 1689 { 0x978, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 12 */ 1690 { 0x97c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 13 */ 1691 { 0x980, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 14 */ 1692 { 0x984, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 15 */ 1693 { -1 } 1694 }; 1695 static const struct omap_mux_conf *pepper_mux_conf[] = { 1696 pepper_mux_button2_conf, 1697 pepper_mux_i2c1_conf, 1698 pepper_mux_wi2wi_conf, 1699 }; 1700 1701 int i; 1702 1703 lcd_config(); 1704 1705 for (i = 0; i < __arraycount(pepper_mux_conf); i++) 1706 gxio_omap_mux_config(pepper_mux_conf[i]); 1707 gxio_omap_mux_config_address("com", 0x48022000, 1708 pepper_mux_uart1_conf, pepper_mux_no_uart1_conf); 1709 } 1710 1711 static void 1712 c_config(void) 1713 { 1714 static const struct omap_mux_conf pepper43c_mux_ft5306_conf[] = { 1715 /* FT5306 at I2C2 */ 1716 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20 */ 1717 { 0x95c, MMODE(7) | PUDEN }, /* GPIO 5 */ 1718 { -1 } 1719 }; 1720 static const struct omap_mux_conf pepper43c_mux_i2c2_conf[] = { 1721 { 0x950, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SDA */ 1722 { 0x954, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SCL */ 1723 { -1 } 1724 }; 1725 static const struct omap_mux_conf *pepper43c_mux_conf[] = { 1726 pepper43c_mux_ft5306_conf, 1727 pepper43c_mux_i2c2_conf, 1728 }; 1729 1730 static const struct omap_gpio_conf pepper43c_gpio_ft5306_conf[] = { 1731 { 5, conf_output_0 }, /* #Reset */ 1732 { -1 } 1733 }; 1734 int i; 1735 1736 pepper43_config(); 1737 1738 for (i = 0; i < __arraycount(pepper43c_mux_conf); i++) 1739 gxio_omap_mux_config(pepper43c_mux_conf[i]); 1740 gxio_omap_gpio_config(pepper43c_gpio_ft5306_conf); 1741 } 1742 1743 static void 1744 dvi_config(void) 1745 { 1746 /* XXXX: hmm... mismatch found in Linux's dts and pubs.gumstix.org... */ 1747 1748 extern struct cfdata cfdata[]; 1749 extern const struct tifb_panel_info *tifb_panel_info; 1750 1751 static const struct tifb_panel_info panel_dvi = { 1752 .panel_tft = 1, 1753 .panel_mono = false, 1754 .panel_bpp = 16, 1755 1756 .panel_pxl_clk = 63500000, 1757 .panel_width = 1024, 1758 .panel_height = 768, 1759 .panel_hfp = 8, 1760 .panel_hbp = 4, 1761 .panel_hsw = 41, 1762 .panel_vfp = 4, 1763 .panel_vbp = 2, 1764 .panel_vsw = 10, 1765 .panel_invert_hsync = 0, 1766 .panel_invert_vsync = 0, 1767 1768 .panel_ac_bias = 255, 1769 .panel_ac_bias_intrpt = 0, 1770 .panel_dma_burst_sz = 16, 1771 .panel_fdd = 0x80, 1772 .panel_sync_edge = 0, 1773 .panel_sync_ctrl = 1, 1774 .panel_invert_pxl_clk = 0, 1775 }; 1776 cfdata_t cf = &cfdata[0]; 1777 1778 /* Disable wireless module. */ 1779 while (cf->cf_name != NULL) { 1780 if (strcmp(cf->cf_name, "sdhc") == 0 && 1781 strcmp(cf->cf_atname, "mainbus") == 0 && 1782 cf->cf_loc[MAINBUSCF_BASE] == 0x47810000) { 1783 if (cf->cf_fstate == FSTATE_NOTFOUND) 1784 cf->cf_fstate = FSTATE_DNOTFOUND; 1785 else if (cf->cf_fstate == FSTATE_STAR) 1786 cf->cf_fstate = FSTATE_DSTAR; 1787 } 1788 cf++; 1789 } 1790 1791 tifb_panel_info = &panel_dvi; 1792 } 1793 1794 static void 1795 r_config(void) 1796 { 1797 static const struct omap_mux_conf pepper43r_mux_ads7846_conf[] = { 1798 /* ADS7846 at McSPI0 */ 1799 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20: IRQ */ 1800 { -1 } 1801 }; 1802 static const struct omap_mux_conf pepper43r_mux_spi0_conf[] = { 1803 { 0x950, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_SCLK */ 1804 { 0x954, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D0 */ 1805 { 0x958, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D1 */ 1806 { 0x95c, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_CS0 */ 1807 { -1 } 1808 }; 1809 static const struct omap_mux_conf *pepper43r_mux_conf[] = { 1810 pepper43r_mux_ads7846_conf, 1811 pepper43r_mux_spi0_conf, 1812 }; 1813 int i; 1814 1815 pepper43_config(); 1816 1817 for (i = 0; i < __arraycount(pepper43r_mux_conf); i++) 1818 gxio_omap_mux_config(pepper43r_mux_conf[i]); 1819 } 1820 1821 #endif 1822 1823 #if defined(OVERO) || defined(DUOVERO) 1824 static void 1825 smsh_config(struct omap_mux_conf *smsh_mux_conf, int intr, int nreset) 1826 { 1827 struct omap_gpio_conf smsh_gpio_conf[] = { 1828 { intr, conf_input }, 1829 { nreset, conf_output_0 }, 1830 { -1 } 1831 }; 1832 1833 /* 1834 * Basically use current settings by U-Boot. 1835 * However remap physical address to configured address. 1836 */ 1837 1838 if (smsh_mux_conf != NULL) 1839 gxio_omap_mux_config(smsh_mux_conf); 1840 gxio_omap_gpio_config(smsh_gpio_conf); 1841 __udelay(100000); 1842 gxio_omap_gpio_write(nreset, 1); 1843 } 1844 #endif 1845 1846 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1847 /* 1848 * The delay for configuration time. 1849 * This function use initialized timer by U-Boot. 1850 */ 1851 static void 1852 __udelay(unsigned int usec) 1853 { 1854 #if defined(OVERO) || defined(DUOVERO) 1855 #define V_SCLK (26000000 >> 1) 1856 #define TCRR 0x28 1857 #elif defined(PEPPER) 1858 #define V_SCLK 24000000 1859 #define TCRR 0x3c 1860 #endif 1861 #define SYS_PTV 2 1862 #define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV)) 1863 1864 const vaddr_t timer_base = 1865 #if defined(OVERO) 1866 OVERO_L4_PERIPHERAL_VBASE + 0x32000; 1867 #elif defined(DUOVERO) 1868 DUOVERO_L4_PERIPHERAL_VBASE + 0x32000; 1869 #elif defined(PEPPER) 1870 PEPPER_L4_PERIPHERAL_VBASE + 0x40000; 1871 #endif 1872 long timo = usec * (TIMER_CLOCK / 1000) / 1000; 1873 uint32_t now, last; 1874 1875 last = ioreg_read(timer_base + TCRR); 1876 while (timo > 0) { 1877 now = ioreg_read(timer_base + TCRR); 1878 if (last > now) 1879 timo -= __BITS(0, 31) - last + now + 1; 1880 else 1881 timo -= now - last; 1882 last = now; 1883 } 1884 } 1885 #endif 1886 1887 #if defined(PEPPER) 1888 static int 1889 read_i2c_device(const vaddr_t i2c_base, uint16_t sa, uint8_t addr, int len, 1890 uint8_t *buf) 1891 { 1892 uint16_t v; 1893 int aok = 0, cnt = 0; 1894 1895 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1896 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1897 while (v & I2C_IRQSTATUS_BB) { 1898 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, v); 1899 __udelay(20); 1900 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1901 } 1902 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1903 1904 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1905 ioreg16_write(i2c_base + OMAP2_I2C_CNT, sizeof(addr)); 1906 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1907 I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STP | I2C_CON_STT); 1908 while (1 /*CONSTCOND*/) { 1909 __udelay(20); 1910 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1911 if ((v & I2C_IRQSTATUS_XRDY) && aok == 0) { 1912 aok = 1; 1913 ioreg16_write(i2c_base + OMAP2_I2C_DATA, addr); 1914 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1915 I2C_IRQSTATUS_XRDY); 1916 } 1917 if (v & I2C_IRQSTATUS_ARDY) { 1918 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1919 I2C_IRQSTATUS_ARDY); 1920 break; 1921 } 1922 } 1923 1924 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1925 ioreg16_write(i2c_base + OMAP2_I2C_CNT, len); 1926 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1927 I2C_CON_EN | I2C_CON_MST | I2C_CON_STP | I2C_CON_STT); 1928 while (1 /*CONSTCOND*/) { 1929 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1930 if (v & I2C_IRQSTATUS_RRDY && 1931 cnt < len) { 1932 buf[cnt++] = ioreg16_read(i2c_base + OMAP2_I2C_DATA); 1933 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1934 I2C_IRQSTATUS_RRDY); 1935 } 1936 if (v & I2C_IRQSTATUS_ARDY) { 1937 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1938 I2C_IRQSTATUS_ARDY); 1939 break; 1940 } 1941 } 1942 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1943 return 0; 1944 } 1945 #endif 1946
Indexes created Tue Sep 30 11:09:46 GMT 2025