gxio.c revision 1.28
1 /* $NetBSD: gxio.c,v 1.28 2021/08/07 16:18:49 thorpej Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: gxio.c,v 1.28 2021/08/07 16:18:49 thorpej Exp $"); 35 36 #include "opt_cputypes.h" 37 #include "opt_gumstix.h" 38 #include "opt_gxio.h" 39 #if defined(OVERO) 40 #include "opt_omap.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/device.h> 45 #include <sys/errno.h> 46 #include <sys/kernel.h> 47 48 #include <sys/systm.h> 49 50 #include <machine/bootconfig.h> 51 52 #include <arm/omap/omap2_gpmcreg.h> 53 #if defined(OMAP2) 54 #include <arm/omap/omap2_reg.h> 55 #if defined(OMAP3530) 56 #include <arm/omap/omap2_intr.h> 57 #endif 58 #endif 59 #include <arm/omap/omap_var.h> 60 #include <arm/omap/ti_iicreg.h> 61 #include <arm/omap/tifbvar.h> 62 #if defined(CPU_XSCALE) 63 #include <arm/xscale/pxa2x0cpu.h> 64 #endif 65 #include <arm/xscale/pxa2x0reg.h> 66 #include <arm/xscale/pxa2x0var.h> 67 #include <arm/xscale/pxa2x0_gpio.h> 68 #include <evbarm/gumstix/gumstixreg.h> 69 #include <evbarm/gumstix/gumstixvar.h> 70 71 #include "ioconf.h" 72 #include "locators.h" 73 74 75 struct gxioconf { 76 const char *name; 77 void (*config)(void); 78 }; 79 80 #if defined(GUMSTIX) 81 static int gxiomatch(device_t, cfdata_t, void *); 82 static void gxioattach(device_t, device_t, void *); 83 static int gxiosearch(device_t, cfdata_t, const int *, void *); 84 static int gxioprint(void *, const char *); 85 86 CFATTACH_DECL_NEW(gxio, sizeof(struct gxio_softc), 87 gxiomatch, gxioattach, NULL, NULL); 88 #endif 89 90 void gxio_config(void); 91 void gxio_config_expansion(const char *); 92 #if defined(GUMSTIX) 93 static void basix_config(void); 94 static void cfstix_config(void); 95 static void etherstix_config(void); 96 static void netcf_config(void); 97 static void netcf_vx_config(void); 98 static void netduommc_config(void); 99 static void netduo_config(void); 100 static void netmicrosd_config(void); 101 static void netwifimicrosd_config(void); 102 static void netmmc_config(void); 103 static void wifistix_config(void); 104 static void wifistix_cf_config(void); 105 #elif defined(OVERO) 106 static void eth0_config(void); 107 static void eth1_config(void); 108 static void dvi_config(void); 109 static void lcd_config(char); 110 static void header_40pin_config(int); 111 112 static void chestnut_config(void); 113 static void gallop_config(void); 114 static void summit_config(void); 115 static void tobi_config(void); 116 static void tobiduo_config(void); 117 #elif defined(DUOVERO) 118 static void ehci_config(void); 119 120 static void parlor_config(void); 121 #elif defined(PEPPER) 122 static void lcd_config(void); 123 static void pepper43_config(void); 124 125 static void pepper_config(void); 126 static void c_config(void); 127 static void dvi_config(void); 128 static void r_config(void); 129 #endif 130 #if defined(OVERO) || defined(DUOVERO) 131 struct omap_mux_conf; 132 static void smsh_config(struct omap_mux_conf *, int, int); 133 #endif 134 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 135 static void __udelay(unsigned int); 136 #endif 137 #if defined(PEPPER) 138 static int read_i2c_device(const vaddr_t, uint16_t, uint8_t, int, uint8_t *); 139 #endif 140 141 #if defined(CPU_XSCALE_PXA250) 142 143 static struct pxa2x0_gpioconf pxa255dep_gpioconf[] = { 144 /* Bluetooth module configuration */ 145 { 7, GPIO_OUT | GPIO_SET }, /* power on */ 146 { 12, GPIO_ALT_FN_1_OUT }, /* 32kHz out. required by SingleStone */ 147 148 /* AC97 configuration */ 149 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 150 151 /* FFUART configuration */ 152 { 35, GPIO_ALT_FN_1_IN }, /* CTS */ 153 { 41, GPIO_ALT_FN_2_OUT }, /* RTS */ 154 155 #ifndef GXIO_BLUETOOTH_ON_HWUART 156 /* BTUART configuration */ 157 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 158 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 159 #else 160 /* HWUART configuration */ 161 { 42, GPIO_ALT_FN_3_IN }, /* HWRXD */ 162 { 43, GPIO_ALT_FN_3_OUT }, /* HWTXD */ 163 { 44, GPIO_ALT_FN_3_IN }, /* HWCTS */ 164 { 45, GPIO_ALT_FN_3_OUT }, /* HWRTS */ 165 #endif 166 167 #ifndef GXIO_BLUETOOTH_ON_HWUART 168 /* HWUART configuration */ 169 { 48, GPIO_ALT_FN_1_OUT }, /* HWTXD */ 170 { 49, GPIO_ALT_FN_1_IN }, /* HWRXD */ 171 { 50, GPIO_ALT_FN_1_IN }, /* HWCTS */ 172 { 51, GPIO_ALT_FN_1_OUT }, /* HWRTS */ 173 #endif 174 175 { -1 } 176 }; 177 #endif 178 #if defined(CPU_XSCALE_PXA270) 179 static struct pxa2x0_gpioconf verdexdep_gpioconf[] = { 180 /* Bluetooth module configuration */ 181 { 9, GPIO_ALT_FN_3_OUT }, /* CHOUT<0> */ 182 { 12, GPIO_OUT | GPIO_SET }, 183 184 /* LCD configuration */ 185 { 17, GPIO_IN }, /* backlight on */ 186 187 /* FFUART configuration */ 188 { 34, GPIO_ALT_FN_1_IN }, /* FFRXD */ 189 { 39, GPIO_ALT_FN_2_OUT }, /* FFTXD */ 190 191 /* BTUART configuration */ 192 { 42, GPIO_ALT_FN_1_IN }, /* BTRXD */ 193 { 43, GPIO_ALT_FN_2_OUT }, /* BTTXD */ 194 { 44, GPIO_ALT_FN_1_IN }, /* BTCTS */ 195 { 45, GPIO_ALT_FN_2_OUT }, /* BTRTS */ 196 197 /* AC97 configuration */ 198 { 29, GPIO_ALT_FN_1_IN }, /* SDATA_IN0 */ 199 200 { -1 } 201 }; 202 203 #elif defined(OMAP2) 204 205 struct omap_mux_conf { 206 int offset; 207 uint32_t value; 208 /* OMAP3/4 register values */ 209 #define WAKEUPEVENT (1 << 15) 210 #define WAKEUPENABLE (1 << 14) 211 #define OFFMODEPULLTYPESELECT (1 << 13) 212 #define OFFMODEPULLUDENABLE (1 << 12) 213 #define OFFMODEOUTVALUE (1 << 11) 214 #define OFFMODEOUTENABLE (1 << 10) 215 #define OFFMODEENABLE (1 << 9) 216 #define INPUTENABLE (1 << 8) 217 #define PULLTYPESELECT (1 << 4) 218 #define PULLUDENABLE (1 << 3) 219 #define MUXMODE(n) ((n) & 0x7) 220 221 /* Sitara AM3xxx register values */ 222 #define SLEWCTRL (1 << 6) 223 #define RXACTIVE (1 << 5) 224 #define PUTYPESEL (1 << 4) 225 #define PUDEN (1 << 3) 226 #define MMODE(n) ((n) & 0x7) 227 }; 228 struct omap_gpio_conf { 229 int pin; 230 enum { 231 conf_input = -1, 232 conf_output_0, 233 conf_output_1, 234 } conf; 235 }; 236 237 static void gxio_omap_mux_config(const struct omap_mux_conf []); 238 static int gxio_omap_mux_config_address(const char *, unsigned long, 239 const struct omap_mux_conf[], 240 const struct omap_mux_conf[]); 241 static void gxio_omap_gpio_config(const struct omap_gpio_conf[]); 242 void gxio_omap_gpio_write(int, int); 243 244 #if defined(OVERO) 245 static const struct omap_mux_conf overo_mux_i2c3_conf[] = { 246 { 0x1c2, MUXMODE(0) | INPUTENABLE }, /* i2c3_scl */ 247 { 0x1c4, MUXMODE(0) | INPUTENABLE }, /* i2c3_sda */ 248 { -1 } 249 }; 250 #endif 251 #if defined(OVERO) 252 static const struct omap_mux_conf overo_mux_mmchs2_conf[] = { 253 { 0x158, /* mmc2_clk */ 254 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 255 { 0x15a, /* mmc2_cmd */ 256 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 257 { 0x15c, /* mmc2_dat0 */ 258 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 259 { 0x15e, /* mmc2_dat1 */ 260 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 261 { 0x160, /* mmc2_dat2 */ 262 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 263 { 0x162, /* mmc2_dat3 */ 264 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 265 { -1 } 266 }; 267 #endif 268 #if defined(OVERO) 269 static const struct omap_mux_conf overo_mux_wireless_conf[] = { 270 { 0x0b4, MUXMODE(4) }, /* gpio_54:BT_nPOWERON*/ 271 { 0x0bc, MUXMODE(4) | INPUTENABLE }, /* gpio_58: WIFI_IRQ */ 272 { 0x19c, MUXMODE(4) }, /* gpio_164:BT_nRESET */ 273 { 0x5e0, MUXMODE(4) }, /* gpio_16: W2W_nRESET*/ 274 { -1 } 275 }; 276 277 #elif defined(DUOVERO) 278 static const struct omap_mux_conf duovero_mux_led_conf[] = { 279 { 0x116, MUXMODE(3) }, /* GPIO 122 */ 280 { -1 } 281 }; 282 static const struct omap_mux_conf duovero_mux_button_conf[] = { 283 { 0x114, /* GPIO 121 */ 284 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 285 { -1 } 286 }; 287 288 #elif defined(PEPPER) 289 static const struct omap_mux_conf pepper_mux_led_conf[] = { 290 { 0x850, MMODE(7) | PUDEN }, /* GPIO 52: Blue */ 291 { 0x854, MMODE(7) | PUDEN }, /* GPIO 53: Red */ 292 { -1 } 293 }; 294 static const struct omap_mux_conf pepper_mux_button_conf[] = { 295 { 0x858, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 54 */ 296 { -1 } 297 }; 298 static const struct omap_mux_conf pepper_mux_mmchs3_conf[] = { 299 { 0x844, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT0 */ 300 { 0x848, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT1 */ 301 { 0x84c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT2 */ 302 { 0x878, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_DAT3 */ 303 { 0x888, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CMD */ 304 { 0x88c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* MMC2_CLK */ 305 { -1 } 306 }; 307 static const struct omap_mux_conf pepper_mux_audio_codec_conf[] = { 308 { 0x840, MMODE(7) | PUDEN }, /* GPIO 48: #Reset */ 309 { -1 } 310 }; 311 #endif 312 313 #endif 314 315 static const struct gxioconf gxioconflist[] = { 316 #if defined(GUMSTIX) 317 { "basix", basix_config }, 318 { "cfstix", cfstix_config }, 319 { "etherstix", etherstix_config }, 320 { "netcf", netcf_config }, 321 { "netcf-vx", netcf_vx_config }, 322 { "netduo-mmc", netduommc_config }, 323 { "netduo", netduo_config }, 324 { "netmicrosd", netmicrosd_config }, 325 { "netmicrosd-vx", netmicrosd_config }, 326 { "netwifimicrosd", netwifimicrosd_config }, 327 { "netmmc", netmmc_config }, 328 { "netpro-vx", netwifimicrosd_config }, 329 { "wifistix-cf", wifistix_cf_config }, 330 { "wifistix", wifistix_config }, 331 #elif defined(OVERO) 332 { "chestnut43", chestnut_config }, 333 { "gallop43", gallop_config }, 334 { "summit", summit_config }, 335 { "tobi", tobi_config }, 336 { "tobi-duo", tobiduo_config }, 337 #elif defined(DUOVERO) 338 { "parlor", parlor_config }, 339 #elif defined(PEPPER) 340 { "43c", c_config }, 341 { "43r", r_config }, 342 { "dvi", dvi_config }, 343 #endif 344 { NULL } 345 }; 346 347 int gxpcic_gpio_reset; 348 struct gxpcic_slot_irqs gxpcic_slot_irqs[2] = { { 0, -1, -1 }, { 0, -1, -1 } }; 349 350 351 #if defined(GUMSTIX) 352 /* ARGSUSED */ 353 static int 354 gxiomatch(device_t parent, cfdata_t match, void *aux) 355 { 356 357 struct pxaip_attach_args *pxa = aux; 358 bus_space_tag_t iot = &pxa2x0_bs_tag; 359 bus_space_handle_t ioh; 360 361 if (strcmp(pxa->pxa_name, match->cf_name) != 0 || 362 pxa->pxa_addr != PXAIPCF_ADDR_DEFAULT) 363 return 0; 364 365 if (bus_space_map(iot, 366 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &ioh)) 367 return 0; 368 bus_space_unmap(iot, ioh, PXA2X0_MEMCTL_SIZE); 369 370 /* nothing */ 371 return 1; 372 } 373 374 /* ARGSUSED */ 375 static void 376 gxioattach(device_t parent, device_t self, void *aux) 377 { 378 struct gxio_softc *sc = device_private(self); 379 380 aprint_normal("\n"); 381 aprint_naive("\n"); 382 383 sc->sc_dev = self; 384 sc->sc_iot = &pxa2x0_bs_tag; 385 386 if (bus_space_map(sc->sc_iot, 387 PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, &sc->sc_ioh)) 388 return; 389 390 /* 391 * Attach each gumstix(busheader)/overo expansion board devices. 392 */ 393 config_search(self, NULL, 394 CFARGS(.search = gxiosearch)); 395 } 396 397 /* ARGSUSED */ 398 static int 399 gxiosearch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 400 { 401 struct gxio_softc *sc = device_private(parent); 402 struct gxio_attach_args gxa; 403 404 gxa.gxa_sc = sc; 405 gxa.gxa_iot = sc->sc_iot; 406 gxa.gxa_addr = cf->cf_loc[GXIOCF_ADDR]; 407 gxa.gxa_gpirq = cf->cf_loc[GXIOCF_GPIRQ]; 408 409 if (config_probe(parent, cf, &gxa)) 410 config_attach(parent, cf, &gxa, gxioprint, CFARGS_NONE); 411 412 return 0; 413 } 414 415 /* ARGSUSED */ 416 static int 417 gxioprint(void *aux, const char *name) 418 { 419 struct gxio_attach_args *gxa = (struct gxio_attach_args *)aux; 420 421 if (gxa->gxa_addr != GXIOCF_ADDR_DEFAULT) 422 printf(" addr 0x%lx", gxa->gxa_addr); 423 if (gxa->gxa_gpirq > 0) 424 printf(" gpirq %d", gxa->gxa_gpirq); 425 return UNCONF; 426 } 427 #endif 428 429 430 #if defined(GUMSTIX) 431 /* 432 * configure for GPIO pin and expansion boards. 433 */ 434 void 435 gxio_config(void) 436 { 437 #if defined(CPU_XSCALE_PXA250) 438 struct pxa2x0_gpioconf *gumstix_gpioconf[] = { 439 pxa25x_com_ffuart_gpioconf, 440 pxa25x_com_stuart_gpioconf, 441 #ifndef GXIO_BLUETOOTH_ON_HWUART 442 pxa25x_com_btuart_gpioconf, 443 #endif 444 pxa25x_com_hwuart_gpioconf, 445 pxa25x_i2c_gpioconf, 446 pxa25x_pxaacu_gpioconf, 447 pxa255dep_gpioconf, 448 NULL 449 }; 450 #endif 451 #if defined(CPU_XSCALE_PXA270) 452 struct pxa2x0_gpioconf *verdex_gpioconf[] = { 453 pxa27x_com_ffuart_gpioconf, 454 pxa27x_com_stuart_gpioconf, 455 pxa27x_com_btuart_gpioconf, 456 pxa27x_i2c_gpioconf, 457 pxa27x_pxaacu_gpioconf, 458 pxa27x_pxamci_gpioconf, 459 pxa27x_ohci_gpioconf, 460 verdexdep_gpioconf, 461 NULL 462 }; 463 #endif 464 465 /* XXX: turn off for power of bluetooth module */ 466 #if defined(CPU_XSCALE_PXA250) 467 pxa2x0_gpio_set_function(7, GPIO_OUT | GPIO_CLR); 468 #elif defined(CPU_XSCALE_PXA270) 469 pxa2x0_gpio_set_function(12, GPIO_OUT | GPIO_CLR); 470 #endif 471 delay(100); 472 473 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 474 pxa2x0_gpio_config( 475 (CPU_IS_PXA250) ? gumstix_gpioconf : verdex_gpioconf); 476 #elif defined(CPU_XSCALE_PXA270) || defined(CPU_XSCALE_PXA250) 477 #if defined(CPU_XSCALE_PXA270) 478 pxa2x0_gpio_config(verdex_gpioconf); 479 #else 480 pxa2x0_gpio_config(gumstix_gpioconf); 481 #endif 482 #endif 483 } 484 #elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 485 static void 486 gxio_omap_mux_config(const struct omap_mux_conf mux_conf[]) 487 { 488 #if defined(OVERO) 489 const vaddr_t ctrlmod_base = OVERO_L4_CORE_VBASE + 0x2000; 490 #elif defined(DUOVERO) 491 const vaddr_t ctrlmod_base = DUOVERO_L4_CM_VBASE; 492 #elif defined(PEPPER) 493 const vaddr_t ctrlmod_base = PEPPER_PRCM_VBASE + 0x10000; 494 #endif 495 int i; 496 497 for (i = 0; mux_conf[i].offset != -1; i++) 498 #if !defined(TI_AM335X) 499 ioreg16_write(ctrlmod_base + mux_conf[i].offset, 500 mux_conf[i].value); 501 #else 502 ioreg_write(ctrlmod_base + mux_conf[i].offset, 503 mux_conf[i].value); 504 #endif 505 } 506 507 static int 508 gxio_omap_mux_config_address(const char *name, unsigned long address, 509 const struct omap_mux_conf mux_conf[], 510 const struct omap_mux_conf not_mux_conf[]) 511 { 512 extern struct cfdata cfdata[]; 513 cfdata_t cf = &cfdata[0]; 514 515 while (cf->cf_name != NULL) { 516 if (strcmp(name, cf->cf_name) == 0 && 517 address == cf->cf_loc[OBIOCF_ADDR]) { 518 gxio_omap_mux_config(mux_conf); 519 return 0; 520 } 521 cf++; 522 } 523 524 if (not_mux_conf == NULL) 525 return -1; 526 527 gxio_omap_mux_config(not_mux_conf); 528 return 0; 529 } 530 531 #if defined(OVERO) 532 #define gpio_reg_read ioreg_read 533 #define gpio_reg_write ioreg_write 534 #elif defined(DUOVERO) || defined(PEPPER) 535 #define gpio_reg_read(a) ioreg_read((a) + GPIO_SIZE2) 536 #define gpio_reg_write(a, v) ioreg_write((a) + GPIO_SIZE2, (v)) 537 #endif 538 539 static const vaddr_t gpio_bases[] = { 540 #if defined(OVERO) 541 #define OVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 542 #define GPIO(n) GPIO ## n ## _BASE_3530 543 #define BASE(a, n) \ 544 (OVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP3530_L4_ ## a ## _BASE)) 545 546 GPIO1_BASE_3530, 547 GPIO2_BASE_3530, 548 GPIO3_BASE_3530, 549 GPIO4_BASE_3530, 550 GPIO5_BASE_3530, 551 GPIO6_BASE_3530, 552 553 #elif defined(DUOVERO) 554 #define DUOVERO_GPIO_VBASE(n) ((n) == 1 ? BASE(WAKEUP, n) : BASE(PERIPHERAL, n)) 555 #define GPIO(n) GPIO ## n ## _BASE_4430 556 #define BASE(a, n) \ 557 (DUOVERO_L4_ ## a ## _VBASE + (GPIO(n) - OMAP4430_L4_ ## a ## _BASE)) 558 559 DUOVERO_GPIO_VBASE(1), 560 DUOVERO_GPIO_VBASE(2), 561 DUOVERO_GPIO_VBASE(3), 562 DUOVERO_GPIO_VBASE(4), 563 DUOVERO_GPIO_VBASE(5), 564 565 #elif defined(PEPPER) 566 #define PEPPER_GPIO_VBASE(n) ((n) == 0 ? WAKEUP(n) : PERIPHERAL(n)) 567 #define GPIO(n) GPIO ## n ## _BASE_TI_AM335X 568 #define WAKEUP(n) (PEPPER_PRCM_VBASE + (GPIO(n) - OMAP2_CM_BASE)) 569 #define PERIPHERAL(n) \ 570 (PEPPER_L4_PERIPHERAL_VBASE + (GPIO(n) - TI_AM335X_L4_PERIPHERAL_BASE)) 571 572 PEPPER_GPIO_VBASE(0), 573 PEPPER_GPIO_VBASE(1), 574 PEPPER_GPIO_VBASE(2), 575 PEPPER_GPIO_VBASE(3), 576 #endif 577 }; 578 579 static void 580 gxio_omap_gpio_config(const struct omap_gpio_conf gpio_conf[]) 581 { 582 vaddr_t gpio_base; 583 int mask, i; 584 585 for (i = 0; gpio_conf[i].pin != -1; i++) { 586 gpio_base = gpio_bases[gpio_conf[i].pin / 32]; 587 mask = 1 << (gpio_conf[i].pin % 32); 588 switch (gpio_conf[i].conf) { 589 case conf_input: 590 ioreg_write(gpio_base + GPIO_OE, 591 ioreg_read(gpio_base + GPIO_OE) | mask); 592 break; 593 case conf_output_0: 594 ioreg_write(gpio_base + GPIO_OE, 595 ioreg_read(gpio_base + GPIO_OE) | ~mask); 596 #if 0 597 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 598 #else 599 ioreg_write(gpio_base + GPIO_DATAOUT, 600 ioreg_read(gpio_base + GPIO_DATAOUT) & ~mask); 601 #endif 602 break; 603 case conf_output_1: 604 ioreg_write(gpio_base + GPIO_OE, 605 ioreg_read(gpio_base + GPIO_OE) | ~mask); 606 #if 0 607 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 608 #else 609 ioreg_write(gpio_base + GPIO_DATAOUT, 610 ioreg_read(gpio_base + GPIO_DATAOUT) | mask); 611 #endif 612 break; 613 } 614 } 615 } 616 617 void 618 gxio_omap_gpio_write(int pin, int val) 619 { 620 vaddr_t gpio_base; 621 int mask; 622 623 KASSERT(pin / 32 < __arraycount(gpio_bases)); 624 625 gpio_base = gpio_bases[pin / 32]; 626 mask = 1 << (pin % 32); 627 if (val == 0) 628 ioreg_write(gpio_base + GPIO_CLEARDATAOUT, mask); 629 else 630 ioreg_write(gpio_base + GPIO_SETDATAOUT, mask); 631 } 632 633 /* 634 * configure for MUX, GPIO. 635 */ 636 void 637 gxio_config(void) 638 { 639 const struct omap_mux_conf *mux_conf[] = { 640 #if defined(OVERO) 641 overo_mux_i2c3_conf, 642 overo_mux_mmchs2_conf, 643 overo_mux_wireless_conf, 644 #elif defined(DUOVERO) 645 duovero_mux_led_conf, 646 duovero_mux_button_conf, 647 #elif defined(PEPPER) 648 pepper_mux_led_conf, 649 pepper_mux_button_conf, 650 pepper_mux_mmchs3_conf, 651 pepper_mux_audio_codec_conf, 652 #endif 653 }; 654 const struct omap_gpio_conf gpio_conf[] = { 655 #if defined(OVERO) 656 { 16, conf_output_0 }, /* Wireless: #Reset */ 657 #elif defined(PEPPER) 658 { 48, conf_output_0 }, /* Audio Codec: #Reset */ 659 #endif 660 { -1 } 661 }; 662 int i; 663 664 for (i = 0; i < __arraycount(mux_conf); i++) 665 gxio_omap_mux_config(mux_conf[i]); 666 gxio_omap_gpio_config(gpio_conf); 667 } 668 #endif 669 670 static int 671 gxio_find_default_expansion(void) 672 { 673 #ifdef GXIO_DEFAULT_EXPANSION 674 int i; 675 676 /* Find out the default expansion */ 677 for (i = 0; gxioconflist[i].name != NULL; i++) 678 if (strncasecmp(gxioconflist[i].name, GXIO_DEFAULT_EXPANSION, 679 strlen(gxioconflist[i].name) + 1) == 0) 680 break; 681 return gxioconflist[i].name == NULL ? -1 : i; 682 #else 683 return -1; 684 #endif 685 } 686 687 void 688 gxio_config_expansion(const char *expansion) 689 { 690 int i, d; 691 692 d = gxio_find_default_expansion(); 693 694 /* Print information about expansions */ 695 printf("supported expansions:\n"); 696 for (i = 0; gxioconflist[i].name != NULL; i++) 697 printf(" %s%s\n", gxioconflist[i].name, 698 i == d ? " (DEFAULT)" : ""); 699 700 701 if (expansion == NULL) { 702 printf("not specified 'expansion=' in the boot args.\n"); 703 i = -1; 704 } else { 705 for (i = 0; gxioconflist[i].name != NULL; i++) 706 if (strncasecmp(gxioconflist[i].name, expansion, 707 strlen(gxioconflist[i].name) + 1) == 0) 708 break; 709 if (gxioconflist[i].name == NULL) { 710 printf("unknown expansion specified: %s\n", expansion); 711 i = -1; 712 } 713 } 714 715 /* Do some magic stuff for PEPPER */ 716 #if defined(PEPPER) 717 if (i < 0) { 718 struct pepper_board_id { 719 unsigned int device_vendor; 720 #define GUMSTIX_PEPPER 0x30000200 /* 1st gen */ 721 #define GUMSTIX_PEPPER_DVI 0x31000200 /* DVI and newer */ 722 unsigned char revision; 723 unsigned char content; 724 char fab_revision[8]; 725 char env_var[16]; 726 char env_setting[64]; 727 } id; 728 const vaddr_t i2c_base = PEPPER_PRCM_VBASE + 0xb000; 729 const uint8_t eeprom = 0x50; 730 const uint8_t len = sizeof(id); 731 int rv; 732 733 rv = read_i2c_device(i2c_base, eeprom, 0x00, len, (void *)&id); 734 if (rv == 0) 735 if (id.device_vendor == GUMSTIX_PEPPER) { 736 printf("configure auto detected expansion" 737 " (pepper)\n"); 738 pepper_config(); 739 return; 740 } 741 } 742 #endif 743 744 /* 745 * Now proceed to configure the default expansion if one was 746 * specified (and found) or return. 747 */ 748 const char *toconfigure; 749 if (i < 0) { 750 #ifdef GXIO_DEFAULT_EXPANSION 751 if (d == -1) { 752 printf("default expansion (%s) not found\n", 753 GXIO_DEFAULT_EXPANSION); 754 return; 755 } 756 expansion = GXIO_DEFAULT_EXPANSION; 757 i = d; 758 toconfigure = "default"; 759 #else 760 return; 761 #endif 762 } else 763 toconfigure = "specified"; 764 765 printf("configure %s expansion (%s)\n", toconfigure, expansion); 766 gxioconflist[i].config(); 767 } 768 769 770 #if defined(GUMSTIX) 771 772 static void 773 basix_config(void) 774 { 775 776 pxa2x0_gpio_set_function(8, GPIO_ALT_FN_1_OUT); /* MMCCS0 */ 777 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_1_OUT); /* MMCCLK */ 778 #if 0 779 /* this configuration set by gxmci.c::pxamci_attach() */ 780 pxa2x0_gpio_set_function(11, GPIO_IN); /* nSD_DETECT */ 781 pxa2x0_gpio_set_function(22, GPIO_IN); /* nSD_WP */ 782 #endif 783 } 784 785 static void 786 cfstix_config(void) 787 { 788 u_int gpio, npoe_fn; 789 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 790 int bvd = (CPU_IS_PXA250) ? 4 : 111; 791 #else 792 #if defined(CPU_XSCALE_PXA270) 793 const int bvd = 111; 794 #else 795 const int bvd = 4; 796 #endif 797 #endif 798 799 if (CPU_IS_PXA250) { 800 gxpcic_slot_irqs[0].valid = 1; 801 gxpcic_slot_irqs[0].cd = 11; 802 gxpcic_slot_irqs[0].prdy = 26; 803 gxpcic_gpio_reset = 8; 804 } else { 805 gxpcic_slot_irqs[0].valid = 1; 806 gxpcic_slot_irqs[0].cd = 104; 807 gxpcic_slot_irqs[0].prdy = 96; 808 gxpcic_gpio_reset = 97; 809 } 810 811 #if 1 812 /* PCD/PRDY set by pxa2x0_pcic.c::pxapcic_attach_common() */ 813 #else 814 pxa2x0_gpio_set_function(11, GPIO_IN); /* PCD1 */ 815 pxa2x0_gpio_set_function(26, GPIO_IN); /* PRDY1/~IRQ1 */ 816 #endif 817 pxa2x0_gpio_set_function(bvd, GPIO_IN); /* BVD1/~STSCHG1 */ 818 819 for (gpio = 48, npoe_fn = 0; gpio <= 53 ; gpio++) 820 npoe_fn |= pxa2x0_gpio_get_function(gpio); 821 npoe_fn &= GPIO_SET; 822 823 pxa2x0_gpio_set_function(48, GPIO_ALT_FN_2_OUT | npoe_fn); /* nPOE */ 824 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 825 pxa2x0_gpio_set_function(50, GPIO_ALT_FN_2_OUT); /* nPIOR */ 826 pxa2x0_gpio_set_function(51, GPIO_ALT_FN_2_OUT); /* nPIOW */ 827 if (CPU_IS_PXA250) { 828 pxa2x0_gpio_set_function(52, GPIO_ALT_FN_2_OUT); /* nPCE1 */ 829 pxa2x0_gpio_set_function(53, GPIO_ALT_FN_2_OUT); /* nPCE2 */ 830 pxa2x0_gpio_set_function(54, GPIO_ALT_FN_2_OUT); /* pSKTSEL */ 831 } else { 832 pxa2x0_gpio_set_function(102, GPIO_ALT_FN_1_OUT); /* nPCE1 */ 833 pxa2x0_gpio_set_function(105, GPIO_ALT_FN_1_OUT); /* nPCE2 */ 834 pxa2x0_gpio_set_function(79, GPIO_ALT_FN_1_OUT); /* pSKTSEL */ 835 } 836 pxa2x0_gpio_set_function(55, GPIO_ALT_FN_2_OUT); /* nPREG */ 837 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); /* nPWAIT */ 838 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); /* nIOIS16 */ 839 } 840 841 static void 842 etherstix_config(void) 843 { 844 extern struct cfdata cfdata[]; 845 #if defined(CPU_XSCALE_PXA270) && defined(CPU_XSCALE_PXA250) 846 int rst = (CPU_IS_PXA250) ? 80 : 32; 847 int irq = (CPU_IS_PXA250) ? 36 : 99; 848 #else 849 #if defined(CPU_XSCALE_PXA270) 850 const int rst = 32, irq = 99; 851 #else 852 const int rst = 80, irq = 36; 853 #endif 854 #endif 855 int i; 856 857 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 858 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 859 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_SET); /* RESET 1 */ 860 delay(1); 861 pxa2x0_gpio_set_function(rst, GPIO_OUT | GPIO_CLR); 862 delay(50000); 863 864 for (i = 0; cfdata[i].cf_name != NULL; i++) 865 if (strcmp(cfdata[i].cf_name, "sm") == 0 && 866 strcmp(cfdata[i].cf_atname, "sm_gxio") == 0 && 867 cfdata[i].cf_loc[GXIOCF_ADDR] == 0x04000300 && 868 cfdata[i].cf_loc[GXIOCF_GPIRQ] == GXIOCF_GPIRQ_DEFAULT) 869 cfdata[i].cf_loc[GXIOCF_GPIRQ] = irq; 870 } 871 872 static void 873 netcf_config(void) 874 { 875 876 etherstix_config(); 877 cfstix_config(); 878 } 879 880 static void 881 netcf_vx_config(void) 882 { 883 884 /* 885 * XXXX: More power is necessary for NIC and USB??? 886 * (no document. from Linux) 887 */ 888 889 pxa2x0_gpio_set_function(27, GPIO_IN); 890 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); 891 pxa2x0_gpio_set_function(118, GPIO_ALT_FN_1_IN | GPIO_CLR); 892 893 etherstix_config(); 894 cfstix_config(); 895 if (CPU_IS_PXA270) { 896 /* Overwrite */ 897 gxpcic_slot_irqs[0].cd = 104; 898 gxpcic_slot_irqs[0].prdy = 109; 899 gxpcic_gpio_reset = 110; 900 }; 901 } 902 903 static void 904 netduommc_config(void) 905 { 906 907 netduo_config(); 908 basix_config(); 909 } 910 911 static void 912 netduo_config(void) 913 { 914 915 etherstix_config(); 916 917 pxa2x0_gpio_set_function(78, GPIO_ALT_FN_2_OUT); /* nCS 2 */ 918 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_SET); /* RESET 2 */ 919 delay(1); 920 pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_CLR); 921 delay(50000); 922 } 923 924 static void 925 netmicrosd_config(void) 926 { 927 928 /* MicroSD(mci) always configure on PXA270 */ 929 930 pxa2x0_gpio_set_function(49, GPIO_ALT_FN_2_OUT); /* nPWE */ 931 pxa2x0_gpio_set_function(15, GPIO_ALT_FN_2_OUT); /* nCS 1 */ 932 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_CLR); /* RESET 1 */ 933 delay(hz / 2); 934 pxa2x0_gpio_set_function(107, GPIO_OUT | GPIO_SET); 935 delay(50000); 936 } 937 938 static void 939 netwifimicrosd_config(void) 940 { 941 942 netmicrosd_config(); 943 944 cfstix_config(); 945 /* However use pxamci. */ 946 pxa2x0_gpio_set_function(111, GPIO_CLR | GPIO_ALT_FN_1_IN); 947 /* Power to Marvell 88W8385 */ 948 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 949 } 950 951 static void 952 netmmc_config(void) 953 { 954 955 etherstix_config(); 956 basix_config(); 957 } 958 959 static void 960 wifistix_config(void) 961 { 962 963 cfstix_config(); 964 965 /* Power to Marvell 88W8385 */ 966 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 967 } 968 969 static void 970 wifistix_cf_config(void) 971 { 972 973 gxpcic_slot_irqs[1].valid = 1; 974 gxpcic_slot_irqs[1].cd = 36; 975 gxpcic_slot_irqs[1].prdy = 27; 976 977 #if 1 978 /* this configuration set by pxa2x0_pcic.c::pxapcic_attach_common() */ 979 #else 980 pxa2x0_gpio_set_function(36, GPIO_IN); /* PCD2 */ 981 pxa2x0_gpio_set_function(27, GPIO_IN); /* PRDY2/~IRQ2 */ 982 #endif 983 pxa2x0_gpio_set_function(18, GPIO_IN); /* BVD2/~STSCHG2 */ 984 985 cfstix_config(); 986 987 /* Power to Marvell 88W8385 */ 988 pxa2x0_gpio_set_function(80, GPIO_OUT | GPIO_SET); 989 } 990 991 #elif defined(OVERO) 992 993 static void 994 eth0_config(void) 995 { 996 /* 997 * ETH0 connects via CS5. It use GPIO 176 for IRQ. 998 * Also GPIO 64 is NRESET. 999 */ 1000 1001 smsh_config(NULL, 176, 64); 1002 } 1003 1004 static void 1005 eth1_config(void) 1006 { 1007 struct omap_mux_conf eth1_mux_conf[] = { 1008 { 0x0d2, MUXMODE(4) | INPUTENABLE }, 1009 { -1 } 1010 }; 1011 1012 /* 1013 * ETH1 connects via CS4. It use GPIO 65 for IRQ. 1014 */ 1015 1016 smsh_config(eth1_mux_conf, 65, 64); 1017 } 1018 1019 static void 1020 dvi_config(void) 1021 { 1022 static const struct omap_mux_conf overo_mux_dvi_conf[] = { 1023 { 0x0d4, MUXMODE(0) }, /* dss_pclk */ 1024 { 0x0d6, MUXMODE(0) }, /* dss_pclk */ 1025 { 0x0d8, MUXMODE(0) }, /* dss_pclk */ 1026 { 0x0da, MUXMODE(0) }, /* dss_pclk */ 1027 { 0x0dc, MUXMODE(0) }, /* dss_pclk */ 1028 { 0x0de, MUXMODE(0) }, /* dss_pclk */ 1029 { 0x0e0, MUXMODE(0) }, /* dss_pclk */ 1030 { 0x0e2, MUXMODE(0) }, /* dss_pclk */ 1031 { 0x0e4, MUXMODE(0) }, /* dss_pclk */ 1032 { 0x0e6, MUXMODE(0) }, /* dss_pclk */ 1033 { 0x0e8, MUXMODE(0) }, /* dss_pclk */ 1034 { 0x0ea, MUXMODE(0) }, /* dss_pclk */ 1035 { 0x0ec, MUXMODE(0) }, /* dss_pclk */ 1036 { 0x0ee, MUXMODE(0) }, /* dss_pclk */ 1037 { 0x0f0, MUXMODE(0) }, /* dss_pclk */ 1038 { 0x0f2, MUXMODE(0) }, /* dss_pclk */ 1039 { 0x0f4, MUXMODE(0) }, /* dss_pclk */ 1040 { 0x0f6, MUXMODE(0) }, /* dss_pclk */ 1041 { 0x0f8, MUXMODE(0) }, /* dss_pclk */ 1042 { 0x0fa, MUXMODE(0) }, /* dss_pclk */ 1043 { 0x0fc, MUXMODE(0) }, /* dss_pclk */ 1044 { 0x0fe, MUXMODE(0) }, /* dss_pclk */ 1045 { 0x100, MUXMODE(0) }, /* dss_pclk */ 1046 { 0x102, MUXMODE(0) }, /* dss_pclk */ 1047 { 0x104, MUXMODE(0) }, /* dss_pclk */ 1048 { 0x106, MUXMODE(0) }, /* dss_pclk */ 1049 { 0x108, MUXMODE(0) }, /* dss_pclk */ 1050 { 0x10a, MUXMODE(0) }, /* dss_pclk */ 1051 { -1 } 1052 }; 1053 1054 gxio_omap_mux_config(overo_mux_dvi_conf); 1055 } 1056 1057 static void 1058 lcd_config(char type) 1059 { 1060 static const struct omap_mux_conf overo_mux_mcspi1_conf[] = { 1061 { 0x1c8, MUXMODE(0) | INPUTENABLE }, /* mcspi1_clk */ 1062 { 0x1ca, MUXMODE(0) | INPUTENABLE }, /* mcspi1_simo*/ 1063 { 0x1cc, MUXMODE(0) | INPUTENABLE }, /* mcspi1_somi*/ 1064 { 0x1ce, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs0 */ 1065 { 0x1d0, MUXMODE(0) | INPUTENABLE }, /* mcspi1_cs1 */ 1066 { -1 } 1067 }; 1068 static const struct omap_mux_conf overo_mux_ads7846_conf[] = { 1069 { 0x138, /* gpio_114: NPENIRQ */ 1070 MUXMODE(4) | PULLUDENABLE | INPUTENABLE }, 1071 { -1 } 1072 }; 1073 static const struct omap_mux_conf overo_mux_lcd_conf[] = { 1074 { 0x174, MUXMODE(4) }, /* gpio_144: DISPLAY_EN */ 1075 { 0x176, MUXMODE(4) }, /* gpio_145: Brightness */ 1076 { -1 } 1077 }; 1078 1079 static const struct omap_gpio_conf overo_gpio_lcd_conf[] = { 1080 { 144, conf_output_0 }, /* DISPLAY_EN */ 1081 { 145, conf_output_0 }, /* Brightness */ 1082 { -1 } 1083 }; 1084 1085 dvi_config(); 1086 if (type != 'C') { 1087 gxio_omap_mux_config(overo_mux_mcspi1_conf); 1088 gxio_omap_mux_config(overo_mux_ads7846_conf); 1089 } 1090 gxio_omap_mux_config(overo_mux_lcd_conf); 1091 1092 gxio_omap_gpio_config(overo_gpio_lcd_conf); 1093 } 1094 1095 enum { 1096 uart1_if_exists = 0, 1097 force_uart1 1098 }; 1099 static void 1100 header_40pin_config(int uart1) 1101 { 1102 static const struct omap_mux_conf overo_mux_40pin_header_conf[] = { 1103 /* 1104 * 1: GND 1105 * 2: VCC_3.3 1106 * 3: GPIO171_SPI1_CLK 1107 * 4: GPIO114_SPI1_NIRQ 1108 * 5: GPIO172_SPI1_MOSI 1109 * 6: GPIO174_SPI1_CS0 1110 * 7: GPIO173_SPI1_MISO 1111 * 8: GPIO175_SPI1_CS1 1112 * 9: GPIO151_RXD1 1113 * 10: GPIO148_TXD1 1114 * 11: SYS_EN 1115 * 12: VBACKUP 1116 * 13: GPIO0_WAKEUP 1117 * 14: POWERON 1118 * 15: GND 1119 * 16: VCC_1.8 1120 * 17: GPIO128_GPS_PPS 1121 * 18: GPIO127_TS_IRQ 1122 * 19: GPIO170_HDQ_1WIRE 1123 * 20: GPIO163_IR_CTS3 1124 * 21: GPIO165_IR_RXD3 (console) 1125 * 22: GPIO166_IR_TXD3 (console) 1126 * 23: GPIO184_SCL3 (system eeprom) 1127 * 24: GPIO185_SDA3 (system eeprom) 1128 * 25: GND 1129 * 26: VCC_1.8 1130 * 27: GPIO146_PWM11 1131 * 28: GPIO145_PWM10 1132 * 29: GPIO147_PWM8 1133 * 30: GPIO144_PWM9 1134 * 31: PWM0 (TPS65950) 1135 * 32: PWM1 (TPS65950) 1136 * 33: ADCIN7 (TPS65950) 1137 * 34: ADCIN2 (TPS65950) 1138 * 35: ADCIN6 (TPS65950) 1139 * 36: ADCIN5 (TPS65950) 1140 * 37: AGND (TPS65950) 1141 * 38: ADCIN3 (TPS65950) 1142 * 39: ADCIN4 (TPS65950) 1143 * 40: VIN (TPS65950) 1144 */ 1145 1146 { 0x152, MUXMODE(4) | INPUTENABLE }, /* gpio_127 */ 1147 { 0x154, MUXMODE(4) | INPUTENABLE }, /* gpio_128 */ 1148 { 0x174, MUXMODE(4) | INPUTENABLE }, /* gpio_144 */ 1149 { 0x176, MUXMODE(4) | INPUTENABLE }, /* gpio_145 */ 1150 { 0x178, MUXMODE(4) | INPUTENABLE }, /* gpio_146 */ 1151 { 0x17a, MUXMODE(4) | INPUTENABLE }, /* gpio_147 */ 1152 { 0x19a, MUXMODE(4) | INPUTENABLE }, /* gpio_163 */ 1153 { -1 } 1154 }; 1155 static const struct omap_mux_conf overo_mux_uart1_conf[] = { 1156 { 0x17c, MUXMODE(0) }, /* uart1_tx */ 1157 { 0x182, MUXMODE(0) | INPUTENABLE }, /* uart1_rx */ 1158 { -1 } 1159 }; 1160 static const struct omap_mux_conf overo_mux_no_uart1_conf[] = { 1161 { 0x17c, MUXMODE(4) | INPUTENABLE }, /* gpio_148 */ 1162 { 0x182, MUXMODE(4) | INPUTENABLE }, /* gpio_151 */ 1163 { -1 } 1164 }; 1165 static const struct omap_mux_conf overo_mux_hdq_conf[] = { 1166 #if 0 1167 { 0x1c4, MUXMODE(0) | ??? | INPUTENABLE }, /* hdq_sio */ 1168 #endif 1169 { -1 } 1170 }; 1171 static const struct omap_mux_conf overo_mux_no_hdq_conf[] = { 1172 { 0x1c4, MUXMODE(4) | INPUTENABLE }, /* gpio_170 */ 1173 { -1 } 1174 }; 1175 1176 gxio_omap_mux_config(overo_mux_40pin_header_conf); 1177 if (uart1 == force_uart1) 1178 gxio_omap_mux_config(overo_mux_uart1_conf); 1179 else 1180 gxio_omap_mux_config_address("com", 0x4806a000, 1181 overo_mux_uart1_conf, overo_mux_no_uart1_conf); 1182 gxio_omap_mux_config_address("hdq", 0x480b2000, 1183 overo_mux_hdq_conf, overo_mux_no_hdq_conf); 1184 } 1185 1186 static void 1187 chestnut_config(void) 1188 { 1189 static const struct omap_mux_conf chestnut_mux_conf[] = { 1190 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1191 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1192 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1193 { -1 } 1194 }; 1195 1196 eth0_config(); 1197 lcd_config('R'); 1198 1199 header_40pin_config(uart1_if_exists); 1200 gxio_omap_mux_config(chestnut_mux_conf); 1201 } 1202 1203 static void 1204 gallop_config(void) 1205 { 1206 static const struct omap_mux_conf gallop43_mux_conf[] = { 1207 { 0x5ec, MUXMODE(4) }, /* gpio_22: LED (Blue)*/ 1208 { 0x5ee, MUXMODE(4) | INPUTENABLE }, /* gpio_23: Button */ 1209 { 0x5dc, MUXMODE(4) | INPUTENABLE }, /* gpio_14: Button */ 1210 { -1 } 1211 }; 1212 1213 lcd_config('R'); 1214 1215 header_40pin_config(force_uart1); 1216 gxio_omap_mux_config(gallop43_mux_conf); 1217 } 1218 1219 static void 1220 summit_config(void) 1221 { 1222 1223 dvi_config(); 1224 1225 header_40pin_config(uart1_if_exists); 1226 } 1227 1228 static void 1229 tobi_config(void) 1230 { 1231 1232 eth0_config(); 1233 dvi_config(); 1234 1235 header_40pin_config(uart1_if_exists); 1236 } 1237 1238 static void 1239 tobiduo_config(void) 1240 { 1241 1242 eth0_config(); 1243 eth1_config(); 1244 } 1245 1246 #elif defined(DUOVERO) 1247 1248 static void 1249 ehci_config(void) 1250 { 1251 uint32_t val; 1252 1253 #define SCRM_ALTCLKSRC 0xa110 1254 #define ALTCLKSRC_ENABLE_EXT (1 << 3) 1255 #define ALTCLKSRC_ENABLE_INT (1 << 2) 1256 #define ALTCLKSRC_MODE_MASK (3 << 0) 1257 #define ALTCLKSRC_MODE_POWERDOWN (0 << 0) 1258 #define ALTCLKSRC_MODE_ACTIVE (1 << 0) 1259 #define ALTCLKSRC_MODE_BYPASS (2 << 0) 1260 #define SCRM_AUXCLK3 0xa31c 1261 #define AUXCLK3_CLKDIV(n) (((n) - 1) << 16) 1262 #define AUXCLK3_CLKDIV_MASK (0xf << 16) 1263 #define AUXCLK3_ENABLE (1 << 8) 1264 #define AUXCLK3_SRCSELECT_MASK (3 << 1) 1265 #define AUXCLK3_SRCSELECT_SYSCLK (0 << 1) 1266 #define AUXCLK3_SRCSELECT_CORE (1 << 1) 1267 #define AUXCLK3_SRCSELECT_PERDPLL (2 << 1) 1268 #define AUXCLK3_SRCSELECT_ALTCLK (3 << 1) 1269 #define AUXCLK3_POLARITY_LOW (0 << 0) 1270 #define AUXCLK3_POLARITY_HIGH (1 << 0) 1271 1272 /* Use the 1/2 auxiliary clock #3 of system clock. */ 1273 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3); 1274 val &= ~(AUXCLK3_CLKDIV_MASK | AUXCLK3_SRCSELECT_MASK); 1275 val |= (AUXCLK3_CLKDIV(2) | AUXCLK3_ENABLE | AUXCLK3_SRCSELECT_SYSCLK); 1276 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_AUXCLK3, val); 1277 1278 val = ioreg_read(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC); 1279 val &= ~ALTCLKSRC_MODE_MASK; 1280 val |= ALTCLKSRC_MODE_ACTIVE; 1281 val |= (ALTCLKSRC_ENABLE_EXT | ALTCLKSRC_ENABLE_INT); 1282 ioreg_write(DUOVERO_L4_WAKEUP_VBASE + SCRM_ALTCLKSRC, val); 1283 } 1284 1285 static void 1286 parlor_config(void) 1287 { 1288 #if 0 1289 static const struct omap_mux_conf parlor_mux_40pin_header_conf[] = { 1290 /* 1291 * 1: GND 1292 * 2: GND 1293 * 3: MCSPI1_CLK or GPIO 134 1294 * 4: MCSPI1_CS0 or GPIO 137 1295 * 5: MCSPI1_SIMO or GPIO 136 1296 * 6: MCSPI1_CS1 or GPIO 138 1297 * 7: MCSPI1_SOMI or GPIO 135 1298 * 8: MCSPI1_CS2 or GPIO 139 1299 * 9: HDQ_SIO or GPIO 127 1300 * 10: MCSPI1_CS3 or GPIO 140 1301 * 11: SDMMC3_CMD or GPIO ??? 1302 * 12: I2C2_SCL or GPIO 128 1303 * 13: SDMMC3_CLK or GPIO ??? 1304 * 14: I2C2_SDA or GPIO 129 1305 * 15: UART2_TX or SDMMC3_DAT1 or GPIO 126 1306 * 16: PMIC_PWM2 (TWL6030) 1307 * 17: UART2_RX or SDMMC3_DAT0 or GPIO 125 1308 * 18: PMIC_PWM1 (TWL6030) 1309 * 19: BSP2_CLKX or GPIO 110 1310 * 20: BSP2_FSX or GPIO 113 1311 * 21: BSP2_DX or GPIO 112 1312 * 22: BSP2_DR or GPIO 111 1313 * 23: BSP2_CLKS or GPIO 118 1314 * 24: FREF1 1315 * 25: MCSPI4_SOMI or GPIO 153 1316 * 26: PMIC_NRESWARN 1317 * 27: MCSPI4_SIMO or GPIO 152 1318 * 28: SYSEN 1319 * 29: MCSPI4_CLK or GPIO 151 1320 * 30: PWRON 1321 * 31: MCSPI4_CS0 or GPIO 154 1322 * 32: REGEN1 1323 * 33: ADCIN3 (TWL6030) 1324 * 34: VCC_1.0 1325 * 35: ADCIN4_VREF (TWL6030) 1326 * 36: VDD_VAUX2 1327 * 37: ADCIN4 (TWL6030) 1328 * 38: VCC_3.3 1329 * 39: ADCIN5 (TWL6030) 1330 * 40: V_BATT_5 1331 */ 1332 { -1 } 1333 }; 1334 #endif 1335 static const struct omap_mux_conf parlor_mux_mcspi1_conf[] = { 1336 #if 0 1337 { 0x132, /* 3: MCSPI1_CLK */ 1338 MUXMODE(0) | ??? }, 1339 { 0x138, /* 4: MCSPI1_CS0 */ 1340 MUXMODE(0) | ??? }, 1341 { 0x136, /* 5: MCSPI1_SIMO */ 1342 MUXMODE(0) | ??? }, 1343 { 0x13a, /* 6: MCSPI1_CS1 */ 1344 MUXMODE(0) | ??? }, 1345 { 0x134, /* 7: MCSPI1_SOMI */ 1346 MUXMODE(0) | ??? | INPUTENABLE }, 1347 { 0x13c, /* 8: MCSPI1_CS2 */ 1348 MUXMODE(0) | ??? }, 1349 { 0x13e, /* 10: MCSPI1_CS3 */ 1350 MUXMODE(0) | ??? }, 1351 #endif 1352 { -1 } 1353 }; 1354 static const struct omap_mux_conf parlor_mux_no_mcspi1_conf[] = { 1355 { 0x132, /* 3: GPIO 134 */ 1356 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1357 { 0x138, /* 4: GPIO 137 */ 1358 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1359 { 0x136, /* 5: GPIO 136 */ 1360 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1361 { 0x13a, /* 6: GPIO 138 */ 1362 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1363 { 0x134, /* 7: GPIO 135 */ 1364 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1365 { 0x13c, /* 8: GPIO 139 */ 1366 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1367 { 0x13e, /* 10: GPIO 140 */ 1368 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1369 { -1 } 1370 }; 1371 static const struct omap_mux_conf parlor_mux_hdq_conf[] = { 1372 #if 0 1373 { 0x120, /* 9: HDQ_SIO */ 1374 MUXMODE(0) | ??? | INPUTENABLE }, 1375 #endif 1376 { -1 } 1377 }; 1378 static const struct omap_mux_conf parlor_mux_no_hdq_conf[] = { 1379 { 0x120, /* 9: GPIO_127 */ 1380 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1381 { -1 } 1382 }; 1383 static const struct omap_mux_conf parlor_mux_i2c2_conf[] = { 1384 { 0x126, /* 12: I2C2_SCL */ 1385 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1386 { 0x128, /* 14: I2C2_SDA */ 1387 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1388 { -1 } 1389 }; 1390 static const struct omap_mux_conf parlor_mux_no_i2c2_conf[] = { 1391 { 0x126, /* 12: GPIO 128 */ 1392 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1393 { 0x128, /* 14: GPIO 129 */ 1394 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1395 { -1 } 1396 }; 1397 static const struct omap_mux_conf parlor_mux_sdmmc3_conf[] = { 1398 #if 0 1399 11 SDMMC3_CMD DuoVero J2 A15 <- omap pin AG10 1400 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1401 13 SDMMC3_CLK DuoVero J2 A16 <- omap pin AE9 1402 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1403 #endif 1404 { 0x11c, /* 17: SDMMC3_DAT0 */ 1405 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1406 { 0x11e, /* 15: SDMMC3_DAT1 */ 1407 MUXMODE(1) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1408 { -1 } 1409 }; 1410 static const struct omap_mux_conf parlor_mux_uart2_conf[] = { 1411 { 0x11c, /* 17: UART2_RX */ 1412 MUXMODE(0) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1413 { 0x11e, 1414 MUXMODE(0) | PULLUDENABLE }, /* 15: UART2_TX */ 1415 { -1 } 1416 }; 1417 static const struct omap_mux_conf parlor_mux_no_uart2_conf[] = { 1418 { 0x11c, /* 17: GPIO 125 */ 1419 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1420 { 0x11e, /* 15: GPIO 126 */ 1421 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1422 { -1 } 1423 }; 1424 static const struct omap_mux_conf parlor_mux_bsp2_conf[] = { 1425 { 0x0f6, /* 19: BSP2_CLKX */ 1426 MUXMODE(0) | INPUTENABLE }, 1427 { 0x0fc, /* 20: BSP2_FSX */ 1428 MUXMODE(0) | INPUTENABLE }, 1429 { 0x0fa, /* 21: BSP2_DX */ 1430 MUXMODE(0) | PULLUDENABLE }, 1431 { 0x0f8, /* 22: BSP2_DR */ 1432 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1433 { 0x10e, /* 23: BSP2_CLKS */ 1434 MUXMODE(0) | PULLUDENABLE | INPUTENABLE }, 1435 { -1 } 1436 }; 1437 static const struct omap_mux_conf parlor_mux_no_bsp2_conf[] = { 1438 { 0x0f6, /* 19: GPIO 110 */ 1439 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1440 { 0x0fc, /* 20: GPIO 113 */ 1441 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1442 { 0x0fa, /* 21: GPIO 112 */ 1443 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1444 { 0x0f8, /* 22: GPIO 111 */ 1445 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1446 { 0x10e, /* 23: GPIO 118 */ 1447 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1448 { -1 } 1449 }; 1450 static const struct omap_mux_conf parlor_mux_mcspi4_conf[] = { 1451 #if 0 1452 { 0x158, /* 25: MCSPI4_SOMI */ 1453 MUXMODE(0) | ??? | INPUTENABLE }, 1454 { 0x156, /* 27: MCSPI4_SIMO */ 1455 MUXMODE(0) | ??? }, 1456 { 0x154, /* 29: MCSPI4_CLK */ 1457 MUXMODE(0) | ??? }, 1458 { 0x15a, /* 31: MCSPI4_CS0 */ 1459 MUXMODE(0) | ??? }, 1460 #endif 1461 { -1 } 1462 }; 1463 static const struct omap_mux_conf parlor_mux_no_mcspi4_conf[] = { 1464 { 0x158, /* 25: GPIO 153 */ 1465 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1466 { 0x156, /* 27: GPIO 152 */ 1467 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1468 { 0x154, /* 29: GPIO 151 */ 1469 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1470 { 0x15a, /* 31: GPIO 154 */ 1471 MUXMODE(3) | PULLUDENABLE | PULLTYPESELECT | INPUTENABLE }, 1472 { -1 } 1473 }; 1474 1475 /* 1476 * ETH0 connects via CS5. It use GPIO 44 for IRQ. 1477 * Also GPIO 45 is NRESET. 1478 */ 1479 smsh_config(NULL, 44, 45); 1480 1481 ehci_config(); 1482 1483 gxio_omap_mux_config_address("mcspi", 0x48098000, 1484 parlor_mux_mcspi1_conf, parlor_mux_no_mcspi1_conf); 1485 gxio_omap_mux_config_address("hdq", 0x480b2000, 1486 parlor_mux_hdq_conf, parlor_mux_no_hdq_conf); 1487 gxio_omap_mux_config_address("tiiic", 0x48072000, 1488 parlor_mux_i2c2_conf, parlor_mux_no_i2c2_conf); 1489 if (gxio_omap_mux_config_address("sdhc", 0x480ad000, 1490 parlor_mux_sdmmc3_conf, NULL) != 0) 1491 gxio_omap_mux_config_address("com", 0x4806c000, 1492 parlor_mux_uart2_conf, parlor_mux_no_uart2_conf); 1493 gxio_omap_mux_config_address("mcbsp", 0x49024000, 1494 parlor_mux_bsp2_conf, parlor_mux_no_bsp2_conf); 1495 gxio_omap_mux_config_address("mcspi", 0x480ba000, 1496 parlor_mux_mcspi4_conf, parlor_mux_no_mcspi4_conf); 1497 } 1498 1499 #elif defined(PEPPER) 1500 1501 static void 1502 lcd_config(void) 1503 { 1504 static const struct tifb_panel_info panel_lcd = { 1505 .panel_tft = 1, 1506 .panel_mono = false, 1507 .panel_bpp = 24, 1508 1509 .panel_pxl_clk = 18400000, 1510 .panel_width = 480, 1511 .panel_height = 272, 1512 .panel_hfp = 8, 1513 .panel_hbp = 4, 1514 .panel_hsw = 41, 1515 .panel_vfp = 4, 1516 .panel_vbp = 2, 1517 .panel_vsw = 10, 1518 .panel_invert_hsync = 0, 1519 .panel_invert_vsync = 0, 1520 1521 .panel_ac_bias = 255, 1522 .panel_ac_bias_intrpt = 0, 1523 .panel_dma_burst_sz = 16, 1524 .panel_fdd = 0x80, 1525 .panel_sync_edge = 0, 1526 .panel_sync_ctrl = 1, 1527 .panel_tft_alt_mode = 0, 1528 .panel_invert_pxl_clk = 0, 1529 }; 1530 static const struct omap_mux_conf pepper_mux_lcd_conf[] = { 1531 /* 1532 * LCD_DATA[0-23] configures in tifb.c 1533 */ 1534 1535 { 0x8e0, MMODE(0) | PUDEN }, /* LCD_VSYNC */ 1536 { 0x8e4, MMODE(0) | PUDEN }, /* LCD_HSYNC */ 1537 { 0x8e8, MMODE(0) | PUDEN }, /* LCD_PCLK */ 1538 { 0x8ec, MMODE(0) | PUDEN }, /* LCD_AC_BIAS_EN */ 1539 1540 { 0x86c, MMODE(7) | PUTYPESEL }, /* GPIO 59: Enable */ 1541 { -1 } 1542 }; 1543 1544 if (gxio_omap_mux_config_address("tifb", 0x4830e000, 1545 pepper_mux_lcd_conf, NULL) == 0) { 1546 extern const struct tifb_panel_info *tifb_panel_info; 1547 extern bool use_tps65217_wled; 1548 1549 tifb_panel_info = &panel_lcd; 1550 use_tps65217_wled = true; 1551 } 1552 } 1553 1554 static void 1555 pepper43_config(void) 1556 { 1557 static const struct omap_mux_conf pepper43_mux_wilink8_conf[] = { 1558 /* TI WiLink 8 */ 1559 { 0x800, MMODE(7) | PUTYPESEL }, /* GPIO 32: Bluetooth */ 1560 { 0x804, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 33: irq */ 1561 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: WiFi */ 1562 { -1 } 1563 }; 1564 static const struct omap_mux_conf pepper43_mux_i2c1_conf[] = { 1565 { 0x968, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1566 { 0x96c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1567 { -1 } 1568 }; 1569 static const struct omap_mux_conf pepper43_mpu9150_conf[] = { 1570 /* MPU9150 at I2C1 */ 1571 { 0x808, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 34: IRQ */ 1572 { 0x898, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 68 */ 1573 { 0x870, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 30 */ 1574 { -1 } 1575 }; 1576 static const struct omap_mux_conf pepper43_mux_20pin_header_conf[] = { 1577 { 0x85c, MMODE(7) | PUDEN | RXACTIVE }, /* 1: GPIO 55 */ 1578 { 0x80c, MMODE(7) | PUDEN | RXACTIVE }, /* 2: GPIO 35 */ 1579 { 0x810, MMODE(7) | PUDEN | RXACTIVE }, /* 3: GPIO 36 */ 1580 { 0x814, MMODE(7) | PUDEN | RXACTIVE }, /* 4: GPIO 37 */ 1581 { 0x818, MMODE(7) | PUDEN | RXACTIVE }, /* 5: GPIO 38 */ 1582 { 0x81c, MMODE(7) | PUDEN | RXACTIVE }, /* 6: GPIO 39 */ 1583 { 0x87c, MMODE(7) | PUDEN | RXACTIVE }, /* 7: GPIO 61 */ 1584 { 0x880, MMODE(7) | PUDEN | RXACTIVE }, /* 8: GPIO 62 */ 1585 { 0x884, MMODE(7) | PUDEN | RXACTIVE }, /* 9: GPIO 63 */ 1586 { 0x9e4, MMODE(7) | PUDEN | RXACTIVE }, /* 10: GPIO 103 */ 1587 { 0x9e8, MMODE(7) | PUDEN | RXACTIVE }, /* 11: GPIO 104 */ 1588 { 0x9b0, MMODE(7) | PUDEN | RXACTIVE }, /* 12: GPIO 19 */ 1589 #if 0 /* UART3 or GPIO */ 1590 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* 13: GPIO 7 */ 1591 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* 14: GPIO 6 */ 1592 #endif 1593 #if 0 /* UART2 or GPIO */ 1594 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* 15: GPIO 98 */ 1595 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* 16: GPIO 97 */ 1596 #endif 1597 /* 17: VCC 5v */ 1598 /* 18: VCC 3.3v */ 1599 /* 19: GND */ 1600 /* 20: GND */ 1601 { -1 } 1602 }; 1603 static const struct omap_mux_conf pepper43_mux_uart2_conf[] = { 1604 { 0x90c, MMODE(6) | PUTYPESEL | RXACTIVE }, /* UART2_RXD */ 1605 { 0x910, MMODE(6) | PUDEN }, /* UART2_TXD */ 1606 { -1 } 1607 }; 1608 static const struct omap_mux_conf pepper43_mux_no_uart2_conf[] = { 1609 { 0x90c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 97 */ 1610 { 0x910, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 98 */ 1611 { -1 } 1612 }; 1613 static const struct omap_mux_conf pepper43_mux_uart3_conf[] = { 1614 { 0x960, MMODE(1) | PUTYPESEL | RXACTIVE }, /* UART3_RXD */ 1615 { 0x964, MMODE(1) | PUDEN }, /* UART3_TXD */ 1616 { -1 } 1617 }; 1618 static const struct omap_mux_conf pepper43_mux_no_uart3_conf[] = { 1619 { 0x960, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 6 */ 1620 { 0x964, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 7 */ 1621 { -1 } 1622 }; 1623 1624 static const struct omap_mux_conf *pepper43_mux_conf[] = { 1625 pepper43_mux_wilink8_conf, 1626 pepper43_mux_i2c1_conf, 1627 pepper43_mpu9150_conf, 1628 pepper43_mux_20pin_header_conf, 1629 }; 1630 1631 static const struct omap_gpio_conf pepper43_gpio_wl18xx_conf[] = { 1632 { 32, conf_output_0 }, /* #Reset: Bluetooth */ 1633 { 56, conf_output_0 }, /* #Reset: WiFi */ 1634 { -1 } 1635 }; 1636 int i; 1637 1638 lcd_config(); 1639 1640 for (i = 0; i < __arraycount(pepper43_mux_conf); i++) 1641 gxio_omap_mux_config(pepper43_mux_conf[i]); 1642 gxio_omap_gpio_config(pepper43_gpio_wl18xx_conf); 1643 1644 #if 0 1645 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 52 (Blue) */ 1646 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 20)); 1647 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1648 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 20)); 1649 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_OE, /* GPIO 53 (Red) */ 1650 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_OE) & ~(1 << 21)); 1651 ioreg_write(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT, 1652 ioreg_read(gpio1_base + GPIO_SIZE2 + GPIO_DATAOUT) | (1 << 21)); 1653 #endif 1654 1655 gxio_omap_mux_config_address("com", 0x48024000, 1656 pepper43_mux_uart2_conf, pepper43_mux_no_uart2_conf); 1657 gxio_omap_mux_config_address("com", 0x481a6000, 1658 pepper43_mux_uart3_conf, pepper43_mux_no_uart3_conf); 1659 } 1660 1661 static void 1662 pepper_config(void) 1663 { 1664 static const struct omap_mux_conf pepper_mux_button2_conf[] = { 1665 { 0x85c, MMODE(7) | PUTYPESEL | RXACTIVE }, /* GPIO 55 */ 1666 { -1 } 1667 }; 1668 static const struct omap_mux_conf pepper_mux_i2c1_conf[] = { 1669 { 0x90c, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SDA */ 1670 { 0x910, MMODE(3) | PUTYPESEL | RXACTIVE }, /* I2C1_SCL */ 1671 { -1 } 1672 }; 1673 static const struct omap_mux_conf pepper_mux_wi2wi_conf[] = { 1674 { 0x9b4, MMODE(3) | PUDEN }, /* CLKOUT2 */ 1675 /* Wi2Wi */ 1676 { 0x860, MMODE(7) | PUTYPESEL }, /* GPIO 56: nReset */ 1677 { 0x870, MMODE(7) | PUTYPESEL }, /* GPIO 30: nPower */ 1678 { -1 } 1679 }; 1680 static const struct omap_mux_conf pepper_mux_uart1_conf[] = { 1681 { 0x978, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_CTSn */ 1682 { 0x97c, MMODE(0) }, /* UART1_RTSn */ 1683 { 0x980, MMODE(0) | PUTYPESEL | RXACTIVE }, /* UART1_RXD */ 1684 { 0x984, MMODE(0) }, /* UART1_TXD */ 1685 { -1 } 1686 }; 1687 static const struct omap_mux_conf pepper_mux_no_uart1_conf[] = { 1688 { 0x978, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 12 */ 1689 { 0x97c, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 13 */ 1690 { 0x980, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 14 */ 1691 { 0x984, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 15 */ 1692 { -1 } 1693 }; 1694 static const struct omap_mux_conf *pepper_mux_conf[] = { 1695 pepper_mux_button2_conf, 1696 pepper_mux_i2c1_conf, 1697 pepper_mux_wi2wi_conf, 1698 }; 1699 1700 int i; 1701 1702 lcd_config(); 1703 1704 for (i = 0; i < __arraycount(pepper_mux_conf); i++) 1705 gxio_omap_mux_config(pepper_mux_conf[i]); 1706 gxio_omap_mux_config_address("com", 0x48022000, 1707 pepper_mux_uart1_conf, pepper_mux_no_uart1_conf); 1708 } 1709 1710 static void 1711 c_config(void) 1712 { 1713 static const struct omap_mux_conf pepper43c_mux_ft5306_conf[] = { 1714 /* FT5306 at I2C2 */ 1715 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20 */ 1716 { 0x95c, MMODE(7) | PUDEN }, /* GPIO 5 */ 1717 { -1 } 1718 }; 1719 static const struct omap_mux_conf pepper43c_mux_i2c2_conf[] = { 1720 { 0x950, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SDA */ 1721 { 0x954, MMODE(2) | PUTYPESEL | RXACTIVE }, /* I2C2_SCL */ 1722 { -1 } 1723 }; 1724 static const struct omap_mux_conf *pepper43c_mux_conf[] = { 1725 pepper43c_mux_ft5306_conf, 1726 pepper43c_mux_i2c2_conf, 1727 }; 1728 1729 static const struct omap_gpio_conf pepper43c_gpio_ft5306_conf[] = { 1730 { 5, conf_output_0 }, /* #Reset */ 1731 { -1 } 1732 }; 1733 int i; 1734 1735 pepper43_config(); 1736 1737 for (i = 0; i < __arraycount(pepper43c_mux_conf); i++) 1738 gxio_omap_mux_config(pepper43c_mux_conf[i]); 1739 gxio_omap_gpio_config(pepper43c_gpio_ft5306_conf); 1740 } 1741 1742 static void 1743 dvi_config(void) 1744 { 1745 /* XXXX: hmm... mismatch found in Linux's dts and pubs.gumstix.org... */ 1746 1747 extern struct cfdata cfdata[]; 1748 extern const struct tifb_panel_info *tifb_panel_info; 1749 1750 static const struct tifb_panel_info panel_dvi = { 1751 .panel_tft = 1, 1752 .panel_mono = false, 1753 .panel_bpp = 16, 1754 1755 .panel_pxl_clk = 63500000, 1756 .panel_width = 1024, 1757 .panel_height = 768, 1758 .panel_hfp = 8, 1759 .panel_hbp = 4, 1760 .panel_hsw = 41, 1761 .panel_vfp = 4, 1762 .panel_vbp = 2, 1763 .panel_vsw = 10, 1764 .panel_invert_hsync = 0, 1765 .panel_invert_vsync = 0, 1766 1767 .panel_ac_bias = 255, 1768 .panel_ac_bias_intrpt = 0, 1769 .panel_dma_burst_sz = 16, 1770 .panel_fdd = 0x80, 1771 .panel_sync_edge = 0, 1772 .panel_sync_ctrl = 1, 1773 .panel_invert_pxl_clk = 0, 1774 }; 1775 cfdata_t cf = &cfdata[0]; 1776 1777 /* Disable wireless module. */ 1778 while (cf->cf_name != NULL) { 1779 if (strcmp(cf->cf_name, "sdhc") == 0 && 1780 strcmp(cf->cf_atname, "mainbus") == 0 && 1781 cf->cf_loc[MAINBUSCF_BASE] == 0x47810000) { 1782 if (cf->cf_fstate == FSTATE_NOTFOUND) 1783 cf->cf_fstate = FSTATE_DNOTFOUND; 1784 else if (cf->cf_fstate == FSTATE_STAR) 1785 cf->cf_fstate = FSTATE_DSTAR; 1786 } 1787 cf++; 1788 } 1789 1790 tifb_panel_info = &panel_dvi; 1791 } 1792 1793 static void 1794 r_config(void) 1795 { 1796 static const struct omap_mux_conf pepper43r_mux_ads7846_conf[] = { 1797 /* ADS7846 at McSPI0 */ 1798 { 0x9b4, MMODE(7) | PUDEN | RXACTIVE }, /* GPIO 20: IRQ */ 1799 { -1 } 1800 }; 1801 static const struct omap_mux_conf pepper43r_mux_spi0_conf[] = { 1802 { 0x950, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_SCLK */ 1803 { 0x954, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D0 */ 1804 { 0x958, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_D1 */ 1805 { 0x95c, MMODE(0) | PUTYPESEL | RXACTIVE }, /* SPI0_CS0 */ 1806 { -1 } 1807 }; 1808 static const struct omap_mux_conf *pepper43r_mux_conf[] = { 1809 pepper43r_mux_ads7846_conf, 1810 pepper43r_mux_spi0_conf, 1811 }; 1812 int i; 1813 1814 pepper43_config(); 1815 1816 for (i = 0; i < __arraycount(pepper43r_mux_conf); i++) 1817 gxio_omap_mux_config(pepper43r_mux_conf[i]); 1818 } 1819 1820 #endif 1821 1822 #if defined(OVERO) || defined(DUOVERO) 1823 static void 1824 smsh_config(struct omap_mux_conf *smsh_mux_conf, int intr, int nreset) 1825 { 1826 struct omap_gpio_conf smsh_gpio_conf[] = { 1827 { intr, conf_input }, 1828 { nreset, conf_output_0 }, 1829 { -1 } 1830 }; 1831 1832 /* 1833 * Basically use current settings by U-Boot. 1834 * However remap physical address to configured address. 1835 */ 1836 1837 if (smsh_mux_conf != NULL) 1838 gxio_omap_mux_config(smsh_mux_conf); 1839 gxio_omap_gpio_config(smsh_gpio_conf); 1840 __udelay(100000); 1841 gxio_omap_gpio_write(nreset, 1); 1842 } 1843 #endif 1844 1845 #if defined(OVERO) || defined(DUOVERO) || defined(PEPPER) 1846 /* 1847 * The delay for configuration time. 1848 * This function use initialized timer by U-Boot. 1849 */ 1850 static void 1851 __udelay(unsigned int usec) 1852 { 1853 #if defined(OVERO) || defined(DUOVERO) 1854 #define V_SCLK (26000000 >> 1) 1855 #define TCRR 0x28 1856 #elif defined(PEPPER) 1857 #define V_SCLK 24000000 1858 #define TCRR 0x3c 1859 #endif 1860 #define SYS_PTV 2 1861 #define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV)) 1862 1863 const vaddr_t timer_base = 1864 #if defined(OVERO) 1865 OVERO_L4_PERIPHERAL_VBASE + 0x32000; 1866 #elif defined(DUOVERO) 1867 DUOVERO_L4_PERIPHERAL_VBASE + 0x32000; 1868 #elif defined(PEPPER) 1869 PEPPER_L4_PERIPHERAL_VBASE + 0x40000; 1870 #endif 1871 long timo = usec * (TIMER_CLOCK / 1000) / 1000; 1872 uint32_t now, last; 1873 1874 last = ioreg_read(timer_base + TCRR); 1875 while (timo > 0) { 1876 now = ioreg_read(timer_base + TCRR); 1877 if (last > now) 1878 timo -= __BITS(0, 31) - last + now + 1; 1879 else 1880 timo -= now - last; 1881 last = now; 1882 } 1883 } 1884 #endif 1885 1886 #if defined(PEPPER) 1887 static int 1888 read_i2c_device(const vaddr_t i2c_base, uint16_t sa, uint8_t addr, int len, 1889 uint8_t *buf) 1890 { 1891 uint16_t v; 1892 int aok = 0, cnt = 0; 1893 1894 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1895 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1896 while (v & I2C_IRQSTATUS_BB) { 1897 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, v); 1898 __udelay(20); 1899 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1900 } 1901 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1902 1903 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1904 ioreg16_write(i2c_base + OMAP2_I2C_CNT, sizeof(addr)); 1905 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1906 I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STP | I2C_CON_STT); 1907 while (1 /*CONSTCOND*/) { 1908 __udelay(20); 1909 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1910 if ((v & I2C_IRQSTATUS_XRDY) && aok == 0) { 1911 aok = 1; 1912 ioreg16_write(i2c_base + OMAP2_I2C_DATA, addr); 1913 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1914 I2C_IRQSTATUS_XRDY); 1915 } 1916 if (v & I2C_IRQSTATUS_ARDY) { 1917 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1918 I2C_IRQSTATUS_ARDY); 1919 break; 1920 } 1921 } 1922 1923 ioreg16_write(i2c_base + OMAP2_I2C_SA, sa); 1924 ioreg16_write(i2c_base + OMAP2_I2C_CNT, len); 1925 ioreg16_write(i2c_base + OMAP2_I2C_CON, 1926 I2C_CON_EN | I2C_CON_MST | I2C_CON_STP | I2C_CON_STT); 1927 while (1 /*CONSTCOND*/) { 1928 v = ioreg16_read(i2c_base + OMAP2_I2C_IRQSTATUS_RAW); 1929 if (v & I2C_IRQSTATUS_RRDY && 1930 cnt < len) { 1931 buf[cnt++] = ioreg16_read(i2c_base + OMAP2_I2C_DATA); 1932 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1933 I2C_IRQSTATUS_RRDY); 1934 } 1935 if (v & I2C_IRQSTATUS_ARDY) { 1936 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 1937 I2C_IRQSTATUS_ARDY); 1938 break; 1939 } 1940 } 1941 ioreg16_write(i2c_base + OMAP2_I2C_IRQSTATUS, 0xffff); 1942 return 0; 1943 } 1944 #endif 1945
Indexes created Tue Sep 30 11:09:46 GMT 2025