hdlgreg.h revision 1.1.2.2
1 1.1.2.2 elad /* $NetBSD: hdlgreg.h,v 1.1.2.2 2006/04/19 02:32:22 elad Exp $ */ 2 1.1.2.2 elad 3 1.1.2.2 elad /* 4 1.1.2.2 elad * Copyright (c) 2005, 2006 Kimihiro Nonaka 5 1.1.2.2 elad * All rights reserved. 6 1.1.2.2 elad * 7 1.1.2.2 elad * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 elad * modification, are permitted provided that the following conditions 9 1.1.2.2 elad * are met: 10 1.1.2.2 elad * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 elad * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 elad * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 elad * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 elad * documentation and/or other materials provided with the distribution. 15 1.1.2.2 elad * 16 1.1.2.2 elad * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 1.1.2.2 elad * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.1.2.2 elad * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.1.2.2 elad * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 1.1.2.2 elad * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.1.2.2 elad * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.1.2.2 elad * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.1.2.2 elad * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.1.2.2 elad * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 elad * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 elad * SUCH DAMAGE. 27 1.1.2.2 elad */ 28 1.1.2.2 elad 29 1.1.2.2 elad #ifndef _HDLGREG_H_ 30 1.1.2.2 elad #define _HDLGREG_H_ 31 1.1.2.2 elad 32 1.1.2.2 elad /* 33 1.1.2.2 elad * Memory map and register definitions for I-O DATA HDL-G 34 1.1.2.2 elad */ 35 1.1.2.2 elad 36 1.1.2.2 elad /* 37 1.1.2.2 elad * The memory map of I/O-DATA HDL-G looks like so: 38 1.1.2.2 elad * 39 1.1.2.2 elad * ------------------------------ 40 1.1.2.2 elad * Intel 80321 IOP Reserved 41 1.1.2.2 elad * FFFF E900 ------------------------------ 42 1.1.2.2 elad * Peripheral Memory Mapped 43 1.1.2.2 elad * Registers 44 1.1.2.2 elad * FFFF E000 ------------------------------ 45 1.1.2.2 elad * On-board devices 46 1.1.2.2 elad * FE80 0000 ------------------------------ 47 1.1.2.2 elad * SDRAM 48 1.1.2.2 elad * A000 0000 ------------------------------ 49 1.1.2.2 elad * Reserved 50 1.1.2.2 elad * 9100 0000 ------------------------------ 51 1.1.2.2 elad * Flash 52 1.1.2.2 elad * 9080 0000 ------------------------------ 53 1.1.2.2 elad * Reserved 54 1.1.2.2 elad * 9002 0000 ------------------------------ 55 1.1.2.2 elad * ATU Outbound Transaction 56 1.1.2.2 elad * Windows 57 1.1.2.2 elad * 8000 0000 ------------------------------ 58 1.1.2.2 elad * ATU Outbound Direct 59 1.1.2.2 elad * Addressing Windows 60 1.1.2.2 elad * 0000 1000 ------------------------------ 61 1.1.2.2 elad * Initialization Boot Code 62 1.1.2.2 elad * from Flash 63 1.1.2.2 elad * 0000 0000 ------------------------------ 64 1.1.2.2 elad */ 65 1.1.2.2 elad 66 1.1.2.2 elad /* 67 1.1.2.2 elad * We allocate a page table for VA 0xfe400000 (4MB) and map the 68 1.1.2.2 elad * PCI I/O space (64K) and i80321 memory-mapped registers (4K) there. 69 1.1.2.2 elad */ 70 1.1.2.2 elad #define HDLG_IOPXS_VBASE 0xfe400000UL 71 1.1.2.2 elad #define HDLG_IOW_VBASE HDLG_IOPXS_VBASE 72 1.1.2.2 elad #define HDLG_80321_VBASE (HDLG_IOW_VBASE + \ 73 1.1.2.2 elad VERDE_OUT_XLATE_IO_WIN_SIZE) 74 1.1.2.2 elad 75 1.1.2.2 elad /* 76 1.1.2.2 elad * The GIGALANDISK on-board devices are mapped VA==PA during bootstrap. 77 1.1.2.2 elad * Conveniently, the size of the on-board register space is 1 section 78 1.1.2.2 elad * mapping. 79 1.1.2.2 elad */ 80 1.1.2.2 elad #define HDLG_OBIO_BASE 0xfe800000UL 81 1.1.2.2 elad #define HDLG_OBIO_SIZE 0x00100000UL /* 1MB */ 82 1.1.2.2 elad 83 1.1.2.2 elad #define HDLG_UART1 0xfe800000UL /* TI 16550 */ 84 1.1.2.2 elad #define HDLG_PLD 0xfe8d0000UL /* CPLD */ 85 1.1.2.2 elad 86 1.1.2.2 elad /* 87 1.1.2.2 elad * CPLD 88 1.1.2.2 elad */ 89 1.1.2.2 elad #define HDLG_LEDCTRL (HDLG_PLD + 0x00) 90 1.1.2.2 elad #define LEDCTRL_STAT_GREEN 0x01 91 1.1.2.2 elad #define LEDCTRL_STAT_RED 0x02 92 1.1.2.2 elad #define LEDCTRL_USB1 0x04 93 1.1.2.2 elad #define LEDCTRL_USB2 0x08 94 1.1.2.2 elad #define LEDCTRL_USB3 0x10 95 1.1.2.2 elad #define LEDCTRL_USB4 0x20 96 1.1.2.2 elad #define LEDCTRL_HDD 0x40 97 1.1.2.2 elad #define LEDCTRL_BUZZER 0x80 98 1.1.2.2 elad #define HDLG_PWRLEDCTRL (HDLG_PLD + 0x01) 99 1.1.2.2 elad #define PWRLEDCTRL_0 0x01 100 1.1.2.2 elad #define PWRLEDCTRL_1 0x02 101 1.1.2.2 elad #define PWRLEDCTRL_2 0x04 102 1.1.2.2 elad #define PWRLEDCTRL_3 0x08 103 1.1.2.2 elad #define HDLG_BTNSTAT (HDLG_PLD + 0x02) 104 1.1.2.2 elad #define BTNSTAT_POWER 0x01 105 1.1.2.2 elad #define BTNSTAT_SELECT 0x02 106 1.1.2.2 elad #define BTNSTAT_COPY 0x04 107 1.1.2.2 elad #define BTNSTAT_REMOVE 0x08 108 1.1.2.2 elad #define BTNSTAT_RESET 0x10 109 1.1.2.2 elad #define HDLG_INTEN (HDLG_PLD + 0x03) 110 1.1.2.2 elad #define INTEN_PWRSW 0x01 111 1.1.2.2 elad #define INTEN_BUTTON 0x02 112 1.1.2.2 elad #define HDLG_PWRMNG (HDLG_PLD + 0x04) 113 1.1.2.2 elad #define PWRMNG_POWOFF 0x01 114 1.1.2.2 elad #define PWRMNG_RESET 0x02 115 1.1.2.2 elad 116 1.1.2.2 elad #define hdlg_enable_pldintr(bit) \ 117 1.1.2.2 elad do { \ 118 1.1.2.2 elad *(volatile uint8_t *)HDLG_INTEN |= (bit); \ 119 1.1.2.2 elad } while (/*CONSTCOND*/0) 120 1.1.2.2 elad 121 1.1.2.2 elad #define hdlg_disable_pldintr(bit) \ 122 1.1.2.2 elad do { \ 123 1.1.2.2 elad *(volatile uint8_t *)HDLG_INTEN &= ~(bit); \ 124 1.1.2.2 elad } while (/*CONSTCOND*/0) 125 1.1.2.2 elad 126 1.1.2.2 elad #endif /* _HDLGREG_H_ */ 127
Indexes created Mon Sep 29 13:09:55 GMT 2025