hdlgreg.h revision 1.2.10.2
1 1.2.10.2 rpaulo /* $NetBSD: hdlgreg.h,v 1.2.10.2 2006/09/09 02:38:46 rpaulo Exp $ */ 2 1.2.10.2 rpaulo 3 1.2.10.2 rpaulo /* 4 1.2.10.2 rpaulo * Copyright (c) 2005, 2006 Kimihiro Nonaka 5 1.2.10.2 rpaulo * All rights reserved. 6 1.2.10.2 rpaulo * 7 1.2.10.2 rpaulo * Redistribution and use in source and binary forms, with or without 8 1.2.10.2 rpaulo * modification, are permitted provided that the following conditions 9 1.2.10.2 rpaulo * are met: 10 1.2.10.2 rpaulo * 1. Redistributions of source code must retain the above copyright 11 1.2.10.2 rpaulo * notice, this list of conditions and the following disclaimer. 12 1.2.10.2 rpaulo * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.10.2 rpaulo * notice, this list of conditions and the following disclaimer in the 14 1.2.10.2 rpaulo * documentation and/or other materials provided with the distribution. 15 1.2.10.2 rpaulo * 16 1.2.10.2 rpaulo * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 1.2.10.2 rpaulo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.2.10.2 rpaulo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.2.10.2 rpaulo * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 1.2.10.2 rpaulo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.2.10.2 rpaulo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.2.10.2 rpaulo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.2.10.2 rpaulo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.2.10.2 rpaulo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.2.10.2 rpaulo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.2.10.2 rpaulo * SUCH DAMAGE. 27 1.2.10.2 rpaulo */ 28 1.2.10.2 rpaulo 29 1.2.10.2 rpaulo #ifndef _HDLGREG_H_ 30 1.2.10.2 rpaulo #define _HDLGREG_H_ 31 1.2.10.2 rpaulo 32 1.2.10.2 rpaulo /* 33 1.2.10.2 rpaulo * Memory map and register definitions for I-O DATA HDL-G 34 1.2.10.2 rpaulo */ 35 1.2.10.2 rpaulo 36 1.2.10.2 rpaulo /* 37 1.2.10.2 rpaulo * The memory map of I/O-DATA HDL-G looks like so: 38 1.2.10.2 rpaulo * 39 1.2.10.2 rpaulo * ------------------------------ 40 1.2.10.2 rpaulo * Intel 80321 IOP Reserved 41 1.2.10.2 rpaulo * FFFF E900 ------------------------------ 42 1.2.10.2 rpaulo * Peripheral Memory Mapped 43 1.2.10.2 rpaulo * Registers 44 1.2.10.2 rpaulo * FFFF E000 ------------------------------ 45 1.2.10.2 rpaulo * On-board devices 46 1.2.10.2 rpaulo * FE80 0000 ------------------------------ 47 1.2.10.2 rpaulo * SDRAM 48 1.2.10.2 rpaulo * A000 0000 ------------------------------ 49 1.2.10.2 rpaulo * Reserved 50 1.2.10.2 rpaulo * 9100 0000 ------------------------------ 51 1.2.10.2 rpaulo * Flash 52 1.2.10.2 rpaulo * 9080 0000 ------------------------------ 53 1.2.10.2 rpaulo * Reserved 54 1.2.10.2 rpaulo * 9002 0000 ------------------------------ 55 1.2.10.2 rpaulo * ATU Outbound Transaction 56 1.2.10.2 rpaulo * Windows 57 1.2.10.2 rpaulo * 8000 0000 ------------------------------ 58 1.2.10.2 rpaulo * ATU Outbound Direct 59 1.2.10.2 rpaulo * Addressing Windows 60 1.2.10.2 rpaulo * 0000 1000 ------------------------------ 61 1.2.10.2 rpaulo * Initialization Boot Code 62 1.2.10.2 rpaulo * from Flash 63 1.2.10.2 rpaulo * 0000 0000 ------------------------------ 64 1.2.10.2 rpaulo */ 65 1.2.10.2 rpaulo 66 1.2.10.2 rpaulo /* 67 1.2.10.2 rpaulo * We allocate a page table for VA 0xfe400000 (4MB) and map the 68 1.2.10.2 rpaulo * PCI I/O space (64K) and i80321 memory-mapped registers (4K) there. 69 1.2.10.2 rpaulo */ 70 1.2.10.2 rpaulo #define HDLG_IOPXS_VBASE 0xfe400000UL 71 1.2.10.2 rpaulo #define HDLG_IOW_VBASE HDLG_IOPXS_VBASE 72 1.2.10.2 rpaulo #define HDLG_80321_VBASE (HDLG_IOW_VBASE + \ 73 1.2.10.2 rpaulo VERDE_OUT_XLATE_IO_WIN_SIZE) 74 1.2.10.2 rpaulo 75 1.2.10.2 rpaulo /* 76 1.2.10.2 rpaulo * The GIGALANDISK on-board devices are mapped VA==PA during bootstrap. 77 1.2.10.2 rpaulo * Conveniently, the size of the on-board register space is 1 section 78 1.2.10.2 rpaulo * mapping. 79 1.2.10.2 rpaulo */ 80 1.2.10.2 rpaulo #define HDLG_OBIO_BASE 0xfe800000UL 81 1.2.10.2 rpaulo #define HDLG_OBIO_SIZE 0x00100000UL /* 1MB */ 82 1.2.10.2 rpaulo 83 1.2.10.2 rpaulo #define HDLG_UART1 0xfe800000UL /* TI 16550 */ 84 1.2.10.2 rpaulo #define HDLG_PLD 0xfe8d0000UL /* CPLD */ 85 1.2.10.2 rpaulo 86 1.2.10.2 rpaulo /* 87 1.2.10.2 rpaulo * CPLD 88 1.2.10.2 rpaulo */ 89 1.2.10.2 rpaulo #define HDLG_LEDCTRL (HDLG_PLD + 0x00) 90 1.2.10.2 rpaulo #define LEDCTRL_STAT_GREEN 0x01 91 1.2.10.2 rpaulo #define LEDCTRL_STAT_RED 0x02 92 1.2.10.2 rpaulo #define LEDCTRL_USB1 0x04 93 1.2.10.2 rpaulo #define LEDCTRL_USB2 0x08 94 1.2.10.2 rpaulo #define LEDCTRL_USB3 0x10 95 1.2.10.2 rpaulo #define LEDCTRL_USB4 0x20 96 1.2.10.2 rpaulo #define LEDCTRL_HDD 0x40 97 1.2.10.2 rpaulo #define LEDCTRL_BUZZER 0x80 98 1.2.10.2 rpaulo #define HDLG_PWRLEDCTRL (HDLG_PLD + 0x01) 99 1.2.10.2 rpaulo #define PWRLEDCTRL_0 0x01 100 1.2.10.2 rpaulo #define PWRLEDCTRL_1 0x02 101 1.2.10.2 rpaulo #define PWRLEDCTRL_2 0x04 102 1.2.10.2 rpaulo #define PWRLEDCTRL_3 0x08 103 1.2.10.2 rpaulo #define HDLG_BTNSTAT (HDLG_PLD + 0x02) 104 1.2.10.2 rpaulo #define BTNSTAT_POWER 0x01 105 1.2.10.2 rpaulo #define BTNSTAT_SELECT 0x02 106 1.2.10.2 rpaulo #define BTNSTAT_COPY 0x04 107 1.2.10.2 rpaulo #define BTNSTAT_REMOVE 0x08 108 1.2.10.2 rpaulo #define BTNSTAT_RESET 0x10 109 1.2.10.2 rpaulo #define HDLG_INTEN (HDLG_PLD + 0x03) 110 1.2.10.2 rpaulo #define INTEN_PWRSW 0x01 111 1.2.10.2 rpaulo #define INTEN_BUTTON 0x02 112 1.2.10.2 rpaulo #define INTEN_RTC 0x40 113 1.2.10.2 rpaulo #define HDLG_PWRMNG (HDLG_PLD + 0x04) 114 1.2.10.2 rpaulo #define PWRMNG_POWOFF 0x01 115 1.2.10.2 rpaulo #define PWRMNG_RESET 0x02 116 1.2.10.2 rpaulo #define HDLG_FANCTRL (HDLG_PLD + 0x06) 117 1.2.10.2 rpaulo #define FANCTRL_OFF 0x00 118 1.2.10.2 rpaulo #define FANCTRL_ON 0x01 119 1.2.10.2 rpaulo 120 1.2.10.2 rpaulo #define hdlg_enable_pldintr(bit) \ 121 1.2.10.2 rpaulo do { \ 122 1.2.10.2 rpaulo *(volatile uint8_t *)HDLG_INTEN |= (bit); \ 123 1.2.10.2 rpaulo } while (/*CONSTCOND*/0) 124 1.2.10.2 rpaulo 125 1.2.10.2 rpaulo #define hdlg_disable_pldintr(bit) \ 126 1.2.10.2 rpaulo do { \ 127 1.2.10.2 rpaulo *(volatile uint8_t *)HDLG_INTEN &= ~(bit); \ 128 1.2.10.2 rpaulo } while (/*CONSTCOND*/0) 129 1.2.10.2 rpaulo 130 1.2.10.2 rpaulo #endif /* _HDLGREG_H_ */ 131
Indexes created Mon Sep 29 21:09:56 GMT 2025