ifpga.c revision 1.1
1 /* $NetBSD: ifpga.c,v 1.1 2001/10/27 16:19:08 rearnsha Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * Integrator FPGA core logic support. 34 * 35 * The integrator board supports the core logic in an FPGA which is loaded 36 * at POR with a custom design. This code supports the default logic as the 37 * board is shipped. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/device.h> 42 #include <sys/systm.h> 43 #include <sys/extent.h> 44 #include <sys/malloc.h> 45 #include <sys/null.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pciconf.h> 49 50 #include <machine/intr.h> 51 52 #include "opt_cputypes.h" 53 #include "opt_pci.h" 54 #include "pci.h" 55 56 #include <evbarm/ifpga/ifpgamem.h> 57 #include <evbarm/ifpga/ifpgavar.h> 58 #include <evbarm/ifpga/ifpgareg.h> 59 #include <evbarm/ifpga/ifpga_pcivar.h> 60 #include <evbarm/dev/v360reg.h> 61 62 /* Prototypes */ 63 static int ifpga_match (struct device *, struct cfdata *, void *); 64 static void ifpga_attach (struct device *, struct device *, void *); 65 static int ifpga_print (void *, const char *); 66 static int ifpga_pci_print (void *, const char *); 67 68 /* Drive and attach structures */ 69 struct cfattach ifpga_ca = { 70 sizeof(struct ifpga_softc), ifpga_match, ifpga_attach 71 }; 72 73 int ifpga_found; 74 75 /* Default UART clock speed (we should make this a boot option). */ 76 int ifpga_uart_clk = IFPGA_UART_CLK; 77 78 /* Virtual base of IRQ controller. */ 79 void *ifpga_irq_vbase; 80 81 #if NPCI > 0 82 /* PCI handles */ 83 extern struct arm32_pci_chipset ifpga_pci_chipset; 84 extern struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag; 85 86 static struct bus_space ifpga_pci_io_tag; 87 static struct bus_space ifpga_pci_mem_tag; 88 #endif /* NPCI > 0 */ 89 90 struct ifpga_softc *clock_sc; 91 92 static struct bus_space ifpga_bs_tag; 93 94 static struct ifpga_softc *ifpga_sc; 95 /* 96 * Print the configuration information for children 97 */ 98 99 static int 100 ifpga_print(void *aux, const char *pnp) 101 { 102 struct ifpga_attach_args *ifa = aux; 103 104 if (ifa->ifa_addr != -1) 105 printf(" addr 0x%lx", (unsigned long)ifa->ifa_addr); 106 if (ifa->ifa_irq != -1) 107 printf(" irq %d", ifa->ifa_irq); 108 109 return UNCONF; 110 } 111 112 #if NPCI > 0 113 static int 114 ifpga_pci_print(void *aux, const char *pnp) 115 { 116 struct pcibus_attach_args *pci_pba = (struct pcibus_attach_args *)aux; 117 118 if (pnp) 119 printf("%s at %s", pci_pba->pba_busname, pnp); 120 if (strcmp(pci_pba->pba_busname, "pci") == 0) 121 printf(" bus %d", pci_pba->pba_bus); 122 123 return UNCONF; 124 } 125 #endif 126 127 static int 128 ifpga_search(struct device *parent, struct cfdata *cf, void *aux) 129 { 130 struct ifpga_softc *sc = (struct ifpga_softc *)parent; 131 struct ifpga_attach_args ifa; 132 int tryagain; 133 134 do { 135 ifa.ifa_name = "ifpga_periph"; 136 ifa.ifa_iot = sc->sc_iot; 137 ifa.ifa_addr = cf->cf_iobase; 138 ifa.ifa_irq = cf->cf_irq; 139 ifa.ifa_sc_ioh = sc->sc_sc_ioh; 140 141 tryagain = 0; 142 if ((*cf->cf_attach->ca_match)(parent, cf, &ifa) > 0) { 143 config_attach(parent, cf, &ifa, ifpga_print); 144 tryagain = (cf->cf_fstate == FSTATE_STAR); 145 } 146 } while (tryagain); 147 148 return 0; 149 } 150 151 static int 152 ifpga_match(struct device *parent, struct cfdata *cf, void *aux) 153 { 154 #if 0 155 struct mainbus_attach_args *ma = aux; 156 157 /* Make sure that we're looking for the IFPGA. */ 158 if (strcmp(ma->ma_name, ifpga_md.md_name)) 159 return 0; 160 #endif 161 162 /* We can only have one instance of the IFPGA. */ 163 if (ifpga_found) 164 return 0; 165 166 return 1; 167 } 168 169 static void 170 ifpga_attach(struct device *parent, struct device *self, void *aux) 171 { 172 struct ifpga_softc *sc = (struct ifpga_softc *)self; 173 u_int id, sysclk; 174 #if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0 175 struct extent *ioext, *memext, *pmemext; 176 struct ifpga_pci_softc *pci_sc; 177 struct pcibus_attach_args pci_pba; 178 #endif 179 180 ifpga_found = 1; 181 182 /* We want a memory-mapped bus space, since the I/O space is sparse. */ 183 ifpga_create_mem_bs_tag(&ifpga_bs_tag, (void *)IFPGA_IO_BASE); 184 185 #if NPCI > 0 186 /* But the PCI config space is quite large, so we have a linear region 187 for that pre-allocated. */ 188 189 ifpga_create_io_bs_tag(&ifpga_pci_io_tag, (void *)IFPGA_PCI_IO_VBASE); 190 ifpga_create_mem_bs_tag(&ifpga_pci_mem_tag, (void *)0); 191 #endif 192 193 sc->sc_iot = &ifpga_bs_tag; 194 195 ifpga_sc = sc; 196 197 /* Now map in the IFPGA motherboard registers. */ 198 if (bus_space_map(sc->sc_iot, IFPGA_IO_SC_BASE, IFPGA_IO_SC_SIZE, 0, 199 &sc->sc_sc_ioh)) 200 panic("%s: Cannot map system controller registers", 201 self->dv_xname); 202 203 id = bus_space_read_4(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_ID); 204 205 printf(": Build %d, ", (id & IFPGA_SC_ID_BUILD_MASK) >> 206 IFPGA_SC_ID_BUILD_SHIFT); 207 switch (id & IFPGA_SC_ID_REV_MASK) 208 { 209 case IFPGA_SC_ID_REV_A: 210 printf("Rev A, "); 211 break; 212 case IFPGA_SC_ID_REV_B: 213 printf("Rev B, "); 214 break; 215 } 216 217 printf("Manufacturer "); 218 switch (id & IFPGA_SC_ID_MAN_MASK) 219 { 220 case IFPGA_SC_ID_MAN_ARM: 221 printf("ARM Ltd,"); 222 break; 223 default: 224 printf("Unknown,"); 225 break; 226 } 227 228 switch (id & IFPGA_SC_ID_ARCH_MASK) 229 { 230 case IFPGA_SC_ID_ARCH_ASBLE: 231 printf(" ASB, Little-endian,"); 232 break; 233 case IFPGA_SC_ID_ARCH_AHBLE: 234 printf(" AHB, Little-endian,"); 235 break; 236 default: 237 panic(" Unsupported bus"); 238 } 239 240 printf("\n%s: FPGA ", self->dv_xname); 241 242 switch (id & IFPGA_SC_ID_FPGA_MASK) 243 { 244 case IFPGA_SC_ID_FPGA_XC4062: 245 printf("XC4062"); 246 break; 247 case IFPGA_SC_ID_FPGA_XC4085: 248 printf("XC4085"); 249 break; 250 default: 251 printf("unknown"); 252 break; 253 } 254 255 sysclk = bus_space_read_1(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_OSC); 256 sysclk &= IFPGA_SC_OSC_S_VDW; 257 sysclk += 8; 258 259 printf(", SYSCLK %d.%02dMHz", sysclk >> 2, (sysclk & 3) * 25); 260 261 /* Map the Interrupt controller */ 262 if (bus_space_map(sc->sc_iot, IFPGA_IO_IRQ_BASE, IFPGA_IO_IRQ_SIZE, 263 BUS_SPACE_MAP_LINEAR, &sc->sc_irq_ioh)) 264 panic("%s: Cannot map irq controller registers", 265 self->dv_xname); 266 ifpga_irq_vbase = bus_space_vaddr(sc->sc_iot, sc->sc_irq_ioh); 267 268 /* We can write to the IRQ/FIQ controller now. */ 269 irq_postinit(); 270 271 /* Map the core module */ 272 if (bus_space_map(sc->sc_iot, IFPGA_IO_CM_BASE, IFPGA_IO_CM_SIZE, 0, 273 &sc->sc_cm_ioh)) 274 panic("%s: Cannot map core module registers", self->dv_xname); 275 276 /* Map the timers */ 277 if (bus_space_map(sc->sc_iot, IFPGA_IO_TMR_BASE, IFPGA_IO_TMR_SIZE, 0, 278 &sc->sc_tmr_ioh)) 279 panic("%s: Cannot map timer registers", self->dv_xname); 280 281 clock_sc = sc; 282 283 printf("\n"); 284 285 #if NPCI > 0 286 pci_sc = malloc(sizeof(struct ifpga_pci_softc), M_DEVBUF, M_WAITOK); 287 pci_sc->sc_iot = &ifpga_pci_io_tag; 288 pci_sc->sc_memt = &ifpga_pci_mem_tag; 289 290 if (bus_space_map(pci_sc->sc_iot, 0, IFPGA_PCI_IO_VSIZE, 0, 291 &pci_sc->sc_io_ioh) 292 || bus_space_map(pci_sc->sc_iot, 293 IFPGA_PCI_CONF_VBASE - IFPGA_PCI_IO_VBASE, IFPGA_PCI_CONF_VSIZE, 0, 294 &pci_sc->sc_conf_ioh) 295 || bus_space_map(pci_sc->sc_memt, IFPGA_V360_REG_BASE, 296 IFPGA_V360_REG_SIZE, 0, &pci_sc->sc_reg_ioh)) 297 panic("%s: Cannot map pci memory", self->dv_xname); 298 299 { 300 pcireg_t id_reg, class_reg; 301 char buf[1000]; 302 303 id_reg = bus_space_read_4(pci_sc->sc_memt, pci_sc->sc_reg_ioh, 304 V360_PCI_VENDOR); 305 class_reg = bus_space_read_4(pci_sc->sc_memt, 306 pci_sc->sc_reg_ioh, V360_PCI_CC_REV); 307 308 pci_devinfo(id_reg, class_reg, 1, buf); 309 printf("%s: %s\n", self->dv_xname, buf); 310 } 311 312 #if defined(PCI_NETBSD_CONFIGURE) 313 ioext = extent_create("pciio", 0x00000000, 314 0x00000000 + IFPGA_PCI_IO_VSIZE, M_DEVBUF, NULL, 0, EX_NOWAIT); 315 memext = extent_create("pcimem", IFPGA_PCI_APP0_BASE, 316 IFPGA_PCI_APP0_BASE + IFPGA_PCI_APP0_SIZE, 317 M_DEVBUF, NULL, 0, EX_NOWAIT); 318 pmemext = extent_create("pcipmem", IFPGA_PCI_APP1_BASE, 319 IFPGA_PCI_APP1_BASE + IFPGA_PCI_APP1_SIZE, 320 M_DEVBUF, NULL, 0, EX_NOWAIT); 321 ifpga_pci_chipset.pc_conf_v = (void *)pci_sc; 322 pci_configure_bus(&ifpga_pci_chipset, ioext, memext, pmemext); 323 extent_destroy(pmemext); 324 extent_destroy(memext); 325 extent_destroy(ioext); 326 327 printf("pci_configure_bus done\n"); 328 #endif /* PCI_NETBSD_CONFIGURE */ 329 #endif /* NPCI > 0 */ 330 331 /* Finally, search for children. */ 332 config_search(ifpga_search, self, NULL); 333 334 #if NPCI > 0 335 pci_pba.pba_busname = "pci"; 336 pci_pba.pba_pc = &ifpga_pci_chipset; 337 pci_pba.pba_iot = &ifpga_pci_io_tag; 338 pci_pba.pba_memt = &ifpga_pci_mem_tag; 339 pci_pba.pba_dmat = &ifpga_pci_bus_dma_tag; 340 pci_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 341 pci_pba.pba_bus = 0; 342 343 config_found(self, &pci_pba, ifpga_pci_print); 344 #endif 345 } 346 347 void 348 ifpga_reset(void) 349 { 350 bus_space_write_1(ifpga_sc->sc_iot, ifpga_sc->sc_sc_ioh, 351 IFPGA_SC_CTRLS, IFPGA_SC_CTRL_SOFTRESET); 352 } 353
Indexes created Mon Sep 29 21:09:56 GMT 2025