ifpga.c revision 1.11
1 /* $NetBSD: ifpga.c,v 1.11 2002/09/27 03:17:47 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * Integrator FPGA core logic support. 34 * 35 * The integrator board supports the core logic in an FPGA which is loaded 36 * at POR with a custom design. This code supports the default logic as the 37 * board is shipped. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/device.h> 42 #include <sys/systm.h> 43 #include <sys/extent.h> 44 #include <sys/malloc.h> 45 #include <sys/null.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pciconf.h> 49 50 #include <machine/intr.h> 51 #include <evbarm/ifpga/irqhandler.h> /* XXX XXX XXX */ 52 53 #include <arm/cpufunc.h> 54 55 #include "opt_pci.h" 56 #include "pci.h" 57 58 #include <evbarm/ifpga/ifpgamem.h> 59 #include <evbarm/ifpga/ifpgavar.h> 60 #include <evbarm/ifpga/ifpgareg.h> 61 #include <evbarm/ifpga/ifpga_pcivar.h> 62 #include <evbarm/dev/v360reg.h> 63 64 #include <evbarm/integrator/int_bus_dma.h> 65 66 /* Prototypes */ 67 static int ifpga_match (struct device *, struct cfdata *, void *); 68 static void ifpga_attach (struct device *, struct device *, void *); 69 static int ifpga_print (void *, const char *); 70 static int ifpga_pci_print (void *, const char *); 71 72 /* Drive and attach structures */ 73 struct cfattach ifpga_ca = { 74 sizeof(struct ifpga_softc), ifpga_match, ifpga_attach 75 }; 76 77 int ifpga_found; 78 79 /* Default UART clock speed (we should make this a boot option). */ 80 int ifpga_uart_clk = IFPGA_UART_CLK; 81 82 /* Virtual base of IRQ controller. */ 83 void *ifpga_irq_vbase; 84 85 #if NPCI > 0 86 /* PCI handles */ 87 extern struct arm32_pci_chipset ifpga_pci_chipset; 88 extern struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag; 89 90 static struct bus_space ifpga_pci_io_tag; 91 static struct bus_space ifpga_pci_mem_tag; 92 #endif /* NPCI > 0 */ 93 94 struct ifpga_softc *clock_sc; 95 96 static struct bus_space ifpga_bs_tag; 97 98 static struct ifpga_softc *ifpga_sc; 99 /* 100 * Print the configuration information for children 101 */ 102 103 static int 104 ifpga_print(void *aux, const char *pnp) 105 { 106 struct ifpga_attach_args *ifa = aux; 107 108 if (ifa->ifa_addr != -1) 109 printf(" addr 0x%lx", (unsigned long)ifa->ifa_addr); 110 if (ifa->ifa_irq != -1) 111 printf(" irq %d", ifa->ifa_irq); 112 113 return UNCONF; 114 } 115 116 #if NPCI > 0 117 static int 118 ifpga_pci_print(void *aux, const char *pnp) 119 { 120 struct pcibus_attach_args *pci_pba = (struct pcibus_attach_args *)aux; 121 122 if (pnp) 123 printf("%s at %s", pci_pba->pba_busname, pnp); 124 if (strcmp(pci_pba->pba_busname, "pci") == 0) 125 printf(" bus %d", pci_pba->pba_bus); 126 127 return UNCONF; 128 } 129 #endif 130 131 static int 132 ifpga_search(struct device *parent, struct cfdata *cf, void *aux) 133 { 134 struct ifpga_softc *sc = (struct ifpga_softc *)parent; 135 struct ifpga_attach_args ifa; 136 int tryagain; 137 138 do { 139 ifa.ifa_name = "ifpga_periph"; 140 ifa.ifa_iot = sc->sc_iot; 141 ifa.ifa_addr = cf->cf_iobase; 142 ifa.ifa_irq = cf->cf_irq; 143 ifa.ifa_sc_ioh = sc->sc_sc_ioh; 144 145 tryagain = 0; 146 if (config_match(parent, cf, &ifa) > 0) { 147 config_attach(parent, cf, &ifa, ifpga_print); 148 tryagain = (cf->cf_fstate == FSTATE_STAR); 149 } 150 } while (tryagain); 151 152 return 0; 153 } 154 155 static int 156 ifpga_match(struct device *parent, struct cfdata *cf, void *aux) 157 { 158 #if 0 159 struct mainbus_attach_args *ma = aux; 160 161 /* Make sure that we're looking for the IFPGA. */ 162 if (strcmp(ma->ma_name, ifpga_md.md_name)) 163 return 0; 164 #endif 165 166 /* We can only have one instance of the IFPGA. */ 167 if (ifpga_found) 168 return 0; 169 170 return 1; 171 } 172 173 static void 174 ifpga_attach(struct device *parent, struct device *self, void *aux) 175 { 176 struct ifpga_softc *sc = (struct ifpga_softc *)self; 177 u_int id, sysclk; 178 #if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0 179 struct extent *ioext, *memext, *pmemext; 180 struct ifpga_pci_softc *pci_sc; 181 struct pcibus_attach_args pci_pba; 182 #endif 183 184 ifpga_found = 1; 185 186 /* We want a memory-mapped bus space, since the I/O space is sparse. */ 187 ifpga_create_mem_bs_tag(&ifpga_bs_tag, (void *)IFPGA_IO_BASE); 188 189 #if NPCI > 0 190 /* But the PCI config space is quite large, so we have a linear region 191 for that pre-allocated. */ 192 193 ifpga_create_io_bs_tag(&ifpga_pci_io_tag, (void *)IFPGA_PCI_IO_VBASE); 194 ifpga_create_mem_bs_tag(&ifpga_pci_mem_tag, (void *)0); 195 #endif 196 197 sc->sc_iot = &ifpga_bs_tag; 198 199 ifpga_sc = sc; 200 201 /* Now map in the IFPGA motherboard registers. */ 202 if (bus_space_map(sc->sc_iot, IFPGA_IO_SC_BASE, IFPGA_IO_SC_SIZE, 0, 203 &sc->sc_sc_ioh)) 204 panic("%s: Cannot map system controller registers", 205 self->dv_xname); 206 207 id = bus_space_read_4(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_ID); 208 209 printf(": Build %d, ", (id & IFPGA_SC_ID_BUILD_MASK) >> 210 IFPGA_SC_ID_BUILD_SHIFT); 211 switch (id & IFPGA_SC_ID_REV_MASK) 212 { 213 case IFPGA_SC_ID_REV_A: 214 printf("Rev A, "); 215 break; 216 case IFPGA_SC_ID_REV_B: 217 printf("Rev B, "); 218 break; 219 } 220 221 printf("Manufacturer "); 222 switch (id & IFPGA_SC_ID_MAN_MASK) 223 { 224 case IFPGA_SC_ID_MAN_ARM: 225 printf("ARM Ltd,"); 226 break; 227 default: 228 printf("Unknown,"); 229 break; 230 } 231 232 switch (id & IFPGA_SC_ID_ARCH_MASK) 233 { 234 case IFPGA_SC_ID_ARCH_ASBLE: 235 printf(" ASB, Little-endian,"); 236 break; 237 case IFPGA_SC_ID_ARCH_AHBLE: 238 printf(" AHB, Little-endian,"); 239 break; 240 default: 241 panic(" Unsupported bus"); 242 } 243 244 printf("\n%s: FPGA ", self->dv_xname); 245 246 switch (id & IFPGA_SC_ID_FPGA_MASK) 247 { 248 case IFPGA_SC_ID_FPGA_XC4062: 249 printf("XC4062"); 250 break; 251 case IFPGA_SC_ID_FPGA_XC4085: 252 printf("XC4085"); 253 break; 254 default: 255 printf("unknown"); 256 break; 257 } 258 259 sysclk = bus_space_read_1(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_OSC); 260 sysclk &= IFPGA_SC_OSC_S_VDW; 261 sysclk += 8; 262 263 printf(", SYSCLK %d.%02dMHz", sysclk >> 2, (sysclk & 3) * 25); 264 265 /* Map the Interrupt controller */ 266 if (bus_space_map(sc->sc_iot, IFPGA_IO_IRQ_BASE, IFPGA_IO_IRQ_SIZE, 267 BUS_SPACE_MAP_LINEAR, &sc->sc_irq_ioh)) 268 panic("%s: Cannot map irq controller registers", 269 self->dv_xname); 270 ifpga_irq_vbase = bus_space_vaddr(sc->sc_iot, sc->sc_irq_ioh); 271 272 /* We can write to the IRQ/FIQ controller now. */ 273 irq_postinit(); 274 275 /* Map the core module */ 276 if (bus_space_map(sc->sc_iot, IFPGA_IO_CM_BASE, IFPGA_IO_CM_SIZE, 0, 277 &sc->sc_cm_ioh)) 278 panic("%s: Cannot map core module registers", self->dv_xname); 279 280 /* Map the timers */ 281 if (bus_space_map(sc->sc_iot, IFPGA_IO_TMR_BASE, IFPGA_IO_TMR_SIZE, 0, 282 &sc->sc_tmr_ioh)) 283 panic("%s: Cannot map timer registers", self->dv_xname); 284 285 clock_sc = sc; 286 287 printf("\n"); 288 289 #if NPCI > 0 290 pci_sc = malloc(sizeof(struct ifpga_pci_softc), M_DEVBUF, M_WAITOK); 291 pci_sc->sc_iot = &ifpga_pci_io_tag; 292 pci_sc->sc_memt = &ifpga_pci_mem_tag; 293 294 if (bus_space_map(pci_sc->sc_iot, 0, IFPGA_PCI_IO_VSIZE, 0, 295 &pci_sc->sc_io_ioh) 296 || bus_space_map(pci_sc->sc_iot, 297 IFPGA_PCI_CONF_VBASE - IFPGA_PCI_IO_VBASE, IFPGA_PCI_CONF_VSIZE, 0, 298 &pci_sc->sc_conf_ioh) 299 || bus_space_map(pci_sc->sc_memt, IFPGA_V360_REG_BASE, 300 IFPGA_V360_REG_SIZE, 0, &pci_sc->sc_reg_ioh)) 301 panic("%s: Cannot map pci memory", self->dv_xname); 302 303 { 304 pcireg_t id_reg, class_reg; 305 char buf[1000]; 306 307 id_reg = bus_space_read_4(pci_sc->sc_memt, pci_sc->sc_reg_ioh, 308 V360_PCI_VENDOR); 309 class_reg = bus_space_read_4(pci_sc->sc_memt, 310 pci_sc->sc_reg_ioh, V360_PCI_CC_REV); 311 312 pci_devinfo(id_reg, class_reg, 1, buf); 313 printf("%s: %s\n", self->dv_xname, buf); 314 } 315 316 #if defined(PCI_NETBSD_CONFIGURE) 317 ioext = extent_create("pciio", 0x00000000, 318 0x00000000 + IFPGA_PCI_IO_VSIZE, M_DEVBUF, NULL, 0, EX_NOWAIT); 319 memext = extent_create("pcimem", IFPGA_PCI_APP0_BASE, 320 IFPGA_PCI_APP0_BASE + IFPGA_PCI_APP0_SIZE, 321 M_DEVBUF, NULL, 0, EX_NOWAIT); 322 pmemext = extent_create("pcipmem", IFPGA_PCI_APP1_BASE, 323 IFPGA_PCI_APP1_BASE + IFPGA_PCI_APP1_SIZE, 324 M_DEVBUF, NULL, 0, EX_NOWAIT); 325 ifpga_pci_chipset.pc_conf_v = (void *)pci_sc; 326 pci_configure_bus(&ifpga_pci_chipset, ioext, memext, pmemext, 0, 327 arm_dcache_align); 328 extent_destroy(pmemext); 329 extent_destroy(memext); 330 extent_destroy(ioext); 331 332 printf("pci_configure_bus done\n"); 333 #endif /* PCI_NETBSD_CONFIGURE */ 334 #endif /* NPCI > 0 */ 335 336 /* Finally, search for children. */ 337 config_search(ifpga_search, self, NULL); 338 339 #if NPCI > 0 340 integrator_pci_dma_init(&ifpga_pci_bus_dma_tag); 341 342 pci_pba.pba_busname = "pci"; 343 pci_pba.pba_pc = &ifpga_pci_chipset; 344 pci_pba.pba_iot = &ifpga_pci_io_tag; 345 pci_pba.pba_memt = &ifpga_pci_mem_tag; 346 pci_pba.pba_dmat = &ifpga_pci_bus_dma_tag; 347 pci_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 348 pci_pba.pba_bus = 0; 349 pci_pba.pba_bridgetag = NULL; 350 351 config_found(self, &pci_pba, ifpga_pci_print); 352 #endif 353 } 354 355 void 356 ifpga_reset(void) 357 { 358 bus_space_write_1(ifpga_sc->sc_iot, ifpga_sc->sc_sc_ioh, 359 IFPGA_SC_CTRLS, IFPGA_SC_CTRL_SOFTRESET); 360 } 361
Indexes created Mon Sep 29 21:09:56 GMT 2025