ifpga.c revision 1.16
1 /* $NetBSD: ifpga.c,v 1.16 2003/07/15 00:24:58 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * Integrator FPGA core logic support. 34 * 35 * The integrator board supports the core logic in an FPGA which is loaded 36 * at POR with a custom design. This code supports the default logic as the 37 * board is shipped. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: ifpga.c,v 1.16 2003/07/15 00:24:58 lukem Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/device.h> 45 #include <sys/systm.h> 46 #include <sys/extent.h> 47 #include <sys/malloc.h> 48 #include <sys/null.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pciconf.h> 52 53 #include <machine/intr.h> 54 #include <evbarm/ifpga/irqhandler.h> /* XXX XXX XXX */ 55 56 #include <arm/cpufunc.h> 57 58 #include "opt_pci.h" 59 #include "pci.h" 60 61 #include <evbarm/ifpga/ifpgamem.h> 62 #include <evbarm/ifpga/ifpgavar.h> 63 #include <evbarm/ifpga/ifpgareg.h> 64 #include <evbarm/ifpga/ifpga_pcivar.h> 65 #include <evbarm/dev/v360reg.h> 66 67 #include <evbarm/integrator/int_bus_dma.h> 68 69 /* Prototypes */ 70 static int ifpga_match (struct device *, struct cfdata *, void *); 71 static void ifpga_attach (struct device *, struct device *, void *); 72 static int ifpga_print (void *, const char *); 73 static int ifpga_pci_print (void *, const char *); 74 75 /* Drive and attach structures */ 76 CFATTACH_DECL(ifpga, sizeof(struct ifpga_softc), 77 ifpga_match, ifpga_attach, NULL, NULL); 78 79 int ifpga_found; 80 81 /* Default UART clock speed (we should make this a boot option). */ 82 int ifpga_uart_clk = IFPGA_UART_CLK; 83 84 /* Virtual base of IRQ controller. */ 85 void *ifpga_irq_vbase; 86 87 #if NPCI > 0 88 /* PCI handles */ 89 extern struct arm32_pci_chipset ifpga_pci_chipset; 90 extern struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag; 91 92 static struct bus_space ifpga_pci_io_tag; 93 static struct bus_space ifpga_pci_mem_tag; 94 #endif /* NPCI > 0 */ 95 96 struct ifpga_softc *clock_sc; 97 98 static struct bus_space ifpga_bs_tag; 99 100 static struct ifpga_softc *ifpga_sc; 101 /* 102 * Print the configuration information for children 103 */ 104 105 static int 106 ifpga_print(void *aux, const char *pnp) 107 { 108 struct ifpga_attach_args *ifa = aux; 109 110 if (ifa->ifa_addr != -1) 111 aprint_normal(" addr 0x%lx", (unsigned long)ifa->ifa_addr); 112 if (ifa->ifa_irq != -1) 113 aprint_normal(" irq %d", ifa->ifa_irq); 114 115 return UNCONF; 116 } 117 118 #if NPCI > 0 119 static int 120 ifpga_pci_print(void *aux, const char *pnp) 121 { 122 struct pcibus_attach_args *pci_pba = (struct pcibus_attach_args *)aux; 123 124 if (pnp) 125 aprint_normal("%s at %s", pci_pba->pba_busname, pnp); 126 if (strcmp(pci_pba->pba_busname, "pci") == 0) 127 aprint_normal(" bus %d", pci_pba->pba_bus); 128 129 return UNCONF; 130 } 131 #endif 132 133 static int 134 ifpga_search(struct device *parent, struct cfdata *cf, void *aux) 135 { 136 struct ifpga_softc *sc = (struct ifpga_softc *)parent; 137 struct ifpga_attach_args ifa; 138 int tryagain; 139 140 do { 141 ifa.ifa_name = "ifpga_periph"; 142 ifa.ifa_iot = sc->sc_iot; 143 ifa.ifa_addr = cf->cf_iobase; 144 ifa.ifa_irq = cf->cf_irq; 145 ifa.ifa_sc_ioh = sc->sc_sc_ioh; 146 147 tryagain = 0; 148 if (config_match(parent, cf, &ifa) > 0) { 149 config_attach(parent, cf, &ifa, ifpga_print); 150 tryagain = (cf->cf_fstate == FSTATE_STAR); 151 } 152 } while (tryagain); 153 154 return 0; 155 } 156 157 static int 158 ifpga_match(struct device *parent, struct cfdata *cf, void *aux) 159 { 160 #if 0 161 struct mainbus_attach_args *ma = aux; 162 163 /* Make sure that we're looking for the IFPGA. */ 164 if (strcmp(ma->ma_name, ifpga_md.md_name)) 165 return 0; 166 #endif 167 168 /* We can only have one instance of the IFPGA. */ 169 if (ifpga_found) 170 return 0; 171 172 return 1; 173 } 174 175 static void 176 ifpga_attach(struct device *parent, struct device *self, void *aux) 177 { 178 struct ifpga_softc *sc = (struct ifpga_softc *)self; 179 u_int id, sysclk; 180 #if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0 181 struct extent *ioext, *memext, *pmemext; 182 struct ifpga_pci_softc *pci_sc; 183 struct pcibus_attach_args pci_pba; 184 #endif 185 186 ifpga_found = 1; 187 188 /* We want a memory-mapped bus space, since the I/O space is sparse. */ 189 ifpga_create_mem_bs_tag(&ifpga_bs_tag, (void *)IFPGA_IO_BASE); 190 191 #if NPCI > 0 192 /* But the PCI config space is quite large, so we have a linear region 193 for that pre-allocated. */ 194 195 ifpga_create_io_bs_tag(&ifpga_pci_io_tag, (void *)IFPGA_PCI_IO_VBASE); 196 ifpga_create_mem_bs_tag(&ifpga_pci_mem_tag, (void *)0); 197 #endif 198 199 sc->sc_iot = &ifpga_bs_tag; 200 201 ifpga_sc = sc; 202 203 /* Now map in the IFPGA motherboard registers. */ 204 if (bus_space_map(sc->sc_iot, IFPGA_IO_SC_BASE, IFPGA_IO_SC_SIZE, 0, 205 &sc->sc_sc_ioh)) 206 panic("%s: Cannot map system controller registers", 207 self->dv_xname); 208 209 id = bus_space_read_4(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_ID); 210 211 printf(": Build %d, ", (id & IFPGA_SC_ID_BUILD_MASK) >> 212 IFPGA_SC_ID_BUILD_SHIFT); 213 switch (id & IFPGA_SC_ID_REV_MASK) 214 { 215 case IFPGA_SC_ID_REV_A: 216 printf("Rev A, "); 217 break; 218 case IFPGA_SC_ID_REV_B: 219 printf("Rev B, "); 220 break; 221 } 222 223 printf("Manufacturer "); 224 switch (id & IFPGA_SC_ID_MAN_MASK) 225 { 226 case IFPGA_SC_ID_MAN_ARM: 227 printf("ARM Ltd,"); 228 break; 229 default: 230 printf("Unknown,"); 231 break; 232 } 233 234 switch (id & IFPGA_SC_ID_ARCH_MASK) 235 { 236 case IFPGA_SC_ID_ARCH_ASBLE: 237 printf(" ASB, Little-endian,"); 238 break; 239 case IFPGA_SC_ID_ARCH_AHBLE: 240 printf(" AHB, Little-endian,"); 241 break; 242 default: 243 panic(" Unsupported bus"); 244 } 245 246 printf("\n%s: FPGA ", self->dv_xname); 247 248 switch (id & IFPGA_SC_ID_FPGA_MASK) 249 { 250 case IFPGA_SC_ID_FPGA_XC4062: 251 printf("XC4062"); 252 break; 253 case IFPGA_SC_ID_FPGA_XC4085: 254 printf("XC4085"); 255 break; 256 default: 257 printf("unknown"); 258 break; 259 } 260 261 sysclk = bus_space_read_1(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_OSC); 262 sysclk &= IFPGA_SC_OSC_S_VDW; 263 sysclk += 8; 264 265 printf(", SYSCLK %d.%02dMHz", sysclk >> 2, (sysclk & 3) * 25); 266 267 /* Map the Interrupt controller */ 268 if (bus_space_map(sc->sc_iot, IFPGA_IO_IRQ_BASE, IFPGA_IO_IRQ_SIZE, 269 BUS_SPACE_MAP_LINEAR, &sc->sc_irq_ioh)) 270 panic("%s: Cannot map irq controller registers", 271 self->dv_xname); 272 ifpga_irq_vbase = bus_space_vaddr(sc->sc_iot, sc->sc_irq_ioh); 273 274 /* We can write to the IRQ/FIQ controller now. */ 275 irq_postinit(); 276 277 /* Map the core module */ 278 if (bus_space_map(sc->sc_iot, IFPGA_IO_CM_BASE, IFPGA_IO_CM_SIZE, 0, 279 &sc->sc_cm_ioh)) 280 panic("%s: Cannot map core module registers", self->dv_xname); 281 282 /* Map the timers */ 283 if (bus_space_map(sc->sc_iot, IFPGA_IO_TMR_BASE, IFPGA_IO_TMR_SIZE, 0, 284 &sc->sc_tmr_ioh)) 285 panic("%s: Cannot map timer registers", self->dv_xname); 286 287 clock_sc = sc; 288 289 printf("\n"); 290 291 #if NPCI > 0 292 pci_sc = malloc(sizeof(struct ifpga_pci_softc), M_DEVBUF, M_WAITOK); 293 pci_sc->sc_iot = &ifpga_pci_io_tag; 294 pci_sc->sc_memt = &ifpga_pci_mem_tag; 295 296 if (bus_space_map(pci_sc->sc_iot, 0, IFPGA_PCI_IO_VSIZE, 0, 297 &pci_sc->sc_io_ioh) 298 || bus_space_map(pci_sc->sc_iot, 299 IFPGA_PCI_CONF_VBASE - IFPGA_PCI_IO_VBASE, IFPGA_PCI_CONF_VSIZE, 0, 300 &pci_sc->sc_conf_ioh) 301 || bus_space_map(pci_sc->sc_memt, IFPGA_V360_REG_BASE, 302 IFPGA_V360_REG_SIZE, 0, &pci_sc->sc_reg_ioh)) 303 panic("%s: Cannot map pci memory", self->dv_xname); 304 305 { 306 pcireg_t id_reg, class_reg; 307 char buf[1000]; 308 309 id_reg = bus_space_read_4(pci_sc->sc_memt, pci_sc->sc_reg_ioh, 310 V360_PCI_VENDOR); 311 class_reg = bus_space_read_4(pci_sc->sc_memt, 312 pci_sc->sc_reg_ioh, V360_PCI_CC_REV); 313 314 pci_devinfo(id_reg, class_reg, 1, buf); 315 printf("%s: %s\n", self->dv_xname, buf); 316 } 317 318 #if defined(PCI_NETBSD_CONFIGURE) 319 ioext = extent_create("pciio", 0x00000000, 320 0x00000000 + IFPGA_PCI_IO_VSIZE, M_DEVBUF, NULL, 0, EX_NOWAIT); 321 memext = extent_create("pcimem", IFPGA_PCI_APP0_BASE, 322 IFPGA_PCI_APP0_BASE + IFPGA_PCI_APP0_SIZE, 323 M_DEVBUF, NULL, 0, EX_NOWAIT); 324 pmemext = extent_create("pcipmem", IFPGA_PCI_APP1_BASE, 325 IFPGA_PCI_APP1_BASE + IFPGA_PCI_APP1_SIZE, 326 M_DEVBUF, NULL, 0, EX_NOWAIT); 327 ifpga_pci_chipset.pc_conf_v = (void *)pci_sc; 328 pci_configure_bus(&ifpga_pci_chipset, ioext, memext, pmemext, 0, 329 arm_dcache_align); 330 extent_destroy(pmemext); 331 extent_destroy(memext); 332 extent_destroy(ioext); 333 334 printf("pci_configure_bus done\n"); 335 #endif /* PCI_NETBSD_CONFIGURE */ 336 #endif /* NPCI > 0 */ 337 338 /* Finally, search for children. */ 339 config_search(ifpga_search, self, NULL); 340 341 #if NPCI > 0 342 integrator_pci_dma_init(&ifpga_pci_bus_dma_tag); 343 344 pci_pba.pba_busname = "pci"; 345 pci_pba.pba_pc = &ifpga_pci_chipset; 346 pci_pba.pba_iot = &ifpga_pci_io_tag; 347 pci_pba.pba_memt = &ifpga_pci_mem_tag; 348 pci_pba.pba_dmat = &ifpga_pci_bus_dma_tag; 349 pci_pba.pba_dmat64 = NULL; 350 pci_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 351 pci_pba.pba_bus = 0; 352 pci_pba.pba_bridgetag = NULL; 353 354 config_found(self, &pci_pba, ifpga_pci_print); 355 #endif 356 } 357 358 void 359 ifpga_reset(void) 360 { 361 bus_space_write_1(ifpga_sc->sc_iot, ifpga_sc->sc_sc_ioh, 362 IFPGA_SC_CTRLS, IFPGA_SC_CTRL_SOFTRESET); 363 } 364
Indexes created Tue Sep 30 06:09:59 GMT 2025