ifpga.c revision 1.18
1 /* $NetBSD: ifpga.c,v 1.18 2004/04/24 15:49:00 kleink Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * Integrator FPGA core logic support. 34 * 35 * The integrator board supports the core logic in an FPGA which is loaded 36 * at POR with a custom design. This code supports the default logic as the 37 * board is shipped. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: ifpga.c,v 1.18 2004/04/24 15:49:00 kleink Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/device.h> 45 #include <sys/systm.h> 46 #include <sys/extent.h> 47 #include <sys/malloc.h> 48 #include <sys/null.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pciconf.h> 52 53 #include <machine/intr.h> 54 55 #include <arm/cpufunc.h> 56 57 #include "opt_pci.h" 58 #include "pci.h" 59 60 #include <evbarm/ifpga/ifpgamem.h> 61 #include <evbarm/ifpga/ifpgavar.h> 62 #include <evbarm/ifpga/ifpgareg.h> 63 #include <evbarm/ifpga/ifpga_pcivar.h> 64 #include <evbarm/dev/v360reg.h> 65 66 #include <evbarm/integrator/int_bus_dma.h> 67 #include "locators.h" 68 69 /* Prototypes */ 70 static int ifpga_match (struct device *, struct cfdata *, void *); 71 static void ifpga_attach (struct device *, struct device *, void *); 72 static int ifpga_print (void *, const char *); 73 static int ifpga_pci_print (void *, const char *); 74 75 /* Drive and attach structures */ 76 CFATTACH_DECL(ifpga, sizeof(struct ifpga_softc), 77 ifpga_match, ifpga_attach, NULL, NULL); 78 79 int ifpga_found; 80 81 /* Default UART clock speed (we should make this a boot option). */ 82 int ifpga_uart_clk = IFPGA_UART_CLK; 83 84 #if NPCI > 0 85 /* PCI handles */ 86 extern struct arm32_pci_chipset ifpga_pci_chipset; 87 extern struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag; 88 89 static struct bus_space ifpga_pci_io_tag; 90 static struct bus_space ifpga_pci_mem_tag; 91 #endif /* NPCI > 0 */ 92 93 static struct bus_space ifpga_bs_tag; 94 95 struct ifpga_softc *ifpga_sc; 96 /* 97 * Print the configuration information for children 98 */ 99 100 static int 101 ifpga_print(void *aux, const char *pnp) 102 { 103 struct ifpga_attach_args *ifa = aux; 104 105 if (ifa->ifa_addr != -1) 106 aprint_normal(" addr 0x%lx", (unsigned long)ifa->ifa_addr); 107 if (ifa->ifa_irq != -1) 108 aprint_normal(" irq %d", ifa->ifa_irq); 109 110 return UNCONF; 111 } 112 113 #if NPCI > 0 114 static int 115 ifpga_pci_print(void *aux, const char *pnp) 116 { 117 struct pcibus_attach_args *pci_pba = (struct pcibus_attach_args *)aux; 118 119 if (pnp) 120 aprint_normal("%s at %s", pci_pba->pba_busname, pnp); 121 if (strcmp(pci_pba->pba_busname, "pci") == 0) 122 aprint_normal(" bus %d", pci_pba->pba_bus); 123 124 return UNCONF; 125 } 126 #endif 127 128 static int 129 ifpga_search(struct device *parent, struct cfdata *cf, void *aux) 130 { 131 struct ifpga_softc *sc = (struct ifpga_softc *)parent; 132 struct ifpga_attach_args ifa; 133 int tryagain; 134 135 do { 136 ifa.ifa_name = "ifpga_periph"; 137 ifa.ifa_iot = sc->sc_iot; 138 ifa.ifa_addr = cf->cf_iobase; 139 ifa.ifa_irq = cf->cf_irq; 140 ifa.ifa_sc_ioh = sc->sc_sc_ioh; 141 142 tryagain = 0; 143 if (config_match(parent, cf, &ifa) > 0) { 144 config_attach(parent, cf, &ifa, ifpga_print); 145 tryagain = (cf->cf_fstate == FSTATE_STAR); 146 } 147 } while (tryagain); 148 149 return 0; 150 } 151 152 static int 153 ifpga_match(struct device *parent, struct cfdata *cf, void *aux) 154 { 155 #if 0 156 struct mainbus_attach_args *ma = aux; 157 158 /* Make sure that we're looking for the IFPGA. */ 159 if (strcmp(ma->ma_name, ifpga_md.md_name)) 160 return 0; 161 #endif 162 163 /* We can only have one instance of the IFPGA. */ 164 if (ifpga_found) 165 return 0; 166 167 return 1; 168 } 169 170 static void 171 ifpga_attach(struct device *parent, struct device *self, void *aux) 172 { 173 struct ifpga_softc *sc = (struct ifpga_softc *)self; 174 u_int id, sysclk; 175 #if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0 176 struct extent *ioext, *memext, *pmemext; 177 struct ifpga_pci_softc *pci_sc; 178 struct pcibus_attach_args pci_pba; 179 #endif 180 181 ifpga_found = 1; 182 183 /* We want a memory-mapped bus space, since the I/O space is sparse. */ 184 ifpga_create_mem_bs_tag(&ifpga_bs_tag, (void *)IFPGA_IO_BASE); 185 186 #if NPCI > 0 187 /* But the PCI config space is quite large, so we have a linear region 188 for that pre-allocated. */ 189 190 ifpga_create_io_bs_tag(&ifpga_pci_io_tag, (void *)IFPGA_PCI_IO_VBASE); 191 ifpga_create_mem_bs_tag(&ifpga_pci_mem_tag, (void *)0); 192 #endif 193 194 sc->sc_iot = &ifpga_bs_tag; 195 196 ifpga_sc = sc; 197 198 /* Now map in the IFPGA motherboard registers. */ 199 if (bus_space_map(sc->sc_iot, IFPGA_IO_SC_BASE, IFPGA_IO_SC_SIZE, 0, 200 &sc->sc_sc_ioh)) 201 panic("%s: Cannot map system controller registers", 202 self->dv_xname); 203 204 id = bus_space_read_4(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_ID); 205 206 printf(": Build %d, ", (id & IFPGA_SC_ID_BUILD_MASK) >> 207 IFPGA_SC_ID_BUILD_SHIFT); 208 switch (id & IFPGA_SC_ID_REV_MASK) 209 { 210 case IFPGA_SC_ID_REV_A: 211 printf("Rev A, "); 212 break; 213 case IFPGA_SC_ID_REV_B: 214 printf("Rev B, "); 215 break; 216 } 217 218 printf("Manufacturer "); 219 switch (id & IFPGA_SC_ID_MAN_MASK) 220 { 221 case IFPGA_SC_ID_MAN_ARM: 222 printf("ARM Ltd,"); 223 break; 224 default: 225 printf("Unknown,"); 226 break; 227 } 228 229 switch (id & IFPGA_SC_ID_ARCH_MASK) 230 { 231 case IFPGA_SC_ID_ARCH_ASBLE: 232 printf(" ASB, Little-endian,"); 233 break; 234 case IFPGA_SC_ID_ARCH_AHBLE: 235 printf(" AHB, Little-endian,"); 236 break; 237 default: 238 panic(" Unsupported bus"); 239 } 240 241 printf("\n%s: FPGA ", self->dv_xname); 242 243 switch (id & IFPGA_SC_ID_FPGA_MASK) 244 { 245 case IFPGA_SC_ID_FPGA_XC4062: 246 printf("XC4062"); 247 break; 248 case IFPGA_SC_ID_FPGA_XC4085: 249 printf("XC4085"); 250 break; 251 default: 252 printf("unknown"); 253 break; 254 } 255 256 sysclk = bus_space_read_1(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_OSC); 257 sysclk &= IFPGA_SC_OSC_S_VDW; 258 sysclk += 8; 259 260 printf(", SYSCLK %d.%02dMHz", sysclk >> 2, (sysclk & 3) * 25); 261 262 /* Map the Interrupt controller */ 263 if (bus_space_map(sc->sc_iot, IFPGA_IO_IRQ_BASE, IFPGA_IO_IRQ_SIZE, 264 BUS_SPACE_MAP_LINEAR, &sc->sc_irq_ioh)) 265 panic("%s: Cannot map irq controller registers", 266 self->dv_xname); 267 268 /* We can write to the IRQ/FIQ controller now. */ 269 ifpga_intr_postinit(); 270 271 /* Map the core module */ 272 if (bus_space_map(sc->sc_iot, IFPGA_IO_CM_BASE, IFPGA_IO_CM_SIZE, 0, 273 &sc->sc_cm_ioh)) 274 panic("%s: Cannot map core module registers", self->dv_xname); 275 276 /* Map the timers */ 277 if (bus_space_map(sc->sc_iot, IFPGA_IO_TMR_BASE, IFPGA_IO_TMR_SIZE, 0, 278 &sc->sc_tmr_ioh)) 279 panic("%s: Cannot map timer registers", self->dv_xname); 280 281 printf("\n"); 282 283 #if NPCI > 0 284 pci_sc = malloc(sizeof(struct ifpga_pci_softc), M_DEVBUF, M_WAITOK); 285 pci_sc->sc_iot = &ifpga_pci_io_tag; 286 pci_sc->sc_memt = &ifpga_pci_mem_tag; 287 288 if (bus_space_map(pci_sc->sc_iot, 0, IFPGA_PCI_IO_VSIZE, 0, 289 &pci_sc->sc_io_ioh) 290 || bus_space_map(pci_sc->sc_iot, 291 IFPGA_PCI_CONF_VBASE - IFPGA_PCI_IO_VBASE, IFPGA_PCI_CONF_VSIZE, 0, 292 &pci_sc->sc_conf_ioh) 293 || bus_space_map(pci_sc->sc_memt, IFPGA_V360_REG_BASE, 294 IFPGA_V360_REG_SIZE, 0, &pci_sc->sc_reg_ioh)) 295 panic("%s: Cannot map pci memory", self->dv_xname); 296 297 { 298 pcireg_t id_reg, class_reg; 299 char buf[1000]; 300 301 id_reg = bus_space_read_4(pci_sc->sc_memt, pci_sc->sc_reg_ioh, 302 V360_PCI_VENDOR); 303 class_reg = bus_space_read_4(pci_sc->sc_memt, 304 pci_sc->sc_reg_ioh, V360_PCI_CC_REV); 305 306 pci_devinfo(id_reg, class_reg, 1, buf, sizeof(buf)); 307 printf("%s: %s\n", self->dv_xname, buf); 308 } 309 310 #if defined(PCI_NETBSD_CONFIGURE) 311 ioext = extent_create("pciio", 0x00000000, 312 0x00000000 + IFPGA_PCI_IO_VSIZE, M_DEVBUF, NULL, 0, EX_NOWAIT); 313 memext = extent_create("pcimem", IFPGA_PCI_APP0_BASE, 314 IFPGA_PCI_APP0_BASE + IFPGA_PCI_APP0_SIZE, 315 M_DEVBUF, NULL, 0, EX_NOWAIT); 316 pmemext = extent_create("pcipmem", IFPGA_PCI_APP1_BASE, 317 IFPGA_PCI_APP1_BASE + IFPGA_PCI_APP1_SIZE, 318 M_DEVBUF, NULL, 0, EX_NOWAIT); 319 ifpga_pci_chipset.pc_conf_v = (void *)pci_sc; 320 pci_configure_bus(&ifpga_pci_chipset, ioext, memext, pmemext, 0, 321 arm_dcache_align); 322 extent_destroy(pmemext); 323 extent_destroy(memext); 324 extent_destroy(ioext); 325 326 printf("pci_configure_bus done\n"); 327 #endif /* PCI_NETBSD_CONFIGURE */ 328 #endif /* NPCI > 0 */ 329 330 /* Finally, search for children. */ 331 config_search(ifpga_search, self, NULL); 332 333 #if NPCI > 0 334 integrator_pci_dma_init(&ifpga_pci_bus_dma_tag); 335 336 pci_pba.pba_busname = "pci"; 337 pci_pba.pba_pc = &ifpga_pci_chipset; 338 pci_pba.pba_iot = &ifpga_pci_io_tag; 339 pci_pba.pba_memt = &ifpga_pci_mem_tag; 340 pci_pba.pba_dmat = &ifpga_pci_bus_dma_tag; 341 pci_pba.pba_dmat64 = NULL; 342 pci_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 343 pci_pba.pba_bus = 0; 344 pci_pba.pba_bridgetag = NULL; 345 346 config_found(self, &pci_pba, ifpga_pci_print); 347 #endif 348 } 349 350 void 351 ifpga_reset(void) 352 { 353 bus_space_write_1(ifpga_sc->sc_iot, ifpga_sc->sc_sc_ioh, 354 IFPGA_SC_CTRLS, IFPGA_SC_CTRL_SOFTRESET); 355 } 356
Indexes created Tue Sep 30 11:09:46 GMT 2025