ifpga.c revision 1.22
1 /* $NetBSD: ifpga.c,v 1.22 2008/04/27 18:58:46 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * Integrator FPGA core logic support. 34 * 35 * The integrator board supports the core logic in an FPGA which is loaded 36 * at POR with a custom design. This code supports the default logic as the 37 * board is shipped. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: ifpga.c,v 1.22 2008/04/27 18:58:46 matt Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/types.h> 45 #include <sys/device.h> 46 #include <sys/systm.h> 47 #include <sys/extent.h> 48 #include <sys/malloc.h> 49 #include <sys/null.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pciconf.h> 53 54 #include <arm/cpufunc.h> 55 56 #include "opt_pci.h" 57 #include "pci.h" 58 59 #include <evbarm/ifpga/ifpgamem.h> 60 #include <evbarm/ifpga/ifpgavar.h> 61 #include <evbarm/ifpga/ifpgareg.h> 62 #include <evbarm/ifpga/ifpga_pcivar.h> 63 #include <evbarm/dev/v360reg.h> 64 65 #include <evbarm/integrator/int_bus_dma.h> 66 #include "locators.h" 67 68 /* Prototypes */ 69 static int ifpga_match (struct device *, struct cfdata *, void *); 70 static void ifpga_attach (struct device *, struct device *, void *); 71 static int ifpga_print (void *, const char *); 72 73 /* Drive and attach structures */ 74 CFATTACH_DECL(ifpga, sizeof(struct ifpga_softc), 75 ifpga_match, ifpga_attach, NULL, NULL); 76 77 int ifpga_found; 78 79 /* Default UART clock speed (we should make this a boot option). */ 80 int ifpga_uart_clk = IFPGA_UART_CLK; 81 82 #if NPCI > 0 83 /* PCI handles */ 84 extern struct arm32_pci_chipset ifpga_pci_chipset; 85 extern struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag; 86 87 static struct bus_space ifpga_pci_io_tag; 88 static struct bus_space ifpga_pci_mem_tag; 89 #endif /* NPCI > 0 */ 90 91 static struct bus_space ifpga_bs_tag; 92 93 struct ifpga_softc *ifpga_sc; 94 /* 95 * Print the configuration information for children 96 */ 97 98 static int 99 ifpga_print(void *aux, const char *pnp) 100 { 101 struct ifpga_attach_args *ifa = aux; 102 103 if (ifa->ifa_addr != -1) 104 aprint_normal(" addr 0x%lx", (unsigned long)ifa->ifa_addr); 105 if (ifa->ifa_irq != -1) 106 aprint_normal(" irq %d", ifa->ifa_irq); 107 108 return UNCONF; 109 } 110 111 static int 112 ifpga_search(struct device *parent, struct cfdata *cf, 113 const int *ldesc, void *aux) 114 { 115 struct ifpga_softc *sc = (struct ifpga_softc *)parent; 116 struct ifpga_attach_args ifa; 117 int tryagain; 118 119 do { 120 ifa.ifa_iot = sc->sc_iot; 121 ifa.ifa_addr = cf->cf_iobase; 122 ifa.ifa_irq = cf->cf_irq; 123 ifa.ifa_sc_ioh = sc->sc_sc_ioh; 124 125 tryagain = 0; 126 if (config_match(parent, cf, &ifa) > 0) { 127 config_attach(parent, cf, &ifa, ifpga_print); 128 tryagain = (cf->cf_fstate == FSTATE_STAR); 129 } 130 } while (tryagain); 131 132 return 0; 133 } 134 135 static int 136 ifpga_match(struct device *parent, struct cfdata *cf, void *aux) 137 { 138 #if 0 139 struct mainbus_attach_args *ma = aux; 140 141 /* Make sure that we're looking for the IFPGA. */ 142 if (strcmp(ma->ma_name, ifpga_md.md_name)) 143 return 0; 144 #endif 145 146 /* We can only have one instance of the IFPGA. */ 147 if (ifpga_found) 148 return 0; 149 150 return 1; 151 } 152 153 static void 154 ifpga_attach(struct device *parent, struct device *self, void *aux) 155 { 156 struct ifpga_softc *sc = (struct ifpga_softc *)self; 157 u_int id, sysclk; 158 #if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0 159 struct extent *ioext, *memext, *pmemext; 160 struct ifpga_pci_softc *pci_sc; 161 struct pcibus_attach_args pci_pba; 162 #endif 163 164 ifpga_found = 1; 165 166 /* We want a memory-mapped bus space, since the I/O space is sparse. */ 167 ifpga_create_mem_bs_tag(&ifpga_bs_tag, (void *)IFPGA_IO_BASE); 168 169 #if NPCI > 0 170 /* But the PCI config space is quite large, so we have a linear region 171 for that pre-allocated. */ 172 173 ifpga_create_io_bs_tag(&ifpga_pci_io_tag, (void *)IFPGA_PCI_IO_VBASE); 174 ifpga_create_mem_bs_tag(&ifpga_pci_mem_tag, (void *)0); 175 #endif 176 177 sc->sc_iot = &ifpga_bs_tag; 178 179 ifpga_sc = sc; 180 181 /* Now map in the IFPGA motherboard registers. */ 182 if (bus_space_map(sc->sc_iot, IFPGA_IO_SC_BASE, IFPGA_IO_SC_SIZE, 0, 183 &sc->sc_sc_ioh)) 184 panic("%s: Cannot map system controller registers", 185 self->dv_xname); 186 187 id = bus_space_read_4(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_ID); 188 189 printf(": Build %d, ", (id & IFPGA_SC_ID_BUILD_MASK) >> 190 IFPGA_SC_ID_BUILD_SHIFT); 191 switch (id & IFPGA_SC_ID_REV_MASK) 192 { 193 case IFPGA_SC_ID_REV_A: 194 printf("Rev A, "); 195 break; 196 case IFPGA_SC_ID_REV_B: 197 printf("Rev B, "); 198 break; 199 } 200 201 printf("Manufacturer "); 202 switch (id & IFPGA_SC_ID_MAN_MASK) 203 { 204 case IFPGA_SC_ID_MAN_ARM: 205 printf("ARM Ltd,"); 206 break; 207 default: 208 printf("Unknown,"); 209 break; 210 } 211 212 switch (id & IFPGA_SC_ID_ARCH_MASK) 213 { 214 case IFPGA_SC_ID_ARCH_ASBLE: 215 printf(" ASB, Little-endian,"); 216 break; 217 case IFPGA_SC_ID_ARCH_AHBLE: 218 printf(" AHB, Little-endian,"); 219 break; 220 default: 221 panic(" Unsupported bus"); 222 } 223 224 printf("\n%s: FPGA ", self->dv_xname); 225 226 switch (id & IFPGA_SC_ID_FPGA_MASK) 227 { 228 case IFPGA_SC_ID_FPGA_XC4062: 229 printf("XC4062"); 230 break; 231 case IFPGA_SC_ID_FPGA_XC4085: 232 printf("XC4085"); 233 break; 234 default: 235 printf("unknown"); 236 break; 237 } 238 239 sysclk = bus_space_read_1(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_OSC); 240 sysclk &= IFPGA_SC_OSC_S_VDW; 241 sysclk += 8; 242 243 printf(", SYSCLK %d.%02dMHz", sysclk >> 2, (sysclk & 3) * 25); 244 245 /* Map the Interrupt controller */ 246 if (bus_space_map(sc->sc_iot, IFPGA_IO_IRQ_BASE, IFPGA_IO_IRQ_SIZE, 247 BUS_SPACE_MAP_LINEAR, &sc->sc_irq_ioh)) 248 panic("%s: Cannot map irq controller registers", 249 self->dv_xname); 250 251 /* We can write to the IRQ/FIQ controller now. */ 252 ifpga_intr_postinit(); 253 254 /* Map the core module */ 255 if (bus_space_map(sc->sc_iot, IFPGA_IO_CM_BASE, IFPGA_IO_CM_SIZE, 0, 256 &sc->sc_cm_ioh)) 257 panic("%s: Cannot map core module registers", self->dv_xname); 258 259 /* Map the timers */ 260 if (bus_space_map(sc->sc_iot, IFPGA_IO_TMR_BASE, IFPGA_IO_TMR_SIZE, 0, 261 &sc->sc_tmr_ioh)) 262 panic("%s: Cannot map timer registers", self->dv_xname); 263 264 printf("\n"); 265 266 #if NPCI > 0 267 pci_sc = malloc(sizeof(struct ifpga_pci_softc), M_DEVBUF, M_WAITOK); 268 pci_sc->sc_iot = &ifpga_pci_io_tag; 269 pci_sc->sc_memt = &ifpga_pci_mem_tag; 270 271 if (bus_space_map(pci_sc->sc_iot, 0, IFPGA_PCI_IO_VSIZE, 0, 272 &pci_sc->sc_io_ioh) 273 || bus_space_map(pci_sc->sc_iot, 274 IFPGA_PCI_CONF_VBASE - IFPGA_PCI_IO_VBASE, IFPGA_PCI_CONF_VSIZE, 0, 275 &pci_sc->sc_conf_ioh) 276 || bus_space_map(pci_sc->sc_memt, IFPGA_V360_REG_BASE, 277 IFPGA_V360_REG_SIZE, 0, &pci_sc->sc_reg_ioh)) 278 panic("%s: Cannot map pci memory", self->dv_xname); 279 280 { 281 pcireg_t id_reg, class_reg; 282 char buf[1000]; 283 284 id_reg = bus_space_read_4(pci_sc->sc_memt, pci_sc->sc_reg_ioh, 285 V360_PCI_VENDOR); 286 class_reg = bus_space_read_4(pci_sc->sc_memt, 287 pci_sc->sc_reg_ioh, V360_PCI_CC_REV); 288 289 pci_devinfo(id_reg, class_reg, 1, buf, sizeof(buf)); 290 printf("%s: %s\n", self->dv_xname, buf); 291 } 292 293 #if defined(PCI_NETBSD_CONFIGURE) 294 ioext = extent_create("pciio", 0x00000000, 295 0x00000000 + IFPGA_PCI_IO_VSIZE, M_DEVBUF, NULL, 0, EX_NOWAIT); 296 memext = extent_create("pcimem", IFPGA_PCI_APP0_BASE, 297 IFPGA_PCI_APP0_BASE + IFPGA_PCI_APP0_SIZE, 298 M_DEVBUF, NULL, 0, EX_NOWAIT); 299 pmemext = extent_create("pcipmem", IFPGA_PCI_APP1_BASE, 300 IFPGA_PCI_APP1_BASE + IFPGA_PCI_APP1_SIZE, 301 M_DEVBUF, NULL, 0, EX_NOWAIT); 302 ifpga_pci_chipset.pc_conf_v = (void *)pci_sc; 303 pci_configure_bus(&ifpga_pci_chipset, ioext, memext, pmemext, 0, 304 arm_dcache_align); 305 extent_destroy(pmemext); 306 extent_destroy(memext); 307 extent_destroy(ioext); 308 309 printf("pci_configure_bus done\n"); 310 #endif /* PCI_NETBSD_CONFIGURE */ 311 #endif /* NPCI > 0 */ 312 313 /* Finally, search for children. */ 314 config_search_ia(ifpga_search, self, "ifpga", NULL); 315 316 #if NPCI > 0 317 integrator_pci_dma_init(&ifpga_pci_bus_dma_tag); 318 319 pci_pba.pba_pc = &ifpga_pci_chipset; 320 pci_pba.pba_iot = &ifpga_pci_io_tag; 321 pci_pba.pba_memt = &ifpga_pci_mem_tag; 322 pci_pba.pba_dmat = &ifpga_pci_bus_dma_tag; 323 pci_pba.pba_dmat64 = NULL; 324 pci_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 325 pci_pba.pba_bus = 0; 326 pci_pba.pba_bridgetag = NULL; 327 328 config_found_ia(self, "pcibus", &pci_pba, pcibusprint); 329 #endif 330 } 331 332 void 333 ifpga_reset(void) 334 { 335 bus_space_write_1(ifpga_sc->sc_iot, ifpga_sc->sc_sc_ioh, 336 IFPGA_SC_CTRLS, IFPGA_SC_CTRL_SOFTRESET); 337 } 338
Indexes created Mon Sep 29 21:09:56 GMT 2025