ifpga.c revision 1.6
1 /* $NetBSD: ifpga.c,v 1.6 2002/01/30 03:59:41 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * Integrator FPGA core logic support. 34 * 35 * The integrator board supports the core logic in an FPGA which is loaded 36 * at POR with a custom design. This code supports the default logic as the 37 * board is shipped. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/device.h> 42 #include <sys/systm.h> 43 #include <sys/extent.h> 44 #include <sys/malloc.h> 45 #include <sys/null.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pciconf.h> 49 50 #include <machine/intr.h> 51 #include <evbarm/ifpga/irqhandler.h> /* XXX XXX XXX */ 52 53 #include <arm/cpufunc.h> 54 55 #include "opt_cputypes.h" 56 #include "opt_pci.h" 57 #include "pci.h" 58 59 #include <evbarm/ifpga/ifpgamem.h> 60 #include <evbarm/ifpga/ifpgavar.h> 61 #include <evbarm/ifpga/ifpgareg.h> 62 #include <evbarm/ifpga/ifpga_pcivar.h> 63 #include <evbarm/dev/v360reg.h> 64 65 /* Prototypes */ 66 static int ifpga_match (struct device *, struct cfdata *, void *); 67 static void ifpga_attach (struct device *, struct device *, void *); 68 static int ifpga_print (void *, const char *); 69 static int ifpga_pci_print (void *, const char *); 70 71 /* Drive and attach structures */ 72 struct cfattach ifpga_ca = { 73 sizeof(struct ifpga_softc), ifpga_match, ifpga_attach 74 }; 75 76 int ifpga_found; 77 78 /* Default UART clock speed (we should make this a boot option). */ 79 int ifpga_uart_clk = IFPGA_UART_CLK; 80 81 /* Virtual base of IRQ controller. */ 82 void *ifpga_irq_vbase; 83 84 #if NPCI > 0 85 /* PCI handles */ 86 extern struct arm32_pci_chipset ifpga_pci_chipset; 87 extern struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag; 88 89 static struct bus_space ifpga_pci_io_tag; 90 static struct bus_space ifpga_pci_mem_tag; 91 #endif /* NPCI > 0 */ 92 93 struct ifpga_softc *clock_sc; 94 95 static struct bus_space ifpga_bs_tag; 96 97 static struct ifpga_softc *ifpga_sc; 98 /* 99 * Print the configuration information for children 100 */ 101 102 static int 103 ifpga_print(void *aux, const char *pnp) 104 { 105 struct ifpga_attach_args *ifa = aux; 106 107 if (ifa->ifa_addr != -1) 108 printf(" addr 0x%lx", (unsigned long)ifa->ifa_addr); 109 if (ifa->ifa_irq != -1) 110 printf(" irq %d", ifa->ifa_irq); 111 112 return UNCONF; 113 } 114 115 #if NPCI > 0 116 static int 117 ifpga_pci_print(void *aux, const char *pnp) 118 { 119 struct pcibus_attach_args *pci_pba = (struct pcibus_attach_args *)aux; 120 121 if (pnp) 122 printf("%s at %s", pci_pba->pba_busname, pnp); 123 if (strcmp(pci_pba->pba_busname, "pci") == 0) 124 printf(" bus %d", pci_pba->pba_bus); 125 126 return UNCONF; 127 } 128 #endif 129 130 static int 131 ifpga_search(struct device *parent, struct cfdata *cf, void *aux) 132 { 133 struct ifpga_softc *sc = (struct ifpga_softc *)parent; 134 struct ifpga_attach_args ifa; 135 int tryagain; 136 137 do { 138 ifa.ifa_name = "ifpga_periph"; 139 ifa.ifa_iot = sc->sc_iot; 140 ifa.ifa_addr = cf->cf_iobase; 141 ifa.ifa_irq = cf->cf_irq; 142 ifa.ifa_sc_ioh = sc->sc_sc_ioh; 143 144 tryagain = 0; 145 if ((*cf->cf_attach->ca_match)(parent, cf, &ifa) > 0) { 146 config_attach(parent, cf, &ifa, ifpga_print); 147 tryagain = (cf->cf_fstate == FSTATE_STAR); 148 } 149 } while (tryagain); 150 151 return 0; 152 } 153 154 static int 155 ifpga_match(struct device *parent, struct cfdata *cf, void *aux) 156 { 157 #if 0 158 struct mainbus_attach_args *ma = aux; 159 160 /* Make sure that we're looking for the IFPGA. */ 161 if (strcmp(ma->ma_name, ifpga_md.md_name)) 162 return 0; 163 #endif 164 165 /* We can only have one instance of the IFPGA. */ 166 if (ifpga_found) 167 return 0; 168 169 return 1; 170 } 171 172 static void 173 ifpga_attach(struct device *parent, struct device *self, void *aux) 174 { 175 struct ifpga_softc *sc = (struct ifpga_softc *)self; 176 u_int id, sysclk; 177 #if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0 178 struct extent *ioext, *memext, *pmemext; 179 struct ifpga_pci_softc *pci_sc; 180 struct pcibus_attach_args pci_pba; 181 #endif 182 183 ifpga_found = 1; 184 185 /* We want a memory-mapped bus space, since the I/O space is sparse. */ 186 ifpga_create_mem_bs_tag(&ifpga_bs_tag, (void *)IFPGA_IO_BASE); 187 188 #if NPCI > 0 189 /* But the PCI config space is quite large, so we have a linear region 190 for that pre-allocated. */ 191 192 ifpga_create_io_bs_tag(&ifpga_pci_io_tag, (void *)IFPGA_PCI_IO_VBASE); 193 ifpga_create_mem_bs_tag(&ifpga_pci_mem_tag, (void *)0); 194 #endif 195 196 sc->sc_iot = &ifpga_bs_tag; 197 198 ifpga_sc = sc; 199 200 /* Now map in the IFPGA motherboard registers. */ 201 if (bus_space_map(sc->sc_iot, IFPGA_IO_SC_BASE, IFPGA_IO_SC_SIZE, 0, 202 &sc->sc_sc_ioh)) 203 panic("%s: Cannot map system controller registers", 204 self->dv_xname); 205 206 id = bus_space_read_4(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_ID); 207 208 printf(": Build %d, ", (id & IFPGA_SC_ID_BUILD_MASK) >> 209 IFPGA_SC_ID_BUILD_SHIFT); 210 switch (id & IFPGA_SC_ID_REV_MASK) 211 { 212 case IFPGA_SC_ID_REV_A: 213 printf("Rev A, "); 214 break; 215 case IFPGA_SC_ID_REV_B: 216 printf("Rev B, "); 217 break; 218 } 219 220 printf("Manufacturer "); 221 switch (id & IFPGA_SC_ID_MAN_MASK) 222 { 223 case IFPGA_SC_ID_MAN_ARM: 224 printf("ARM Ltd,"); 225 break; 226 default: 227 printf("Unknown,"); 228 break; 229 } 230 231 switch (id & IFPGA_SC_ID_ARCH_MASK) 232 { 233 case IFPGA_SC_ID_ARCH_ASBLE: 234 printf(" ASB, Little-endian,"); 235 break; 236 case IFPGA_SC_ID_ARCH_AHBLE: 237 printf(" AHB, Little-endian,"); 238 break; 239 default: 240 panic(" Unsupported bus"); 241 } 242 243 printf("\n%s: FPGA ", self->dv_xname); 244 245 switch (id & IFPGA_SC_ID_FPGA_MASK) 246 { 247 case IFPGA_SC_ID_FPGA_XC4062: 248 printf("XC4062"); 249 break; 250 case IFPGA_SC_ID_FPGA_XC4085: 251 printf("XC4085"); 252 break; 253 default: 254 printf("unknown"); 255 break; 256 } 257 258 sysclk = bus_space_read_1(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_OSC); 259 sysclk &= IFPGA_SC_OSC_S_VDW; 260 sysclk += 8; 261 262 printf(", SYSCLK %d.%02dMHz", sysclk >> 2, (sysclk & 3) * 25); 263 264 /* Map the Interrupt controller */ 265 if (bus_space_map(sc->sc_iot, IFPGA_IO_IRQ_BASE, IFPGA_IO_IRQ_SIZE, 266 BUS_SPACE_MAP_LINEAR, &sc->sc_irq_ioh)) 267 panic("%s: Cannot map irq controller registers", 268 self->dv_xname); 269 ifpga_irq_vbase = bus_space_vaddr(sc->sc_iot, sc->sc_irq_ioh); 270 271 /* We can write to the IRQ/FIQ controller now. */ 272 irq_postinit(); 273 274 /* Map the core module */ 275 if (bus_space_map(sc->sc_iot, IFPGA_IO_CM_BASE, IFPGA_IO_CM_SIZE, 0, 276 &sc->sc_cm_ioh)) 277 panic("%s: Cannot map core module registers", self->dv_xname); 278 279 /* Map the timers */ 280 if (bus_space_map(sc->sc_iot, IFPGA_IO_TMR_BASE, IFPGA_IO_TMR_SIZE, 0, 281 &sc->sc_tmr_ioh)) 282 panic("%s: Cannot map timer registers", self->dv_xname); 283 284 clock_sc = sc; 285 286 printf("\n"); 287 288 #if NPCI > 0 289 pci_sc = malloc(sizeof(struct ifpga_pci_softc), M_DEVBUF, M_WAITOK); 290 pci_sc->sc_iot = &ifpga_pci_io_tag; 291 pci_sc->sc_memt = &ifpga_pci_mem_tag; 292 293 if (bus_space_map(pci_sc->sc_iot, 0, IFPGA_PCI_IO_VSIZE, 0, 294 &pci_sc->sc_io_ioh) 295 || bus_space_map(pci_sc->sc_iot, 296 IFPGA_PCI_CONF_VBASE - IFPGA_PCI_IO_VBASE, IFPGA_PCI_CONF_VSIZE, 0, 297 &pci_sc->sc_conf_ioh) 298 || bus_space_map(pci_sc->sc_memt, IFPGA_V360_REG_BASE, 299 IFPGA_V360_REG_SIZE, 0, &pci_sc->sc_reg_ioh)) 300 panic("%s: Cannot map pci memory", self->dv_xname); 301 302 { 303 pcireg_t id_reg, class_reg; 304 char buf[1000]; 305 306 id_reg = bus_space_read_4(pci_sc->sc_memt, pci_sc->sc_reg_ioh, 307 V360_PCI_VENDOR); 308 class_reg = bus_space_read_4(pci_sc->sc_memt, 309 pci_sc->sc_reg_ioh, V360_PCI_CC_REV); 310 311 pci_devinfo(id_reg, class_reg, 1, buf); 312 printf("%s: %s\n", self->dv_xname, buf); 313 } 314 315 #if defined(PCI_NETBSD_CONFIGURE) 316 ioext = extent_create("pciio", 0x00000000, 317 0x00000000 + IFPGA_PCI_IO_VSIZE, M_DEVBUF, NULL, 0, EX_NOWAIT); 318 memext = extent_create("pcimem", IFPGA_PCI_APP0_BASE, 319 IFPGA_PCI_APP0_BASE + IFPGA_PCI_APP0_SIZE, 320 M_DEVBUF, NULL, 0, EX_NOWAIT); 321 pmemext = extent_create("pcipmem", IFPGA_PCI_APP1_BASE, 322 IFPGA_PCI_APP1_BASE + IFPGA_PCI_APP1_SIZE, 323 M_DEVBUF, NULL, 0, EX_NOWAIT); 324 ifpga_pci_chipset.pc_conf_v = (void *)pci_sc; 325 pci_configure_bus(&ifpga_pci_chipset, ioext, memext, pmemext, 0, 326 arm_dcache_align); 327 extent_destroy(pmemext); 328 extent_destroy(memext); 329 extent_destroy(ioext); 330 331 printf("pci_configure_bus done\n"); 332 #endif /* PCI_NETBSD_CONFIGURE */ 333 #endif /* NPCI > 0 */ 334 335 /* Finally, search for children. */ 336 config_search(ifpga_search, self, NULL); 337 338 #if NPCI > 0 339 pci_pba.pba_busname = "pci"; 340 pci_pba.pba_pc = &ifpga_pci_chipset; 341 pci_pba.pba_iot = &ifpga_pci_io_tag; 342 pci_pba.pba_memt = &ifpga_pci_mem_tag; 343 pci_pba.pba_dmat = &ifpga_pci_bus_dma_tag; 344 pci_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 345 pci_pba.pba_bus = 0; 346 347 config_found(self, &pci_pba, ifpga_pci_print); 348 #endif 349 } 350 351 void 352 ifpga_reset(void) 353 { 354 bus_space_write_1(ifpga_sc->sc_iot, ifpga_sc->sc_sc_ioh, 355 IFPGA_SC_CTRLS, IFPGA_SC_CTRL_SOFTRESET); 356 } 357
Indexes created Mon Sep 29 21:09:56 GMT 2025