ifpga.c revision 1.9
1 /* $NetBSD: ifpga.c,v 1.9 2002/05/22 23:54:14 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * Integrator FPGA core logic support. 34 * 35 * The integrator board supports the core logic in an FPGA which is loaded 36 * at POR with a custom design. This code supports the default logic as the 37 * board is shipped. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/device.h> 42 #include <sys/systm.h> 43 #include <sys/extent.h> 44 #include <sys/malloc.h> 45 #include <sys/null.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pciconf.h> 49 50 #include <machine/intr.h> 51 #include <evbarm/ifpga/irqhandler.h> /* XXX XXX XXX */ 52 53 #include <arm/cpufunc.h> 54 55 #include "opt_pci.h" 56 #include "pci.h" 57 58 #include <evbarm/ifpga/ifpgamem.h> 59 #include <evbarm/ifpga/ifpgavar.h> 60 #include <evbarm/ifpga/ifpgareg.h> 61 #include <evbarm/ifpga/ifpga_pcivar.h> 62 #include <evbarm/dev/v360reg.h> 63 64 /* Prototypes */ 65 static int ifpga_match (struct device *, struct cfdata *, void *); 66 static void ifpga_attach (struct device *, struct device *, void *); 67 static int ifpga_print (void *, const char *); 68 static int ifpga_pci_print (void *, const char *); 69 70 /* Drive and attach structures */ 71 struct cfattach ifpga_ca = { 72 sizeof(struct ifpga_softc), ifpga_match, ifpga_attach 73 }; 74 75 int ifpga_found; 76 77 /* Default UART clock speed (we should make this a boot option). */ 78 int ifpga_uart_clk = IFPGA_UART_CLK; 79 80 /* Virtual base of IRQ controller. */ 81 void *ifpga_irq_vbase; 82 83 #if NPCI > 0 84 /* PCI handles */ 85 extern struct arm32_pci_chipset ifpga_pci_chipset; 86 extern struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag; 87 88 static struct bus_space ifpga_pci_io_tag; 89 static struct bus_space ifpga_pci_mem_tag; 90 #endif /* NPCI > 0 */ 91 92 struct ifpga_softc *clock_sc; 93 94 static struct bus_space ifpga_bs_tag; 95 96 static struct ifpga_softc *ifpga_sc; 97 /* 98 * Print the configuration information for children 99 */ 100 101 static int 102 ifpga_print(void *aux, const char *pnp) 103 { 104 struct ifpga_attach_args *ifa = aux; 105 106 if (ifa->ifa_addr != -1) 107 printf(" addr 0x%lx", (unsigned long)ifa->ifa_addr); 108 if (ifa->ifa_irq != -1) 109 printf(" irq %d", ifa->ifa_irq); 110 111 return UNCONF; 112 } 113 114 #if NPCI > 0 115 static int 116 ifpga_pci_print(void *aux, const char *pnp) 117 { 118 struct pcibus_attach_args *pci_pba = (struct pcibus_attach_args *)aux; 119 120 if (pnp) 121 printf("%s at %s", pci_pba->pba_busname, pnp); 122 if (strcmp(pci_pba->pba_busname, "pci") == 0) 123 printf(" bus %d", pci_pba->pba_bus); 124 125 return UNCONF; 126 } 127 #endif 128 129 static int 130 ifpga_search(struct device *parent, struct cfdata *cf, void *aux) 131 { 132 struct ifpga_softc *sc = (struct ifpga_softc *)parent; 133 struct ifpga_attach_args ifa; 134 int tryagain; 135 136 do { 137 ifa.ifa_name = "ifpga_periph"; 138 ifa.ifa_iot = sc->sc_iot; 139 ifa.ifa_addr = cf->cf_iobase; 140 ifa.ifa_irq = cf->cf_irq; 141 ifa.ifa_sc_ioh = sc->sc_sc_ioh; 142 143 tryagain = 0; 144 if ((*cf->cf_attach->ca_match)(parent, cf, &ifa) > 0) { 145 config_attach(parent, cf, &ifa, ifpga_print); 146 tryagain = (cf->cf_fstate == FSTATE_STAR); 147 } 148 } while (tryagain); 149 150 return 0; 151 } 152 153 static int 154 ifpga_match(struct device *parent, struct cfdata *cf, void *aux) 155 { 156 #if 0 157 struct mainbus_attach_args *ma = aux; 158 159 /* Make sure that we're looking for the IFPGA. */ 160 if (strcmp(ma->ma_name, ifpga_md.md_name)) 161 return 0; 162 #endif 163 164 /* We can only have one instance of the IFPGA. */ 165 if (ifpga_found) 166 return 0; 167 168 return 1; 169 } 170 171 static void 172 ifpga_attach(struct device *parent, struct device *self, void *aux) 173 { 174 struct ifpga_softc *sc = (struct ifpga_softc *)self; 175 u_int id, sysclk; 176 #if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0 177 struct extent *ioext, *memext, *pmemext; 178 struct ifpga_pci_softc *pci_sc; 179 struct pcibus_attach_args pci_pba; 180 #endif 181 182 ifpga_found = 1; 183 184 /* We want a memory-mapped bus space, since the I/O space is sparse. */ 185 ifpga_create_mem_bs_tag(&ifpga_bs_tag, (void *)IFPGA_IO_BASE); 186 187 #if NPCI > 0 188 /* But the PCI config space is quite large, so we have a linear region 189 for that pre-allocated. */ 190 191 ifpga_create_io_bs_tag(&ifpga_pci_io_tag, (void *)IFPGA_PCI_IO_VBASE); 192 ifpga_create_mem_bs_tag(&ifpga_pci_mem_tag, (void *)0); 193 #endif 194 195 sc->sc_iot = &ifpga_bs_tag; 196 197 ifpga_sc = sc; 198 199 /* Now map in the IFPGA motherboard registers. */ 200 if (bus_space_map(sc->sc_iot, IFPGA_IO_SC_BASE, IFPGA_IO_SC_SIZE, 0, 201 &sc->sc_sc_ioh)) 202 panic("%s: Cannot map system controller registers", 203 self->dv_xname); 204 205 id = bus_space_read_4(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_ID); 206 207 printf(": Build %d, ", (id & IFPGA_SC_ID_BUILD_MASK) >> 208 IFPGA_SC_ID_BUILD_SHIFT); 209 switch (id & IFPGA_SC_ID_REV_MASK) 210 { 211 case IFPGA_SC_ID_REV_A: 212 printf("Rev A, "); 213 break; 214 case IFPGA_SC_ID_REV_B: 215 printf("Rev B, "); 216 break; 217 } 218 219 printf("Manufacturer "); 220 switch (id & IFPGA_SC_ID_MAN_MASK) 221 { 222 case IFPGA_SC_ID_MAN_ARM: 223 printf("ARM Ltd,"); 224 break; 225 default: 226 printf("Unknown,"); 227 break; 228 } 229 230 switch (id & IFPGA_SC_ID_ARCH_MASK) 231 { 232 case IFPGA_SC_ID_ARCH_ASBLE: 233 printf(" ASB, Little-endian,"); 234 break; 235 case IFPGA_SC_ID_ARCH_AHBLE: 236 printf(" AHB, Little-endian,"); 237 break; 238 default: 239 panic(" Unsupported bus"); 240 } 241 242 printf("\n%s: FPGA ", self->dv_xname); 243 244 switch (id & IFPGA_SC_ID_FPGA_MASK) 245 { 246 case IFPGA_SC_ID_FPGA_XC4062: 247 printf("XC4062"); 248 break; 249 case IFPGA_SC_ID_FPGA_XC4085: 250 printf("XC4085"); 251 break; 252 default: 253 printf("unknown"); 254 break; 255 } 256 257 sysclk = bus_space_read_1(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_OSC); 258 sysclk &= IFPGA_SC_OSC_S_VDW; 259 sysclk += 8; 260 261 printf(", SYSCLK %d.%02dMHz", sysclk >> 2, (sysclk & 3) * 25); 262 263 /* Map the Interrupt controller */ 264 if (bus_space_map(sc->sc_iot, IFPGA_IO_IRQ_BASE, IFPGA_IO_IRQ_SIZE, 265 BUS_SPACE_MAP_LINEAR, &sc->sc_irq_ioh)) 266 panic("%s: Cannot map irq controller registers", 267 self->dv_xname); 268 ifpga_irq_vbase = bus_space_vaddr(sc->sc_iot, sc->sc_irq_ioh); 269 270 /* We can write to the IRQ/FIQ controller now. */ 271 irq_postinit(); 272 273 /* Map the core module */ 274 if (bus_space_map(sc->sc_iot, IFPGA_IO_CM_BASE, IFPGA_IO_CM_SIZE, 0, 275 &sc->sc_cm_ioh)) 276 panic("%s: Cannot map core module registers", self->dv_xname); 277 278 /* Map the timers */ 279 if (bus_space_map(sc->sc_iot, IFPGA_IO_TMR_BASE, IFPGA_IO_TMR_SIZE, 0, 280 &sc->sc_tmr_ioh)) 281 panic("%s: Cannot map timer registers", self->dv_xname); 282 283 clock_sc = sc; 284 285 printf("\n"); 286 287 #if NPCI > 0 288 pci_sc = malloc(sizeof(struct ifpga_pci_softc), M_DEVBUF, M_WAITOK); 289 pci_sc->sc_iot = &ifpga_pci_io_tag; 290 pci_sc->sc_memt = &ifpga_pci_mem_tag; 291 292 if (bus_space_map(pci_sc->sc_iot, 0, IFPGA_PCI_IO_VSIZE, 0, 293 &pci_sc->sc_io_ioh) 294 || bus_space_map(pci_sc->sc_iot, 295 IFPGA_PCI_CONF_VBASE - IFPGA_PCI_IO_VBASE, IFPGA_PCI_CONF_VSIZE, 0, 296 &pci_sc->sc_conf_ioh) 297 || bus_space_map(pci_sc->sc_memt, IFPGA_V360_REG_BASE, 298 IFPGA_V360_REG_SIZE, 0, &pci_sc->sc_reg_ioh)) 299 panic("%s: Cannot map pci memory", self->dv_xname); 300 301 { 302 pcireg_t id_reg, class_reg; 303 char buf[1000]; 304 305 id_reg = bus_space_read_4(pci_sc->sc_memt, pci_sc->sc_reg_ioh, 306 V360_PCI_VENDOR); 307 class_reg = bus_space_read_4(pci_sc->sc_memt, 308 pci_sc->sc_reg_ioh, V360_PCI_CC_REV); 309 310 pci_devinfo(id_reg, class_reg, 1, buf); 311 printf("%s: %s\n", self->dv_xname, buf); 312 } 313 314 #if defined(PCI_NETBSD_CONFIGURE) 315 ioext = extent_create("pciio", 0x00000000, 316 0x00000000 + IFPGA_PCI_IO_VSIZE, M_DEVBUF, NULL, 0, EX_NOWAIT); 317 memext = extent_create("pcimem", IFPGA_PCI_APP0_BASE, 318 IFPGA_PCI_APP0_BASE + IFPGA_PCI_APP0_SIZE, 319 M_DEVBUF, NULL, 0, EX_NOWAIT); 320 pmemext = extent_create("pcipmem", IFPGA_PCI_APP1_BASE, 321 IFPGA_PCI_APP1_BASE + IFPGA_PCI_APP1_SIZE, 322 M_DEVBUF, NULL, 0, EX_NOWAIT); 323 ifpga_pci_chipset.pc_conf_v = (void *)pci_sc; 324 pci_configure_bus(&ifpga_pci_chipset, ioext, memext, pmemext, 0, 325 arm_dcache_align); 326 extent_destroy(pmemext); 327 extent_destroy(memext); 328 extent_destroy(ioext); 329 330 printf("pci_configure_bus done\n"); 331 #endif /* PCI_NETBSD_CONFIGURE */ 332 #endif /* NPCI > 0 */ 333 334 /* Finally, search for children. */ 335 config_search(ifpga_search, self, NULL); 336 337 #if NPCI > 0 338 pci_pba.pba_busname = "pci"; 339 pci_pba.pba_pc = &ifpga_pci_chipset; 340 pci_pba.pba_iot = &ifpga_pci_io_tag; 341 pci_pba.pba_memt = &ifpga_pci_mem_tag; 342 pci_pba.pba_dmat = &ifpga_pci_bus_dma_tag; 343 pci_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 344 pci_pba.pba_bus = 0; 345 pci_pba.pba_bridgetag = NULL; 346 347 config_found(self, &pci_pba, ifpga_pci_print); 348 #endif 349 } 350 351 void 352 ifpga_reset(void) 353 { 354 bus_space_write_1(ifpga_sc->sc_iot, ifpga_sc->sc_sc_ioh, 355 IFPGA_SC_CTRLS, IFPGA_SC_CTRL_SOFTRESET); 356 } 357
Indexes created Mon Sep 29 03:10:08 GMT 2025