ifpga_intr.c revision 1.5
1 /* $NetBSD: ifpga_intr.c,v 1.5 2006/11/24 21:20:05 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef EVBARM_SPL_NOINLINE 39 #define EVBARM_SPL_NOINLINE 40 #endif 41 42 /* 43 * Interrupt support for the Integrator FPGA. 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 50 #include <uvm/uvm_extern.h> 51 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 55 #include <arm/cpufunc.h> 56 57 #include <evbarm/ifpga/ifpgareg.h> 58 #include <evbarm/ifpga/ifpgavar.h> 59 60 /* Interrupt handler queues. */ 61 struct intrq intrq[NIRQ]; 62 63 /* Interrupts to mask at each level. */ 64 int ifpga_imask[NIPL]; 65 66 /* Current interrupt priority level. */ 67 volatile int current_spl_level; 68 69 /* Interrupts pending. */ 70 volatile int ifpga_ipending; 71 72 /* Software copy of the IRQs we have enabled. */ 73 volatile uint32_t intr_enabled; 74 75 /* Mask if interrupts steered to FIQs. */ 76 uint32_t intr_steer; 77 78 /* 79 * Map a software interrupt queue index (to the unused bits in the 80 * ICU registers -- XXX will need to revisit this if those bits are 81 * ever used in future steppings). 82 */ 83 static const uint32_t si_to_irqbit[SI_NQUEUES] = { 84 IFPGA_INTR_bit31, /* SI_SOFT */ 85 IFPGA_INTR_bit30, /* SI_SOFTCLOCK */ 86 IFPGA_INTR_bit29, /* SI_SOFTNET */ 87 IFPGA_INTR_bit28, /* SI_SOFTSERIAL */ 88 }; 89 90 #define SI_TO_IRQBIT(si) (si_to_irqbit[(si)]) 91 92 /* 93 * Map a software interrupt queue to an interrupt priority level. 94 */ 95 static const int si_to_ipl[SI_NQUEUES] = { 96 IPL_SOFT, /* SI_SOFT */ 97 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 98 IPL_SOFTNET, /* SI_SOFTNET */ 99 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 100 }; 101 102 /* 103 * Interrupt bit names. 104 */ 105 const char *ifpga_irqnames[] = { 106 "soft", /* 0 */ 107 "uart 0", /* 1 */ 108 "uart 1", /* 2 */ 109 "kbd", /* 3 */ 110 "mouse", /* 4 */ 111 "tmr 0", /* 5 */ 112 "tmr 1 hard", /* 6 */ 113 "tmr 2 stat", /* 7 */ 114 "rtc", /* 8 */ 115 "exp 0", /* 9 */ 116 "exp 1", /* 10 */ 117 "exp 2", /* 11 */ 118 "exp 3", /* 12 */ 119 "pci 0", /* 13 */ 120 "pci 1", /* 14 */ 121 "pci 2", /* 15 */ 122 "pci 3", /* 16 */ 123 "V3 br", /* 17 */ 124 "deg", /* 18 */ 125 "enum", /* 19 */ 126 "pci lb", /* 20 */ 127 "autoPC", /* 21 */ 128 "irq 22", /* 22 */ 129 "irq 23", /* 23 */ 130 "irq 24", /* 24 */ 131 "irq 25", /* 25 */ 132 "irq 26", /* 26 */ 133 "irq 27", /* 27 */ 134 "irq 28", /* 28 */ 135 "irq 29", /* 29 */ 136 "irq 30", /* 30 */ 137 "irq 31", /* 31 */ 138 }; 139 140 void ifpga_intr_dispatch(struct clockframe *frame); 141 142 extern struct ifpga_softc *ifpga_sc; 143 144 static inline uint32_t 145 ifpga_iintsrc_read(void) 146 { 147 return bus_space_read_4(ifpga_sc->sc_iot, ifpga_sc->sc_irq_ioh, 148 IFPGA_INTR_STATUS); 149 } 150 151 static inline void 152 ifpga_enable_irq(int irq) 153 { 154 155 intr_enabled |= (1U << irq); 156 ifpga_set_intrmask(); 157 } 158 159 static inline void 160 ifpga_disable_irq(int irq) 161 { 162 163 intr_enabled &= ~(1U << irq); 164 ifpga_set_intrmask(); 165 } 166 167 /* 168 * NOTE: This routine must be called with interrupts disabled in the CPSR. 169 */ 170 static void 171 ifpga_intr_calculate_masks(void) 172 { 173 struct intrq *iq; 174 struct intrhand *ih; 175 int irq, ipl; 176 177 /* First, figure out which IPLs each IRQ has. */ 178 for (irq = 0; irq < NIRQ; irq++) { 179 int levels = 0; 180 iq = &intrq[irq]; 181 ifpga_disable_irq(irq); 182 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 183 ih = TAILQ_NEXT(ih, ih_list)) 184 levels |= (1U << ih->ih_ipl); 185 iq->iq_levels = levels; 186 } 187 188 /* Next, figure out which IRQs are used by each IPL. */ 189 for (ipl = 0; ipl < NIPL; ipl++) { 190 int irqs = 0; 191 for (irq = 0; irq < NIRQ; irq++) { 192 if (intrq[irq].iq_levels & (1U << ipl)) 193 irqs |= (1U << irq); 194 } 195 ifpga_imask[ipl] = irqs; 196 } 197 198 ifpga_imask[IPL_NONE] = 0; 199 200 /* 201 * Initialize the soft interrupt masks to block themselves. 202 */ 203 ifpga_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 204 ifpga_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 205 ifpga_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 206 ifpga_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 207 208 /* 209 * splsoftclock() is the only interface that users of the 210 * generic software interrupt facility have to block their 211 * soft intrs, so splsoftclock() must also block IPL_SOFT. 212 */ 213 ifpga_imask[IPL_SOFTCLOCK] |= ifpga_imask[IPL_SOFT]; 214 215 /* 216 * splsoftnet() must also block splsoftclock(), since we don't 217 * want timer-driven network events to occur while we're 218 * processing incoming packets. 219 */ 220 ifpga_imask[IPL_SOFTNET] |= ifpga_imask[IPL_SOFTCLOCK]; 221 222 /* 223 * Enforce a hierarchy that gives "slow" device (or devices with 224 * limited input buffer space/"real-time" requirements) a better 225 * chance at not dropping data. 226 */ 227 ifpga_imask[IPL_BIO] |= ifpga_imask[IPL_SOFTNET]; 228 ifpga_imask[IPL_NET] |= ifpga_imask[IPL_BIO]; 229 ifpga_imask[IPL_SOFTSERIAL] |= ifpga_imask[IPL_NET]; 230 ifpga_imask[IPL_TTY] |= ifpga_imask[IPL_SOFTSERIAL]; 231 232 /* 233 * splvm() blocks all interrupts that use the kernel memory 234 * allocation facilities. 235 */ 236 ifpga_imask[IPL_VM] |= ifpga_imask[IPL_TTY]; 237 238 /* 239 * Audio devices are not allowed to perform memory allocation 240 * in their interrupt routines, and they have fairly "real-time" 241 * requirements, so give them a high interrupt priority. 242 */ 243 ifpga_imask[IPL_AUDIO] |= ifpga_imask[IPL_VM]; 244 245 /* 246 * splclock() must block anything that uses the scheduler. 247 */ 248 ifpga_imask[IPL_CLOCK] |= ifpga_imask[IPL_AUDIO]; 249 250 /* 251 * splstatclock() must also block the clock. 252 */ 253 ifpga_imask[IPL_STATCLOCK] |= ifpga_imask[IPL_CLOCK]; 254 255 /* 256 * splhigh() must block "everything". 257 */ 258 ifpga_imask[IPL_HIGH] |= ifpga_imask[IPL_STATCLOCK]; 259 260 /* 261 * XXX We need serial drivers to run at the absolute highest priority 262 * in order to avoid overruns, so serial > high. 263 */ 264 ifpga_imask[IPL_SERIAL] |= ifpga_imask[IPL_HIGH]; 265 266 /* 267 * Now compute which IRQs must be blocked when servicing any 268 * given IRQ. 269 */ 270 for (irq = 0; irq < NIRQ; irq++) { 271 int irqs = (1U << irq); 272 iq = &intrq[irq]; 273 if (TAILQ_FIRST(&iq->iq_list) != NULL) 274 ifpga_enable_irq(irq); 275 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 276 ih = TAILQ_NEXT(ih, ih_list)) 277 irqs |= ifpga_imask[ih->ih_ipl]; 278 iq->iq_mask = irqs; 279 } 280 } 281 282 void 283 ifpga_do_pending(void) 284 { 285 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 286 int new, oldirqstate; 287 288 if (__cpu_simple_lock_try(&processing) == 0) 289 return; 290 291 new = current_spl_level; 292 293 oldirqstate = disable_interrupts(I32_bit); 294 295 #define DO_SOFTINT(si) \ 296 if ((ifpga_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 297 ifpga_ipending &= ~SI_TO_IRQBIT(si); \ 298 current_spl_level |= ifpga_imask[si_to_ipl[(si)]]; \ 299 restore_interrupts(oldirqstate); \ 300 softintr_dispatch(si); \ 301 oldirqstate = disable_interrupts(I32_bit); \ 302 current_spl_level = new; \ 303 } 304 305 DO_SOFTINT(SI_SOFTSERIAL); 306 DO_SOFTINT(SI_SOFTNET); 307 DO_SOFTINT(SI_SOFTCLOCK); 308 DO_SOFTINT(SI_SOFT); 309 310 __cpu_simple_unlock(&processing); 311 312 restore_interrupts(oldirqstate); 313 } 314 315 void 316 splx(int new) 317 { 318 319 ifpga_splx(new); 320 } 321 322 int 323 _spllower(int ipl) 324 { 325 326 return (ifpga_spllower(ipl)); 327 } 328 329 int 330 _splraise(int ipl) 331 { 332 333 return (ifpga_splraise(ipl)); 334 } 335 336 void 337 _setsoftintr(int si) 338 { 339 int oldirqstate; 340 341 oldirqstate = disable_interrupts(I32_bit); 342 ifpga_ipending |= SI_TO_IRQBIT(si); 343 restore_interrupts(oldirqstate); 344 345 /* Process unmasked pending soft interrupts. */ 346 if ((ifpga_ipending & INT_SWMASK) & ~current_spl_level) 347 ifpga_do_pending(); 348 } 349 350 /* 351 * ifpga_intr_init: 352 * 353 * Initialize the rest of the interrupt subsystem, making it 354 * ready to handle interrupts from devices. 355 */ 356 void 357 ifpga_intr_init(void) 358 { 359 struct intrq *iq; 360 int i; 361 362 intr_enabled = 0; 363 364 for (i = 0; i < NIRQ; i++) { 365 iq = &intrq[i]; 366 TAILQ_INIT(&iq->iq_list); 367 368 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 369 NULL, "ifpga", ifpga_irqnames[i]); 370 } 371 } 372 373 void 374 ifpga_intr_postinit(void) 375 { 376 ifpga_intr_calculate_masks(); 377 378 /* Enable IRQs (don't yet use FIQs). */ 379 enable_interrupts(I32_bit); 380 } 381 382 void * 383 ifpga_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 384 { 385 struct intrq *iq; 386 struct intrhand *ih; 387 u_int oldirqstate; 388 389 if (irq < 0 || irq > NIRQ) 390 panic("ifpga_intr_establish: IRQ %d out of range", irq); 391 392 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 393 if (ih == NULL) 394 return (NULL); 395 396 ih->ih_func = func; 397 ih->ih_arg = arg; 398 ih->ih_ipl = ipl; 399 ih->ih_irq = irq; 400 401 iq = &intrq[irq]; 402 403 /* All IOP321 interrupts are level-triggered. */ 404 iq->iq_ist = IST_LEVEL; 405 406 oldirqstate = disable_interrupts(I32_bit); 407 408 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 409 410 ifpga_intr_calculate_masks(); 411 412 restore_interrupts(oldirqstate); 413 414 return (ih); 415 } 416 417 void 418 ifpga_intr_disestablish(void *cookie) 419 { 420 struct intrhand *ih = cookie; 421 struct intrq *iq = &intrq[ih->ih_irq]; 422 int oldirqstate; 423 424 oldirqstate = disable_interrupts(I32_bit); 425 426 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 427 428 ifpga_intr_calculate_masks(); 429 430 restore_interrupts(oldirqstate); 431 } 432 433 void 434 ifpga_intr_dispatch(struct clockframe *frame) 435 { 436 struct intrq *iq; 437 struct intrhand *ih; 438 int oldirqstate, pcpl, irq, ibit, hwpend; 439 440 pcpl = current_spl_level; 441 442 hwpend = ifpga_iintsrc_read(); 443 444 /* 445 * Disable all the interrupts that are pending. We will 446 * reenable them once they are processed and not masked. 447 */ 448 intr_enabled &= ~hwpend; 449 ifpga_set_intrmask(); 450 451 /* Wait for these interrupts to be suppressed. */ 452 while ((ifpga_iintsrc_read() & hwpend) != 0) 453 ; 454 455 while (hwpend != 0) { 456 irq = ffs(hwpend) - 1; 457 ibit = (1U << irq); 458 459 hwpend &= ~ibit; 460 461 if (pcpl & ibit) { 462 /* 463 * IRQ is masked; mark it as pending and check 464 * the next one. Note: the IRQ is already disabled. 465 */ 466 ifpga_ipending |= ibit; 467 continue; 468 } 469 470 ifpga_ipending &= ~ibit; 471 472 iq = &intrq[irq]; 473 iq->iq_ev.ev_count++; 474 uvmexp.intrs++; 475 current_spl_level |= iq->iq_mask; 476 oldirqstate = enable_interrupts(I32_bit); 477 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 478 ih = TAILQ_NEXT(ih, ih_list)) { 479 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 480 } 481 restore_interrupts(oldirqstate); 482 current_spl_level = pcpl; 483 484 hwpend |= (ifpga_ipending & IFPGA_INTR_HWMASK) & ~pcpl; 485 486 /* Re-enable this interrupt now that's it's cleared. */ 487 intr_enabled |= ibit; 488 ifpga_set_intrmask(); 489 } 490 491 /* Check for pendings soft intrs. */ 492 if ((ifpga_ipending & INT_SWMASK) & ~current_spl_level) { 493 oldirqstate = enable_interrupts(I32_bit); 494 ifpga_do_pending(); 495 restore_interrupts(oldirqstate); 496 } 497 } 498
Indexes created Mon Sep 29 03:10:08 GMT 2025