ifpga_intr.c revision 1.7
1 /* $NetBSD: ifpga_intr.c,v 1.7 2008/01/06 01:37:57 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef EVBARM_SPL_NOINLINE 39 #define EVBARM_SPL_NOINLINE 40 #endif 41 42 /* 43 * Interrupt support for the Integrator FPGA. 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/bus.h> 50 #include <sys/intr.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <arm/cpufunc.h> 55 56 #include <evbarm/ifpga/ifpgareg.h> 57 #include <evbarm/ifpga/ifpgavar.h> 58 59 /* Interrupt handler queues. */ 60 struct intrq intrq[NIRQ]; 61 62 /* Interrupts to mask at each level. */ 63 int ifpga_imask[NIPL]; 64 65 /* Current interrupt priority level. */ 66 volatile int current_spl_level; 67 68 /* Interrupts pending. */ 69 volatile int ifpga_ipending; 70 71 /* Software copy of the IRQs we have enabled. */ 72 volatile uint32_t intr_enabled; 73 74 /* Mask if interrupts steered to FIQs. */ 75 uint32_t intr_steer; 76 77 #ifdef __HAVE_FAST_SOFTINTS 78 /* 79 * Map a software interrupt queue index (to the unused bits in the 80 * ICU registers -- XXX will need to revisit this if those bits are 81 * ever used in future steppings). 82 */ 83 static const uint32_t si_to_irqbit[] = { 84 [SI_SOFTCLOCK] = IFPGA_INTR_bit31, 85 [SI_SOFTBIO] = IFPGA_INTR_bit30, 86 [SI_SOFTNET] = IFPGA_INTR_bit29, 87 [SI_SOFTSERIAL] = IFPGA_INTR_bit28, 88 }; 89 90 #define SI_TO_IRQBIT(si) (si_to_irqbit[(si)]) 91 92 /* 93 * Map a software interrupt queue to an interrupt priority level. 94 */ 95 static const int si_to_ipl[] = { 96 [SI_SOFTCLOCK] = IPL_SOFTCLOCK, 97 [SI_SOFTBIO] = IPL_SOFTBIO, 98 [SI_SOFTNET] = IPL_SOFTNET, 99 [SI_SOFTSERIAL] = IPL_SOFTSERIAL, 100 }; 101 #endif 102 103 /* 104 * Interrupt bit names. 105 */ 106 const char * const ifpga_irqnames[] = { 107 "soft", /* 0 */ 108 "uart 0", /* 1 */ 109 "uart 1", /* 2 */ 110 "kbd", /* 3 */ 111 "mouse", /* 4 */ 112 "tmr 0", /* 5 */ 113 "tmr 1 hard", /* 6 */ 114 "tmr 2 stat", /* 7 */ 115 "rtc", /* 8 */ 116 "exp 0", /* 9 */ 117 "exp 1", /* 10 */ 118 "exp 2", /* 11 */ 119 "exp 3", /* 12 */ 120 "pci 0", /* 13 */ 121 "pci 1", /* 14 */ 122 "pci 2", /* 15 */ 123 "pci 3", /* 16 */ 124 "V3 br", /* 17 */ 125 "deg", /* 18 */ 126 "enum", /* 19 */ 127 "pci lb", /* 20 */ 128 "autoPC", /* 21 */ 129 "irq 22", /* 22 */ 130 "irq 23", /* 23 */ 131 "irq 24", /* 24 */ 132 "irq 25", /* 25 */ 133 "irq 26", /* 26 */ 134 "irq 27", /* 27 */ 135 "irq 28", /* 28 */ 136 "irq 29", /* 29 */ 137 "irq 30", /* 30 */ 138 "irq 31", /* 31 */ 139 }; 140 141 void ifpga_intr_dispatch(struct clockframe *frame); 142 143 extern struct ifpga_softc *ifpga_sc; 144 145 static inline uint32_t 146 ifpga_iintsrc_read(void) 147 { 148 return bus_space_read_4(ifpga_sc->sc_iot, ifpga_sc->sc_irq_ioh, 149 IFPGA_INTR_STATUS); 150 } 151 152 static inline void 153 ifpga_enable_irq(int irq) 154 { 155 156 intr_enabled |= (1U << irq); 157 ifpga_set_intrmask(); 158 } 159 160 static inline void 161 ifpga_disable_irq(int irq) 162 { 163 164 intr_enabled &= ~(1U << irq); 165 ifpga_set_intrmask(); 166 } 167 168 /* 169 * NOTE: This routine must be called with interrupts disabled in the CPSR. 170 */ 171 static void 172 ifpga_intr_calculate_masks(void) 173 { 174 struct intrq *iq; 175 struct intrhand *ih; 176 int irq, ipl; 177 178 /* First, figure out which IPLs each IRQ has. */ 179 for (irq = 0; irq < NIRQ; irq++) { 180 int levels = 0; 181 iq = &intrq[irq]; 182 ifpga_disable_irq(irq); 183 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 184 ih = TAILQ_NEXT(ih, ih_list)) 185 levels |= (1U << ih->ih_ipl); 186 iq->iq_levels = levels; 187 } 188 189 /* Next, figure out which IRQs are used by each IPL. */ 190 for (ipl = 0; ipl < NIPL; ipl++) { 191 int irqs = 0; 192 for (irq = 0; irq < NIRQ; irq++) { 193 if (intrq[irq].iq_levels & (1U << ipl)) 194 irqs |= (1U << irq); 195 } 196 ifpga_imask[ipl] = irqs; 197 } 198 199 KASSERT(ifpga_imask[IPL_NONE] == 0); 200 201 #ifdef __HAVE_FAST_SOFTINTS 202 /* 203 * Initialize the soft interrupt masks to block themselves. 204 */ 205 ifpga_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 206 ifpga_imask[IPL_SOFTBIO] = SI_TO_IRQBIT(SI_SOFTBIO); 207 ifpga_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 208 ifpga_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 209 #endif 210 211 /* 212 * Enforce a hierarchy that gives "slow" device (or devices with 213 * limited input buffer space/"real-time" requirements) a better 214 * chance at not dropping data. 215 */ 216 ifpga_imask[IPL_SOFTBIO] |= ifpga_imask[IPL_SOFTCLOCK]; 217 ifpga_imask[IPL_SOFTNET] |= ifpga_imask[IPL_SOFTBIO]; 218 ifpga_imask[IPL_SOFTSERIAL] |= ifpga_imask[IPL_SOFTNET]; 219 ifpga_imask[IPL_VM] |= ifpga_imask[IPL_SOFTSERIAL]; 220 ifpga_imask[IPL_SCHED] |= ifpga_imask[IPL_VM]; 221 ifpga_imask[IPL_HIGH] |= ifpga_imask[IPL_SCHED]; 222 223 /* 224 * Now compute which IRQs must be blocked when servicing any 225 * given IRQ. 226 */ 227 for (irq = 0; irq < NIRQ; irq++) { 228 int irqs = (1U << irq); 229 iq = &intrq[irq]; 230 if (TAILQ_FIRST(&iq->iq_list) != NULL) 231 ifpga_enable_irq(irq); 232 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 233 ih = TAILQ_NEXT(ih, ih_list)) 234 irqs |= ifpga_imask[ih->ih_ipl]; 235 iq->iq_mask = irqs; 236 } 237 } 238 239 #ifdef __HAVE_FAST_SOFTINTS 240 void 241 ifpga_do_pending(void) 242 { 243 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 244 int new, oldirqstate; 245 246 if (__cpu_simple_lock_try(&processing) == 0) 247 return; 248 249 new = current_spl_level; 250 251 oldirqstate = disable_interrupts(I32_bit); 252 253 #define DO_SOFTINT(si) \ 254 if ((ifpga_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 255 ifpga_ipending &= ~SI_TO_IRQBIT(si); \ 256 current_spl_level |= ifpga_imask[si_to_ipl[(si)]]; \ 257 restore_interrupts(oldirqstate); \ 258 softintr_dispatch(si); \ 259 oldirqstate = disable_interrupts(I32_bit); \ 260 current_spl_level = new; \ 261 } 262 263 DO_SOFTINT(SI_SOFTSERIAL); 264 DO_SOFTINT(SI_SOFTNET); 265 DO_SOFTINT(SI_SOFTBIO); 266 DO_SOFTINT(SI_SOFTCLOCK); 267 268 __cpu_simple_unlock(&processing); 269 270 restore_interrupts(oldirqstate); 271 } 272 #endif 273 274 void 275 splx(int new) 276 { 277 278 ifpga_splx(new); 279 } 280 281 int 282 _spllower(int ipl) 283 { 284 285 return (ifpga_spllower(ipl)); 286 } 287 288 int 289 _splraise(int ipl) 290 { 291 292 return (ifpga_splraise(ipl)); 293 } 294 295 #ifdef __HAVE_FAST_SOFTINTS 296 void 297 _setsoftintr(int si) 298 { 299 int oldirqstate; 300 301 oldirqstate = disable_interrupts(I32_bit); 302 ifpga_ipending |= SI_TO_IRQBIT(si); 303 restore_interrupts(oldirqstate); 304 305 /* Process unmasked pending soft interrupts. */ 306 if ((ifpga_ipending & INT_SWMASK) & ~current_spl_level) 307 ifpga_do_pending(); 308 } 309 #endif 310 311 /* 312 * ifpga_intr_init: 313 * 314 * Initialize the rest of the interrupt subsystem, making it 315 * ready to handle interrupts from devices. 316 */ 317 void 318 ifpga_intr_init(void) 319 { 320 struct intrq *iq; 321 int i; 322 323 intr_enabled = 0; 324 325 for (i = 0; i < NIRQ; i++) { 326 iq = &intrq[i]; 327 TAILQ_INIT(&iq->iq_list); 328 329 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 330 NULL, "ifpga", ifpga_irqnames[i]); 331 } 332 } 333 334 void 335 ifpga_intr_postinit(void) 336 { 337 ifpga_intr_calculate_masks(); 338 339 /* Enable IRQs (don't yet use FIQs). */ 340 enable_interrupts(I32_bit); 341 } 342 343 void * 344 ifpga_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 345 { 346 struct intrq *iq; 347 struct intrhand *ih; 348 u_int oldirqstate; 349 350 if (irq < 0 || irq > NIRQ) 351 panic("ifpga_intr_establish: IRQ %d out of range", irq); 352 353 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 354 if (ih == NULL) 355 return (NULL); 356 357 ih->ih_func = func; 358 ih->ih_arg = arg; 359 ih->ih_ipl = ipl; 360 ih->ih_irq = irq; 361 362 iq = &intrq[irq]; 363 364 /* All IOP321 interrupts are level-triggered. */ 365 iq->iq_ist = IST_LEVEL; 366 367 oldirqstate = disable_interrupts(I32_bit); 368 369 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 370 371 ifpga_intr_calculate_masks(); 372 373 restore_interrupts(oldirqstate); 374 375 return (ih); 376 } 377 378 void 379 ifpga_intr_disestablish(void *cookie) 380 { 381 struct intrhand *ih = cookie; 382 struct intrq *iq = &intrq[ih->ih_irq]; 383 int oldirqstate; 384 385 oldirqstate = disable_interrupts(I32_bit); 386 387 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 388 389 ifpga_intr_calculate_masks(); 390 391 restore_interrupts(oldirqstate); 392 } 393 394 void 395 ifpga_intr_dispatch(struct clockframe *frame) 396 { 397 struct intrq *iq; 398 struct intrhand *ih; 399 int oldirqstate, pcpl, irq, ibit, hwpend; 400 struct cpu_info *ci; 401 402 ci = curcpu(); 403 ci->ci_idepth++; 404 405 pcpl = current_spl_level; 406 407 hwpend = ifpga_iintsrc_read(); 408 409 /* 410 * Disable all the interrupts that are pending. We will 411 * reenable them once they are processed and not masked. 412 */ 413 intr_enabled &= ~hwpend; 414 ifpga_set_intrmask(); 415 416 /* Wait for these interrupts to be suppressed. */ 417 while ((ifpga_iintsrc_read() & hwpend) != 0) 418 ; 419 420 while (hwpend != 0) { 421 irq = ffs(hwpend) - 1; 422 ibit = (1U << irq); 423 424 hwpend &= ~ibit; 425 426 if (pcpl & ibit) { 427 /* 428 * IRQ is masked; mark it as pending and check 429 * the next one. Note: the IRQ is already disabled. 430 */ 431 ifpga_ipending |= ibit; 432 continue; 433 } 434 435 ifpga_ipending &= ~ibit; 436 437 iq = &intrq[irq]; 438 iq->iq_ev.ev_count++; 439 uvmexp.intrs++; 440 current_spl_level |= iq->iq_mask; 441 oldirqstate = enable_interrupts(I32_bit); 442 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 443 ih = TAILQ_NEXT(ih, ih_list)) { 444 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 445 } 446 restore_interrupts(oldirqstate); 447 current_spl_level = pcpl; 448 449 hwpend |= (ifpga_ipending & IFPGA_INTR_HWMASK) & ~pcpl; 450 451 /* Re-enable this interrupt now that's it's cleared. */ 452 intr_enabled |= ibit; 453 ifpga_set_intrmask(); 454 } 455 456 ci->ci_idepth--; 457 458 #ifdef __HAVE_FAST_SOFTINTS 459 /* Check for pendings soft intrs. */ 460 if ((ifpga_ipending & INT_SWMASK) & ~current_spl_level) { 461 oldirqstate = enable_interrupts(I32_bit); 462 ifpga_do_pending(); 463 restore_interrupts(oldirqstate); 464 } 465 #endif 466 } 467
Indexes created Mon Sep 29 13:09:55 GMT 2025