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ifpga_intr.c revision 1.8 
      1 /*	$NetBSD: ifpga_intr.c,v 1.8 2008/04/27 18:58:46 matt Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed for the NetBSD Project by
     20  *	Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 #ifndef EVBARM_SPL_NOINLINE
     39 #define	EVBARM_SPL_NOINLINE
     40 #endif
     41 
     42 /*
     43  * Interrupt support for the Integrator FPGA.
     44  */
     45 
     46 #include <sys/param.h>
     47 #include <sys/systm.h>
     48 #include <sys/malloc.h>
     49 #include <sys/bus.h>
     50 #include <sys/intr.h>
     51 
     52 #include <uvm/uvm_extern.h>
     53 
     54 #include <arm/cpufunc.h>
     55 
     56 #include <evbarm/ifpga/ifpgareg.h>
     57 #include <evbarm/ifpga/ifpgavar.h>
     58 
     59 /* Interrupt handler queues. */
     60 struct intrq intrq[NIRQ];
     61 
     62 /* Interrupts to mask at each level. */
     63 int ifpga_imask[NIPL];
     64 
     65 /* Interrupts pending. */
     66 volatile int ifpga_ipending;
     67 
     68 /* Software copy of the IRQs we have enabled. */
     69 volatile uint32_t intr_enabled;
     70 
     71 /* Mask if interrupts steered to FIQs. */
     72 uint32_t intr_steer;
     73 
     74 /*
     75  * Interrupt bit names.
     76  */
     77 const char * const ifpga_irqnames[] = {
     78 	"soft",		/* 0 */
     79 	"uart 0",	/* 1 */
     80 	"uart 1",	/* 2 */
     81 	"kbd",		/* 3 */
     82 	"mouse",	/* 4 */
     83 	"tmr 0",	/* 5 */
     84 	"tmr 1 hard",	/* 6 */
     85 	"tmr 2 stat",	/* 7 */
     86 	"rtc",		/* 8 */
     87 	"exp 0",	/* 9 */
     88 	"exp 1",	/* 10 */
     89 	"exp 2",	/* 11 */
     90 	"exp 3",	/* 12 */
     91 	"pci 0",	/* 13 */
     92 	"pci 1",	/* 14 */
     93 	"pci 2",	/* 15 */
     94 	"pci 3",	/* 16 */
     95 	"V3 br",	/* 17 */
     96 	"deg",		/* 18 */
     97 	"enum",		/* 19 */
     98 	"pci lb",	/* 20 */
     99 	"autoPC",	/* 21 */
    100 	"irq 22",	/* 22 */
    101 	"irq 23",	/* 23 */
    102 	"irq 24",	/* 24 */
    103 	"irq 25",	/* 25 */
    104 	"irq 26",	/* 26 */
    105 	"irq 27",	/* 27 */
    106 	"irq 28",	/* 28 */
    107 	"irq 29",	/* 29 */
    108 	"irq 30",	/* 30 */
    109 	"irq 31",	/* 31 */
    110 };
    111 
    112 void	ifpga_intr_dispatch(struct clockframe *frame);
    113 
    114 extern struct ifpga_softc *ifpga_sc;
    115 
    116 static inline uint32_t
    117 ifpga_iintsrc_read(void)
    118 {
    119 	return bus_space_read_4(ifpga_sc->sc_iot, ifpga_sc->sc_irq_ioh,
    120 	    IFPGA_INTR_STATUS);
    121 }
    122 
    123 static inline void
    124 ifpga_enable_irq(int irq)
    125 {
    126 
    127 	intr_enabled |= (1U << irq);
    128 	ifpga_set_intrmask();
    129 }
    130 
    131 static inline void
    132 ifpga_disable_irq(int irq)
    133 {
    134 
    135 	intr_enabled &= ~(1U << irq);
    136 	ifpga_set_intrmask();
    137 }
    138 
    139 /*
    140  * NOTE: This routine must be called with interrupts disabled in the CPSR.
    141  */
    142 static void
    143 ifpga_intr_calculate_masks(void)
    144 {
    145 	struct intrq *iq;
    146 	struct intrhand *ih;
    147 	int irq, ipl;
    148 
    149 	/* First, figure out which IPLs each IRQ has. */
    150 	for (irq = 0; irq < NIRQ; irq++) {
    151 		int levels = 0;
    152 		iq = &intrq[irq];
    153 		ifpga_disable_irq(irq);
    154 		for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
    155 		     ih = TAILQ_NEXT(ih, ih_list))
    156 			levels |= (1U << ih->ih_ipl);
    157 		iq->iq_levels = levels;
    158 	}
    159 
    160 	/* Next, figure out which IRQs are used by each IPL. */
    161 	for (ipl = 0; ipl < NIPL; ipl++) {
    162 		int irqs = 0;
    163 		for (irq = 0; irq < NIRQ; irq++) {
    164 			if (intrq[irq].iq_levels & (1U << ipl))
    165 				irqs |= (1U << irq);
    166 		}
    167 		ifpga_imask[ipl] = irqs;
    168 	}
    169 
    170 	KASSERT(ifpga_imask[IPL_NONE] == 0);
    171 
    172 	/*
    173 	 * Enforce a hierarchy that gives "slow" device (or devices with
    174 	 * limited input buffer space/"real-time" requirements) a better
    175 	 * chance at not dropping data.
    176 	 */
    177 	ifpga_imask[IPL_VM] |= 0;
    178 	ifpga_imask[IPL_SCHED] |= ifpga_imask[IPL_VM];
    179 	ifpga_imask[IPL_HIGH] |= ifpga_imask[IPL_SCHED];
    180 
    181 	/*
    182 	 * Now compute which IRQs must be blocked when servicing any
    183 	 * given IRQ.
    184 	 */
    185 	for (irq = 0; irq < NIRQ; irq++) {
    186 		int irqs = (1U << irq);
    187 		iq = &intrq[irq];
    188 		if (TAILQ_FIRST(&iq->iq_list) != NULL)
    189 			ifpga_enable_irq(irq);
    190 		for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
    191 		     ih = TAILQ_NEXT(ih, ih_list))
    192 			irqs |= ifpga_imask[ih->ih_ipl];
    193 		iq->iq_mask = irqs;
    194 	}
    195 }
    196 
    197 void
    198 splx(int new)
    199 {
    200 
    201 	ifpga_splx(new);
    202 }
    203 
    204 int
    205 _spllower(int ipl)
    206 {
    207 
    208 	return (ifpga_spllower(ipl));
    209 }
    210 
    211 int
    212 _splraise(int ipl)
    213 {
    214 
    215 	return (ifpga_splraise(ipl));
    216 }
    217 
    218 /*
    219  * ifpga_intr_init:
    220  *
    221  *	Initialize the rest of the interrupt subsystem, making it
    222  *	ready to handle interrupts from devices.
    223  */
    224 void
    225 ifpga_intr_init(void)
    226 {
    227 	struct intrq *iq;
    228 	int i;
    229 
    230 	intr_enabled = 0;
    231 
    232 	for (i = 0; i < NIRQ; i++) {
    233 		iq = &intrq[i];
    234 		TAILQ_INIT(&iq->iq_list);
    235 
    236 		evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
    237 		    NULL, "ifpga", ifpga_irqnames[i]);
    238 	}
    239 }
    240 
    241 void
    242 ifpga_intr_postinit(void)
    243 {
    244 	ifpga_intr_calculate_masks();
    245 
    246 	/* Enable IRQs (don't yet use FIQs). */
    247 	enable_interrupts(I32_bit);
    248 }
    249 
    250 void *
    251 ifpga_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)
    252 {
    253 	struct intrq *iq;
    254 	struct intrhand *ih;
    255 	u_int oldirqstate;
    256 
    257 	if (irq < 0 || irq > NIRQ)
    258 		panic("ifpga_intr_establish: IRQ %d out of range", irq);
    259 
    260 	ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
    261 	if (ih == NULL)
    262 		return (NULL);
    263 
    264 	ih->ih_func = func;
    265 	ih->ih_arg = arg;
    266 	ih->ih_ipl = ipl;
    267 	ih->ih_irq = irq;
    268 
    269 	iq = &intrq[irq];
    270 
    271 	/* All IOP321 interrupts are level-triggered. */
    272 	iq->iq_ist = IST_LEVEL;
    273 
    274 	oldirqstate = disable_interrupts(I32_bit);
    275 
    276 	TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
    277 
    278 	ifpga_intr_calculate_masks();
    279 
    280 	restore_interrupts(oldirqstate);
    281 
    282 	return (ih);
    283 }
    284 
    285 void
    286 ifpga_intr_disestablish(void *cookie)
    287 {
    288 	struct intrhand *ih = cookie;
    289 	struct intrq *iq = &intrq[ih->ih_irq];
    290 	int oldirqstate;
    291 
    292 	oldirqstate = disable_interrupts(I32_bit);
    293 
    294 	TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
    295 
    296 	ifpga_intr_calculate_masks();
    297 
    298 	restore_interrupts(oldirqstate);
    299 }
    300 
    301 void
    302 ifpga_intr_dispatch(struct clockframe *frame)
    303 {
    304 	struct intrq *iq;
    305 	struct intrhand *ih;
    306 	int oldirqstate, pcpl, irq, ibit, hwpend;
    307 	struct cpu_info * const ci = curcpu();
    308 
    309 	pcpl = ci->ci_cpl;
    310 
    311 	hwpend = ifpga_iintsrc_read();
    312 
    313 	/*
    314 	 * Disable all the interrupts that are pending.  We will
    315 	 * reenable them once they are processed and not masked.
    316 	 */
    317 	intr_enabled &= ~hwpend;
    318 	ifpga_set_intrmask();
    319 
    320 	/* Wait for these interrupts to be suppressed.  */
    321 	while ((ifpga_iintsrc_read() & hwpend) != 0)
    322 	    ;
    323 
    324 	while (hwpend != 0) {
    325 		irq = ffs(hwpend) - 1;
    326 		ibit = (1U << irq);
    327 
    328 		hwpend &= ~ibit;
    329 
    330 		if (pcpl & ibit) {
    331 			/*
    332 			 * IRQ is masked; mark it as pending and check
    333 			 * the next one.  Note: the IRQ is already disabled.
    334 			 */
    335 			ifpga_ipending |= ibit;
    336 			continue;
    337 		}
    338 
    339 		ifpga_ipending &= ~ibit;
    340 
    341 		iq = &intrq[irq];
    342 		iq->iq_ev.ev_count++;
    343 		uvmexp.intrs++;
    344 		ci->ci_cpl |= iq->iq_mask;
    345 		oldirqstate = enable_interrupts(I32_bit);
    346 		for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
    347 		     ih = TAILQ_NEXT(ih, ih_list)) {
    348 			(void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
    349 		}
    350 		restore_interrupts(oldirqstate);
    351 		ci->ci_cpl = pcpl;
    352 
    353 		hwpend |= (ifpga_ipending & IFPGA_INTR_HWMASK) & ~pcpl;
    354 
    355 		/* Re-enable this interrupt now that's it's cleared. */
    356 		intr_enabled |= ibit;
    357 		ifpga_set_intrmask();
    358 	}
    359 
    360 #ifdef __HAVE_FAST_SOFTINTS
    361 	cpu_dosoftints();
    362 #endif
    363 }
    364