ifpga_pci.c revision 1.1.2.5
1 1.1.2.5 nathanw /* $NetBSD: ifpga_pci.c,v 1.1.2.5 2002/10/18 02:36:28 nathanw Exp $ */ 2 1.1.2.2 nathanw 3 1.1.2.2 nathanw /* 4 1.1.2.2 nathanw * Copyright (c) 2001 ARM Ltd 5 1.1.2.2 nathanw * All rights reserved. 6 1.1.2.2 nathanw * 7 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 9 1.1.2.2 nathanw * are met: 10 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 15 1.1.2.2 nathanw * 3. The name of the company may not be used to endorse or promote 16 1.1.2.2 nathanw * products derived from this software without specific prior written 17 1.1.2.2 nathanw * permission. 18 1.1.2.2 nathanw * 19 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 1.1.2.2 nathanw * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 1.1.2.2 nathanw * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 1.1.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 1.1.2.2 nathanw * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 1.1.2.2 nathanw * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 1.1.2.2 nathanw * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 1.1.2.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 1.1.2.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 1.1.2.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 1.1.2.2 nathanw * SUCH DAMAGE. 30 1.1.2.2 nathanw * 31 1.1.2.2 nathanw * Copyright (c) 1997,1998 Mark Brinicombe. 32 1.1.2.2 nathanw * Copyright (c) 1997,1998 Causality Limited 33 1.1.2.2 nathanw * All rights reserved. 34 1.1.2.2 nathanw * 35 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 36 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 37 1.1.2.2 nathanw * are met: 38 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 39 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 40 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 41 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 42 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 43 1.1.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 44 1.1.2.2 nathanw * must display the following acknowledgement: 45 1.1.2.2 nathanw * This product includes software developed by Mark Brinicombe 46 1.1.2.2 nathanw * for the NetBSD Project. 47 1.1.2.2 nathanw * 4. The name of the company nor the name of the author may be used to 48 1.1.2.2 nathanw * endorse or promote products derived from this software without specific 49 1.1.2.2 nathanw * prior written permission. 50 1.1.2.2 nathanw * 51 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 52 1.1.2.2 nathanw * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 53 1.1.2.2 nathanw * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 1.1.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 55 1.1.2.2 nathanw * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 1.1.2.2 nathanw * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 1.1.2.2 nathanw * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 1.1.2.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 1.1.2.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 1.1.2.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 1.1.2.2 nathanw * SUCH DAMAGE. 62 1.1.2.2 nathanw */ 63 1.1.2.2 nathanw 64 1.1.2.2 nathanw #include <sys/param.h> 65 1.1.2.2 nathanw #include <sys/systm.h> 66 1.1.2.2 nathanw #include <sys/conf.h> 67 1.1.2.2 nathanw #include <sys/malloc.h> 68 1.1.2.2 nathanw #include <sys/device.h> 69 1.1.2.2 nathanw 70 1.1.2.2 nathanw #define _ARM32_BUS_DMA_PRIVATE 71 1.1.2.2 nathanw #include <evbarm/integrator/int_bus_dma.h> 72 1.1.2.2 nathanw 73 1.1.2.2 nathanw #include <machine/intr.h> 74 1.1.2.2 nathanw #include <evbarm/ifpga/irqhandler.h> /* XXX XXX XXX */ 75 1.1.2.2 nathanw 76 1.1.2.2 nathanw #include <dev/pci/pcireg.h> 77 1.1.2.2 nathanw #include <dev/pci/pcivar.h> 78 1.1.2.2 nathanw 79 1.1.2.2 nathanw #include <evbarm/ifpga/ifpgareg.h> 80 1.1.2.2 nathanw #include <evbarm/ifpga/ifpgamem.h> 81 1.1.2.2 nathanw #include <evbarm/ifpga/ifpga_pcivar.h> 82 1.1.2.2 nathanw #include <evbarm/dev/v360reg.h> 83 1.1.2.2 nathanw 84 1.1.2.2 nathanw 85 1.1.2.2 nathanw void ifpga_pci_attach_hook (struct device *, struct device *, 86 1.1.2.2 nathanw struct pcibus_attach_args *); 87 1.1.2.2 nathanw int ifpga_pci_bus_maxdevs (void *, int); 88 1.1.2.2 nathanw pcitag_t ifpga_pci_make_tag (void *, int, int, int); 89 1.1.2.2 nathanw void ifpga_pci_decompose_tag (void *, pcitag_t, int *, int *, 90 1.1.2.2 nathanw int *); 91 1.1.2.2 nathanw pcireg_t ifpga_pci_conf_read (void *, pcitag_t, int); 92 1.1.2.2 nathanw void ifpga_pci_conf_write (void *, pcitag_t, int, pcireg_t); 93 1.1.2.2 nathanw int ifpga_pci_intr_map (struct pci_attach_args *, 94 1.1.2.2 nathanw pci_intr_handle_t *); 95 1.1.2.2 nathanw const char *ifpga_pci_intr_string (void *, pci_intr_handle_t); 96 1.1.2.2 nathanw const struct evcnt *ifpga_pci_intr_evcnt (void *, pci_intr_handle_t); 97 1.1.2.2 nathanw void *ifpga_pci_intr_establish (void *, pci_intr_handle_t, int, 98 1.1.2.2 nathanw int (*)(void *), void *); 99 1.1.2.2 nathanw void ifpga_pci_intr_disestablish (void *, void *); 100 1.1.2.2 nathanw 101 1.1.2.2 nathanw struct arm32_pci_chipset ifpga_pci_chipset = { 102 1.1.2.2 nathanw NULL, /* conf_v */ 103 1.1.2.2 nathanw ifpga_pci_attach_hook, 104 1.1.2.2 nathanw ifpga_pci_bus_maxdevs, 105 1.1.2.2 nathanw ifpga_pci_make_tag, 106 1.1.2.2 nathanw ifpga_pci_decompose_tag, 107 1.1.2.2 nathanw ifpga_pci_conf_read, 108 1.1.2.2 nathanw ifpga_pci_conf_write, 109 1.1.2.2 nathanw NULL, /* intr_v */ 110 1.1.2.2 nathanw ifpga_pci_intr_map, 111 1.1.2.2 nathanw ifpga_pci_intr_string, 112 1.1.2.2 nathanw ifpga_pci_intr_evcnt, 113 1.1.2.2 nathanw ifpga_pci_intr_establish, 114 1.1.2.2 nathanw ifpga_pci_intr_disestablish 115 1.1.2.2 nathanw }; 116 1.1.2.2 nathanw 117 1.1.2.2 nathanw /* 118 1.1.2.2 nathanw * Use the integrator-specific bus_dma routines. 119 1.1.2.2 nathanw */ 120 1.1.2.2 nathanw struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag = { 121 1.1.2.2 nathanw 0, 122 1.1.2.2 nathanw 0, 123 1.1.2.2 nathanw _bus_dmamap_create, 124 1.1.2.2 nathanw _bus_dmamap_destroy, 125 1.1.2.3 nathanw _bus_dmamap_load, 126 1.1.2.3 nathanw _bus_dmamap_load_mbuf, 127 1.1.2.3 nathanw _bus_dmamap_load_uio, 128 1.1.2.2 nathanw _bus_dmamap_load_raw, 129 1.1.2.2 nathanw _bus_dmamap_unload, 130 1.1.2.4 thorpej _bus_dmamap_sync, /* pre */ 131 1.1.2.4 thorpej NULL, /* post */ 132 1.1.2.3 nathanw _bus_dmamem_alloc, 133 1.1.2.3 nathanw _bus_dmamem_free, 134 1.1.2.3 nathanw _bus_dmamem_map, 135 1.1.2.2 nathanw _bus_dmamem_unmap, 136 1.1.2.3 nathanw _bus_dmamem_mmap, 137 1.1.2.2 nathanw }; 138 1.1.2.2 nathanw 139 1.1.2.2 nathanw /* 140 1.1.2.2 nathanw * Currently we only support 12 devices as we select directly in the 141 1.1.2.2 nathanw * type 0 config cycle 142 1.1.2.2 nathanw * (See conf_{read,write} for more detail 143 1.1.2.2 nathanw */ 144 1.1.2.2 nathanw #define MAX_PCI_DEVICES 21 145 1.1.2.2 nathanw 146 1.1.2.2 nathanw /*static int 147 1.1.2.2 nathanw pci_intr(void *arg) 148 1.1.2.2 nathanw { 149 1.1.2.2 nathanw printf("pci int %x\n", (int)arg); 150 1.1.2.2 nathanw return 0; 151 1.1.2.2 nathanw }*/ 152 1.1.2.2 nathanw 153 1.1.2.2 nathanw 154 1.1.2.2 nathanw void 155 1.1.2.2 nathanw ifpga_pci_attach_hook(struct device *parent, struct device *self, 156 1.1.2.2 nathanw struct pcibus_attach_args *pba) 157 1.1.2.2 nathanw { 158 1.1.2.2 nathanw #ifdef PCI_DEBUG 159 1.1.2.2 nathanw printf("ifpga_pci_attach_hook()\n"); 160 1.1.2.2 nathanw #endif 161 1.1.2.2 nathanw } 162 1.1.2.2 nathanw 163 1.1.2.2 nathanw int 164 1.1.2.2 nathanw ifpga_pci_bus_maxdevs(void *pcv, int busno) 165 1.1.2.2 nathanw { 166 1.1.2.2 nathanw #ifdef PCI_DEBUG 167 1.1.2.2 nathanw printf("ifpga_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 168 1.1.2.2 nathanw #endif 169 1.1.2.2 nathanw return MAX_PCI_DEVICES; 170 1.1.2.2 nathanw } 171 1.1.2.2 nathanw 172 1.1.2.2 nathanw pcitag_t 173 1.1.2.2 nathanw ifpga_pci_make_tag(void *pcv, int bus, int device, int function) 174 1.1.2.2 nathanw { 175 1.1.2.2 nathanw #ifdef PCI_DEBUG 176 1.1.2.2 nathanw printf("ifpga_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 177 1.1.2.2 nathanw pcv, bus, device, function); 178 1.1.2.2 nathanw #endif 179 1.1.2.2 nathanw return (bus << 16) | (device << 11) | (function << 8); 180 1.1.2.2 nathanw } 181 1.1.2.2 nathanw 182 1.1.2.2 nathanw void 183 1.1.2.2 nathanw ifpga_pci_decompose_tag(void *pcv, pcitag_t tag, int *busp, int *devicep, 184 1.1.2.2 nathanw int *functionp) 185 1.1.2.2 nathanw { 186 1.1.2.2 nathanw #ifdef PCI_DEBUG 187 1.1.2.2 nathanw printf("ifpga_pci_decompose_tag(pcv=%p, tag=0x%08lx, bp=%p, dp=%p, " 188 1.1.2.2 nathanw "fp=%p)\n", pcv, tag, busp, devicep, functionp); 189 1.1.2.2 nathanw #endif 190 1.1.2.2 nathanw 191 1.1.2.2 nathanw if (busp != NULL) 192 1.1.2.2 nathanw *busp = (tag >> 16) & 0xff; 193 1.1.2.2 nathanw if (devicep != NULL) 194 1.1.2.2 nathanw *devicep = (tag >> 11) & 0x1f; 195 1.1.2.2 nathanw if (functionp != NULL) 196 1.1.2.2 nathanw *functionp = (tag >> 8) & 0x7; 197 1.1.2.2 nathanw } 198 1.1.2.2 nathanw 199 1.1.2.2 nathanw pcireg_t 200 1.1.2.2 nathanw ifpga_pci_conf_read(void *pcv, pcitag_t tag, int reg) 201 1.1.2.2 nathanw { 202 1.1.2.2 nathanw pcireg_t data; 203 1.1.2.2 nathanw struct ifpga_pci_softc *sc = (struct ifpga_pci_softc *)pcv; 204 1.1.2.2 nathanw int bus, device, function; 205 1.1.2.2 nathanw u_int address; 206 1.1.2.2 nathanw 207 1.1.2.2 nathanw ifpga_pci_decompose_tag(pcv, tag, &bus, &device, &function); 208 1.1.2.2 nathanw 209 1.1.2.2 nathanw /* Reset the appertures so that we can talk to the register space. */ 210 1.1.2.2 nathanw bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0, 211 1.1.2.2 nathanw IFPGA_PCI_APP0_512MB_BASE); 212 1.1.2.2 nathanw bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1, 213 1.1.2.2 nathanw IFPGA_PCI_APP1_CONF_BASE); 214 1.1.2.2 nathanw 215 1.1.2.2 nathanw if (bus == 0) { 216 1.1.2.2 nathanw address = (1 << (device + 11)) | reg; 217 1.1.2.2 nathanw bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 218 1.1.2.2 nathanw IFPGA_PCI_APP1_CONF_T0_MAP | ((address >> 16) & 0xff00)); 219 1.1.2.2 nathanw 220 1.1.2.2 nathanw /* Read the value from the bus... */ 221 1.1.2.2 nathanw data = bus_space_read_4(sc->sc_iot, sc->sc_conf_ioh, 222 1.1.2.2 nathanw address & 0x00ffffff); 223 1.1.2.2 nathanw 224 1.1.2.2 nathanw } else { 225 1.1.2.2 nathanw bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 226 1.1.2.2 nathanw IFPGA_PCI_APP1_CONF_T1_MAP); 227 1.1.2.2 nathanw 228 1.1.2.2 nathanw /* Read the value from the bus... */ 229 1.1.2.2 nathanw data = bus_space_read_4(sc->sc_iot, sc->sc_conf_ioh, 230 1.1.2.2 nathanw tag | reg); 231 1.1.2.2 nathanw } 232 1.1.2.2 nathanw /* ... and put the memory spaces back again. */ 233 1.1.2.2 nathanw 234 1.1.2.2 nathanw bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1, 235 1.1.2.2 nathanw IFPGA_PCI_APP1_256MB_BASE); 236 1.1.2.2 nathanw bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 237 1.1.2.2 nathanw IFPGA_PCI_APP1_256MB_MAP); 238 1.1.2.2 nathanw bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0, 239 1.1.2.2 nathanw IFPGA_PCI_APP0_256MB_BASE); 240 1.1.2.2 nathanw #ifdef PCI_DEBUG 241 1.1.2.2 nathanw printf("ifpga_pci_conf_read(pcv=%p tag=0x%08lx reg=0x%02x)=0x%08x\n", 242 1.1.2.2 nathanw pcv, tag, reg, data); 243 1.1.2.2 nathanw #endif 244 1.1.2.2 nathanw return data; 245 1.1.2.2 nathanw } 246 1.1.2.2 nathanw 247 1.1.2.2 nathanw void 248 1.1.2.2 nathanw ifpga_pci_conf_write(void *pcv, pcitag_t tag, int reg, pcireg_t data) 249 1.1.2.2 nathanw { 250 1.1.2.2 nathanw struct ifpga_pci_softc *sc = (struct ifpga_pci_softc *)pcv; 251 1.1.2.2 nathanw int bus, device, function; 252 1.1.2.2 nathanw u_int address; 253 1.1.2.2 nathanw 254 1.1.2.2 nathanw #ifdef PCI_DEBUG 255 1.1.2.2 nathanw printf("ifpga_pci_conf_write(pcv=%p tag=0x%08lx reg=0x%02x, 0x%08x)\n", 256 1.1.2.2 nathanw pcv, tag, reg, data); 257 1.1.2.2 nathanw #endif 258 1.1.2.2 nathanw 259 1.1.2.2 nathanw ifpga_pci_decompose_tag(pcv, tag, &bus, &device, &function); 260 1.1.2.2 nathanw 261 1.1.2.2 nathanw /* Reset the appertures so that we can talk to the register space. */ 262 1.1.2.2 nathanw bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0, 263 1.1.2.2 nathanw IFPGA_PCI_APP0_512MB_BASE); 264 1.1.2.2 nathanw bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1, 265 1.1.2.2 nathanw IFPGA_PCI_APP1_CONF_BASE); 266 1.1.2.2 nathanw 267 1.1.2.2 nathanw if (bus == 0) { 268 1.1.2.2 nathanw address = (1 << (device + 11)) | reg; 269 1.1.2.2 nathanw bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 270 1.1.2.2 nathanw IFPGA_PCI_APP1_CONF_T0_MAP | ((address >> 16) & 0xff00)); 271 1.1.2.2 nathanw 272 1.1.2.2 nathanw /* Read the value from the bus... */ 273 1.1.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh, 274 1.1.2.2 nathanw address & 0x00ffffff, data); 275 1.1.2.2 nathanw 276 1.1.2.2 nathanw } else { 277 1.1.2.2 nathanw bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 278 1.1.2.2 nathanw IFPGA_PCI_APP1_CONF_T1_MAP); 279 1.1.2.2 nathanw 280 1.1.2.2 nathanw /* Read the value from the bus... */ 281 1.1.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh, tag | reg, 282 1.1.2.2 nathanw data); 283 1.1.2.2 nathanw } 284 1.1.2.2 nathanw /* ... and put the memory spaces back again. */ 285 1.1.2.2 nathanw 286 1.1.2.2 nathanw bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1, 287 1.1.2.2 nathanw IFPGA_PCI_APP1_256MB_BASE); 288 1.1.2.2 nathanw bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 289 1.1.2.2 nathanw IFPGA_PCI_APP1_256MB_MAP); 290 1.1.2.2 nathanw bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0, 291 1.1.2.2 nathanw IFPGA_PCI_APP0_256MB_BASE); 292 1.1.2.2 nathanw } 293 1.1.2.2 nathanw 294 1.1.2.2 nathanw int 295 1.1.2.2 nathanw ifpga_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 296 1.1.2.2 nathanw { 297 1.1.2.2 nathanw int line = pa->pa_intrline; 298 1.1.2.2 nathanw 299 1.1.2.2 nathanw #ifdef PCI_DEBUG 300 1.1.2.2 nathanw int pin = pa->pa_intrpin; 301 1.1.2.2 nathanw void *pcv = pa->pa_pc; 302 1.1.2.2 nathanw pcitag_t intrtag = pa->pa_intrtag; 303 1.1.2.2 nathanw int bus, device, function; 304 1.1.2.2 nathanw 305 1.1.2.2 nathanw ifpga_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 306 1.1.2.2 nathanw printf("ifpga_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d " 307 1.1.2.2 nathanw "dev=%d\n", pcv, intrtag, pin, line, device); 308 1.1.2.2 nathanw #endif 309 1.1.2.2 nathanw 310 1.1.2.2 nathanw 311 1.1.2.2 nathanw #ifdef PCI_DEBUG 312 1.1.2.2 nathanw printf("pin %d, line %d mapped to int %d\n", pin, line, line); 313 1.1.2.2 nathanw #endif 314 1.1.2.2 nathanw 315 1.1.2.2 nathanw *ihp = line; 316 1.1.2.2 nathanw return 0; 317 1.1.2.2 nathanw } 318 1.1.2.2 nathanw 319 1.1.2.2 nathanw const char * 320 1.1.2.2 nathanw ifpga_pci_intr_string(void *pcv, pci_intr_handle_t ih) 321 1.1.2.2 nathanw { 322 1.1.2.2 nathanw static char irqstr[12]; /* 6 + 1 + NULL + sanity */ 323 1.1.2.2 nathanw 324 1.1.2.2 nathanw #ifdef PCI_DEBUG 325 1.1.2.2 nathanw printf("ifpga_pci_intr_string(pcv=0x%p, ih=0x%lx)\n", pcv, ih); 326 1.1.2.2 nathanw #endif 327 1.1.2.2 nathanw if (ih == 0) 328 1.1.2.5 nathanw panic("ifpga_pci_intr_string: bogus handle 0x%lx", ih); 329 1.1.2.2 nathanw 330 1.1.2.2 nathanw sprintf(irqstr, "pciint%ld", ih - IFPGA_INTRNUM_PCIINT0); 331 1.1.2.2 nathanw return irqstr; 332 1.1.2.2 nathanw } 333 1.1.2.2 nathanw 334 1.1.2.2 nathanw const struct evcnt * 335 1.1.2.2 nathanw ifpga_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih) 336 1.1.2.2 nathanw { 337 1.1.2.2 nathanw 338 1.1.2.2 nathanw /* XXX for now, no evcnt parent reported */ 339 1.1.2.2 nathanw return NULL; 340 1.1.2.2 nathanw } 341 1.1.2.2 nathanw 342 1.1.2.2 nathanw void * 343 1.1.2.2 nathanw ifpga_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level, 344 1.1.2.2 nathanw int (*func) (void *), void *arg) 345 1.1.2.2 nathanw { 346 1.1.2.2 nathanw void *intr; 347 1.1.2.2 nathanw int length; 348 1.1.2.2 nathanw char *string; 349 1.1.2.2 nathanw 350 1.1.2.2 nathanw #ifdef PCI_DEBUG 351 1.1.2.2 nathanw printf("ifpga_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, " 352 1.1.2.2 nathanw "func=%p, arg=%p)\n", pcv, ih, level, func, arg); 353 1.1.2.2 nathanw #endif 354 1.1.2.2 nathanw 355 1.1.2.2 nathanw /* Copy the interrupt string to a private buffer */ 356 1.1.2.2 nathanw length = strlen(ifpga_pci_intr_string(pcv, ih)); 357 1.1.2.2 nathanw string = malloc(length + 1, M_DEVBUF, M_WAITOK); 358 1.1.2.2 nathanw strcpy(string, ifpga_pci_intr_string(pcv, ih)); 359 1.1.2.2 nathanw intr = intr_claim(ih, level, string, func, arg); 360 1.1.2.2 nathanw 361 1.1.2.2 nathanw return intr; 362 1.1.2.2 nathanw } 363 1.1.2.2 nathanw 364 1.1.2.2 nathanw void 365 1.1.2.2 nathanw ifpga_pci_intr_disestablish(void *pcv, void *cookie) 366 1.1.2.2 nathanw { 367 1.1.2.2 nathanw #ifdef PCI_DEBUG 368 1.1.2.2 nathanw printf("ifpga_pci_intr_disestablish(pcv=%p, cookie=%p)\n", 369 1.1.2.2 nathanw pcv, cookie); 370 1.1.2.2 nathanw #endif 371 1.1.2.2 nathanw /* XXXX Need to free the string */ 372 1.1.2.2 nathanw 373 1.1.2.2 nathanw intr_release(cookie); 374 1.1.2.2 nathanw } 375
Indexes created Wed Oct 22 13:09:56 GMT 2025