ifpga_pci.c revision 1.15.2.1
1 /* $NetBSD: ifpga_pci.c,v 1.15.2.1 2014/08/20 00:02:54 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * Copyright (c) 1997,1998 Mark Brinicombe. 32 * Copyright (c) 1997,1998 Causality Limited 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Mark Brinicombe 46 * for the NetBSD Project. 47 * 4. The name of the company nor the name of the author may be used to 48 * endorse or promote products derived from this software without specific 49 * prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 52 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 53 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 */ 63 64 #define _ARM32_BUS_DMA_PRIVATE 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: ifpga_pci.c,v 1.15.2.1 2014/08/20 00:02:54 tls Exp $"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/conf.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 75 #include <evbarm/integrator/int_bus_dma.h> 76 77 #include <machine/intr.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 82 #include <evbarm/ifpga/ifpgareg.h> 83 #include <evbarm/ifpga/ifpgamem.h> 84 #include <evbarm/ifpga/ifpga_pcivar.h> 85 #include <evbarm/dev/v360reg.h> 86 87 88 void ifpga_pci_attach_hook (device_t, device_t, 89 struct pcibus_attach_args *); 90 int ifpga_pci_bus_maxdevs (void *, int); 91 pcitag_t ifpga_pci_make_tag (void *, int, int, int); 92 void ifpga_pci_decompose_tag (void *, pcitag_t, int *, int *, 93 int *); 94 pcireg_t ifpga_pci_conf_read (void *, pcitag_t, int); 95 void ifpga_pci_conf_write (void *, pcitag_t, int, pcireg_t); 96 int ifpga_pci_intr_map (const struct pci_attach_args *, 97 pci_intr_handle_t *); 98 const char *ifpga_pci_intr_string (void *, pci_intr_handle_t, char *, size_t); 99 const struct evcnt *ifpga_pci_intr_evcnt (void *, pci_intr_handle_t); 100 void *ifpga_pci_intr_establish (void *, pci_intr_handle_t, int, 101 int (*)(void *), void *); 102 void ifpga_pci_intr_disestablish (void *, void *); 103 104 struct arm32_pci_chipset ifpga_pci_chipset = { 105 NULL, /* conf_v */ 106 ifpga_pci_attach_hook, 107 ifpga_pci_bus_maxdevs, 108 ifpga_pci_make_tag, 109 ifpga_pci_decompose_tag, 110 ifpga_pci_conf_read, 111 ifpga_pci_conf_write, 112 NULL, /* intr_v */ 113 ifpga_pci_intr_map, 114 ifpga_pci_intr_string, 115 ifpga_pci_intr_evcnt, 116 ifpga_pci_intr_establish, 117 ifpga_pci_intr_disestablish, 118 #ifdef __HAVE_PCI_CONF_HOOK 119 NULL, 120 #endif 121 ifpga_pci_conf_interrupt, 122 }; 123 124 /* 125 * Use the integrator-specific bus_dma routines. 126 */ 127 struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag = { 128 0, 129 0, 130 NULL, 131 _bus_dmamap_create, 132 _bus_dmamap_destroy, 133 _bus_dmamap_load, 134 _bus_dmamap_load_mbuf, 135 _bus_dmamap_load_uio, 136 _bus_dmamap_load_raw, 137 _bus_dmamap_unload, 138 _bus_dmamap_sync, /* pre */ 139 NULL, /* post */ 140 _bus_dmamem_alloc, 141 _bus_dmamem_free, 142 _bus_dmamem_map, 143 _bus_dmamem_unmap, 144 _bus_dmamem_mmap, 145 }; 146 147 /* 148 * Currently we only support 12 devices as we select directly in the 149 * type 0 config cycle 150 * (See conf_{read,write} for more detail 151 */ 152 #define MAX_PCI_DEVICES 21 153 154 /*static int 155 pci_intr(void *arg) 156 { 157 printf("pci int %x\n", (int)arg); 158 return 0; 159 }*/ 160 161 162 void 163 ifpga_pci_attach_hook(device_t parent, device_t self, 164 struct pcibus_attach_args *pba) 165 { 166 #ifdef PCI_DEBUG 167 printf("ifpga_pci_attach_hook()\n"); 168 #endif 169 } 170 171 int 172 ifpga_pci_bus_maxdevs(void *pcv, int busno) 173 { 174 #ifdef PCI_DEBUG 175 printf("ifpga_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 176 #endif 177 return MAX_PCI_DEVICES; 178 } 179 180 pcitag_t 181 ifpga_pci_make_tag(void *pcv, int bus, int device, int function) 182 { 183 #ifdef PCI_DEBUG 184 printf("ifpga_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 185 pcv, bus, device, function); 186 #endif 187 return (bus << 16) | (device << 11) | (function << 8); 188 } 189 190 void 191 ifpga_pci_decompose_tag(void *pcv, pcitag_t tag, int *busp, int *devicep, 192 int *functionp) 193 { 194 #ifdef PCI_DEBUG 195 printf("ifpga_pci_decompose_tag(pcv=%p, tag=0x%08lx, bp=%p, dp=%p, " 196 "fp=%p)\n", pcv, tag, busp, devicep, functionp); 197 #endif 198 199 if (busp != NULL) 200 *busp = (tag >> 16) & 0xff; 201 if (devicep != NULL) 202 *devicep = (tag >> 11) & 0x1f; 203 if (functionp != NULL) 204 *functionp = (tag >> 8) & 0x7; 205 } 206 207 pcireg_t 208 ifpga_pci_conf_read(void *pcv, pcitag_t tag, int reg) 209 { 210 pcireg_t data; 211 struct ifpga_pci_softc *sc = (struct ifpga_pci_softc *)pcv; 212 int bus, device, function; 213 u_int address; 214 215 ifpga_pci_decompose_tag(pcv, tag, &bus, &device, &function); 216 217 /* Reset the appertures so that we can talk to the register space. */ 218 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0, 219 IFPGA_PCI_APP0_512MB_BASE); 220 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1, 221 IFPGA_PCI_APP1_CONF_BASE); 222 223 if (bus == 0) { 224 address = (1 << (device + 11)) | reg; 225 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 226 IFPGA_PCI_APP1_CONF_T0_MAP | ((address >> 16) & 0xff00)); 227 228 /* Read the value from the bus... */ 229 data = bus_space_read_4(sc->sc_iot, sc->sc_conf_ioh, 230 address & 0x00ffffff); 231 232 } else { 233 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 234 IFPGA_PCI_APP1_CONF_T1_MAP); 235 236 /* Read the value from the bus... */ 237 data = bus_space_read_4(sc->sc_iot, sc->sc_conf_ioh, 238 tag | reg); 239 } 240 /* ... and put the memory spaces back again. */ 241 242 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1, 243 IFPGA_PCI_APP1_256MB_BASE); 244 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 245 IFPGA_PCI_APP1_256MB_MAP); 246 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0, 247 IFPGA_PCI_APP0_256MB_BASE); 248 #ifdef PCI_DEBUG 249 printf("ifpga_pci_conf_read(pcv=%p tag=0x%08lx reg=0x%02x)=0x%08x\n", 250 pcv, tag, reg, data); 251 #endif 252 return data; 253 } 254 255 void 256 ifpga_pci_conf_write(void *pcv, pcitag_t tag, int reg, pcireg_t data) 257 { 258 struct ifpga_pci_softc *sc = (struct ifpga_pci_softc *)pcv; 259 int bus, device, function; 260 u_int address; 261 262 #ifdef PCI_DEBUG 263 printf("ifpga_pci_conf_write(pcv=%p tag=0x%08lx reg=0x%02x, 0x%08x)\n", 264 pcv, tag, reg, data); 265 #endif 266 267 ifpga_pci_decompose_tag(pcv, tag, &bus, &device, &function); 268 269 /* Reset the appertures so that we can talk to the register space. */ 270 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0, 271 IFPGA_PCI_APP0_512MB_BASE); 272 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1, 273 IFPGA_PCI_APP1_CONF_BASE); 274 275 if (bus == 0) { 276 address = (1 << (device + 11)) | reg; 277 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 278 IFPGA_PCI_APP1_CONF_T0_MAP | ((address >> 16) & 0xff00)); 279 280 /* Write the value to the bus... */ 281 bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh, 282 address & 0x00ffffff, data); 283 284 } else { 285 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 286 IFPGA_PCI_APP1_CONF_T1_MAP); 287 288 /* Write the value to the bus... */ 289 bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh, tag | reg, 290 data); 291 } 292 /* ... and put the memory spaces back again. */ 293 294 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1, 295 IFPGA_PCI_APP1_256MB_BASE); 296 bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1, 297 IFPGA_PCI_APP1_256MB_MAP); 298 bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0, 299 IFPGA_PCI_APP0_256MB_BASE); 300 } 301 302 int 303 ifpga_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 304 { 305 int line = pa->pa_intrline; 306 307 #ifdef PCI_DEBUG 308 int pin = pa->pa_intrpin; 309 void *pcv = pa->pa_pc; 310 pcitag_t intrtag = pa->pa_intrtag; 311 int bus, device, function; 312 313 ifpga_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 314 printf("ifpga_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d " 315 "dev=%d\n", pcv, intrtag, pin, line, device); 316 #endif 317 318 319 #ifdef PCI_DEBUG 320 printf("pin %d, line %d mapped to int %d\n", pin, line, line); 321 #endif 322 323 *ihp = line; 324 return 0; 325 } 326 327 const char * 328 ifpga_pci_intr_string(void *pcv, pci_intr_handle_t ih, char *buf, size_t len) 329 { 330 #ifdef PCI_DEBUG 331 printf("ifpga_pci_intr_string(pcv=%p, ih=0x%lx)\n", pcv, ih); 332 #endif 333 if (ih == 0) 334 panic("ifpga_pci_intr_string: bogus handle 0x%lx", ih); 335 336 snprintf(buf, len, "pciint%ld", ih - IFPGA_INTRNUM_PCIINT0); 337 return buf; 338 } 339 340 const struct evcnt * 341 ifpga_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih) 342 { 343 344 /* XXX for now, no evcnt parent reported */ 345 return NULL; 346 } 347 348 void * 349 ifpga_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level, 350 int (*func) (void *), void *arg) 351 { 352 void *intr; 353 354 #ifdef PCI_DEBUG 355 printf("ifpga_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, " 356 "func=%p, arg=%p)\n", pcv, ih, level, func, arg); 357 #endif 358 359 intr = ifpga_intr_establish(ih, level, func, arg); 360 361 return intr; 362 } 363 364 void 365 ifpga_pci_intr_disestablish(void *pcv, void *cookie) 366 { 367 #ifdef PCI_DEBUG 368 printf("ifpga_pci_intr_disestablish(pcv=%p, cookie=%p)\n", 369 pcv, cookie); 370 #endif 371 ifpga_intr_disestablish(cookie); 372 } 373
Indexes created Sun Oct 19 02:09:48 GMT 2025