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ifpgavar.h revision 1.6.2.1 
      1 /*	$NetBSD: ifpgavar.h,v 1.6.2.1 2014/05/22 11:39:41 yamt Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2001 ARM Ltd
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. The name of the company may not be used to endorse or promote
     16  *    products derived from this software without specific prior written
     17  *    permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     20  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     21  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29  * SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _IFPGAVAR_H_
     33 #define _IFPGAVAR_H_
     34 
     35 #include <sys/bus.h>
     36 #include <sys/evcnt.h>
     37 
     38 /* We statically map the UARTS at boot so that we can access the console
     39    before we've probed for the IFPGA. */
     40 #define UART0_BOOT_BASE		0xfde00000
     41 #define UART1_BOOT_BASE		0xfdf00000
     42 
     43 #define IFPGA_UART0		0x06000000	/* Uart 0 */
     44 #define IFPGA_UART1		0x07000000	/* Uart 1 */
     45 
     46 /* SMC91C111 network module. */
     47 #define IFPGA_SMC911_BASE	0xb8000000
     48 
     49 typedef paddr_t ifpga_addr_t;
     50 
     51 struct ifpga_softc {
     52 	bus_space_tag_t		sc_iot;		/* Bus tag */
     53 	bus_space_handle_t	sc_sc_ioh;	/* System Controller handle */
     54 	bus_space_handle_t	sc_cm_ioh;	/* Core Module handle */
     55 	bus_space_handle_t	sc_tmr_ioh;	/* Timers handle */
     56 	bus_space_handle_t	sc_irq_ioh;	/* IRQ controller handle */
     57 
     58 	/* Clock variables.  */
     59 	int			sc_statclock_count;
     60 	int			sc_clock_count;
     61 	int			sc_clock_ticks_per_256us;
     62 	void *			sc_clockintr;
     63 	void *			sc_statclockintr;
     64 };
     65 
     66 #define cf_iobase			cf_loc[IFPGACF_OFFSET]
     67 #define cf_irq				cf_loc[IFPGACF_IRQ]
     68 
     69 #define IRQUNK		IFPGACF_IRQ_DEFAULT
     70 
     71 struct ifpga_attach_args {
     72 	char *ifa_name;			/* Device name */
     73 	bus_space_tag_t    ifa_iot;	/* Bus space tag for io */
     74 	bus_space_handle_t ifa_sc_ioh;	/* System controller handle */
     75 
     76 	ifpga_addr_t	   ifa_addr;	/* Address of device.  */
     77 	int		   ifa_irq;	/* IRQ to use.  */
     78 	/*
     79 	 * Other data extracted from the system should go here.  Eg UART clock
     80 	 * rates.
     81 	 */
     82 };
     83 
     84 /* There are roughly 32 interrupt sources.  */
     85 #define NIRQ		32
     86 struct intrhand {
     87 	TAILQ_ENTRY(intrhand) ih_list;	/* link on intrq list */
     88 	int (*ih_func)(void *);		/* handler */
     89 	void *ih_arg;			/* arg for handler */
     90 	int ih_ipl;			/* IPL_* */
     91 	int ih_irq;			/* IRQ number */
     92 };
     93 
     94 #define IRQNAMESIZE	sizeof("tmr 0 hard")
     95 
     96 struct intrq {
     97 	TAILQ_HEAD(, intrhand) iq_list;	/* handler list */
     98 	struct evcnt iq_ev;		/* event counter */
     99 	int iq_mask;			/* IRQs to mask while handling */
    100 	int iq_levels;			/* IPL_*'s this IRQ has */
    101 	int iq_ist;			/* share type */
    102 };
    103 
    104 
    105 void ifpga_intr_init(void);
    106 void ifpga_intr_postinit(void);
    107 void *ifpga_intr_establish(int, int, int (*)(void *), void *);
    108 void ifpga_intr_disestablish(void *);
    109 
    110 void ifpga_create_io_bs_tag(struct bus_space *, void *);
    111 void ifpga_create_mem_bs_tag(struct bus_space *, void *);
    112 
    113 void ifpga_reset(void);
    114 
    115 #endif /* _IFPGAVAR_H */
    116