plcom_ifpga.c revision 1.1 1 /* $NetBSD: plcom_ifpga.c,v 1.1 2001/10/27 16:19:10 rearnsha Exp $ */
2
3 /*
4 * Copyright (c) 2001 ARM Ltd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 * products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 /* Interface to plcom (PL010) serial driver. */
33
34 #include <sys/types.h>
35 #include <sys/device.h>
36 #include <sys/systm.h>
37 #include <sys/param.h>
38 #include <sys/malloc.h>
39
40 #include <sys/termios.h>
41
42 #include <machine/intr.h>
43 #include <machine/bus.h>
44
45 #include <evbarm/dev/plcomreg.h>
46 #include <evbarm/dev/plcomvar.h>
47
48 #include <evbarm/ifpga/plcom_ifpgavar.h>
49
50 #include <evbarm/ifpga/ifpgareg.h>
51 #include <evbarm/ifpga/ifpgavar.h>
52
53 static int plcom_ifpga_match(struct device *, struct cfdata *, void *);
54 static void plcom_ifpga_attach(struct device *, struct device *, void *);
55 static void plcom_ifpga_set_mcr(void *, int, u_int);
56
57 struct cfattach plcom_ifpga_ca = {
58 sizeof(struct plcom_softc), plcom_ifpga_match, plcom_ifpga_attach
59 };
60
61 static int
62 plcom_ifpga_match(struct device *parent, struct cfdata *cf, void *aux)
63 {
64 if (strcmp(cf->cf_driver->cd_name, "plcom") == 0)
65 return 1;
66 return 0;
67 }
68
69 static void
70 plcom_ifpga_attach(struct device *parent, struct device *self, void *aux)
71 {
72 struct plcom_ifpga_softc *isc = (struct plcom_ifpga_softc *)self;
73 struct plcom_softc *sc = &isc->sc_plcom;
74 struct ifpga_attach_args *ifa = aux;
75 char *irqname;
76
77 isc->sc_iot = ifa->ifa_iot;
78 isc->sc_ioh = ifa->ifa_sc_ioh;
79 sc->sc_iounit = sc->sc_dev.dv_unit;
80 sc->sc_frequency = IFPGA_UART_CLK;
81 sc->sc_iot = ifa->ifa_iot;
82 sc->sc_hwflags = 0;
83 sc->sc_swflags = 0;
84 sc->sc_set_mcr = plcom_ifpga_set_mcr;
85 sc->sc_set_mcr_arg = (void *)isc;
86
87 if (bus_space_map(ifa->ifa_iot, ifa->ifa_addr, PLCOM_UART_SIZE, 0,
88 &sc->sc_ioh)) {
89 printf("%s: unable to map device\n", sc->sc_dev.dv_xname);
90 return;
91 }
92
93 plcom_attach_subr(sc);
94 irqname = malloc(sizeof("uart") + 2, M_DEVBUF, M_WAITOK);
95 sprintf(irqname, "uart%d", sc->sc_dev.dv_unit);
96 isc->sc_ih = intr_claim(ifa->ifa_irq, IPL_SERIAL, irqname, plcomintr,
97 sc);
98 if (isc->sc_ih == NULL)
99 panic("%s: cannot install interrupt handler\n",
100 sc->sc_dev.dv_xname);
101 }
102
103 static void plcom_ifpga_set_mcr(void *aux, int unit, u_int mcr)
104 {
105 struct plcom_ifpga_softc *isc = (struct plcom_ifpga_softc *)aux;
106 u_int set, clr;
107
108 set = clr = 0;
109
110 switch (unit) {
111 case 0:
112 if (mcr & MCR_RTS)
113 set |= IFPGA_SC_CTRL_UART0RTS;
114 else
115 clr |= IFPGA_SC_CTRL_UART0RTS;
116 if (mcr & MCR_DTR)
117 set |= IFPGA_SC_CTRL_UART0DTR;
118 else
119 clr |= IFPGA_SC_CTRL_UART0DTR;
120 case 1:
121 if (mcr & MCR_RTS)
122 set |= IFPGA_SC_CTRL_UART1RTS;
123 else
124 clr |= IFPGA_SC_CTRL_UART1RTS;
125 if (mcr & MCR_DTR)
126 set |= IFPGA_SC_CTRL_UART1DTR;
127 else
128 clr |= IFPGA_SC_CTRL_UART1DTR;
129 default:
130 return;
131 }
132
133 if (set)
134 bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLS,
135 set);
136 if (clr)
137 bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLC,
138 clr);
139 }
140