plcom_ifpga.c revision 1.13 1 /* $NetBSD: plcom_ifpga.c,v 1.13 2012/05/20 10:28:44 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2001 ARM Ltd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 * products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 /* Interface to plcom (PL010) serial driver. */
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: plcom_ifpga.c,v 1.13 2012/05/20 10:28:44 skrll Exp $");
36
37 #include <sys/types.h>
38 #include <sys/device.h>
39 #include <sys/systm.h>
40 #include <sys/param.h>
41 #include <sys/malloc.h>
42
43 #include <sys/termios.h>
44
45 #include <machine/intr.h>
46 #include <sys/bus.h>
47
48 #include <evbarm/dev/plcomreg.h>
49 #include <evbarm/dev/plcomvar.h>
50
51 #include <evbarm/ifpga/plcom_ifpgavar.h>
52
53 #include <evbarm/ifpga/ifpgareg.h>
54 #include <evbarm/ifpga/ifpgavar.h>
55
56 static int plcom_ifpga_match(device_t, cfdata_t, void *);
57 static void plcom_ifpga_attach(device_t, device_t, void *);
58 static void plcom_ifpga_set_mcr(void *, int, u_int);
59
60 CFATTACH_DECL_NEW(plcom_ifpga, sizeof(struct plcom_ifpga_softc),
61 plcom_ifpga_match, plcom_ifpga_attach, NULL, NULL);
62
63 static int
64 plcom_ifpga_match(device_t parent, cfdata_t cf, void *aux)
65 {
66 return 1;
67 }
68
69 static void
70 plcom_ifpga_attach(device_t parent, device_t self, void *aux)
71 {
72 struct plcom_ifpga_softc *isc = device_private(self);
73 struct plcom_softc *sc = &isc->sc_plcom;
74 struct ifpga_attach_args *ifa = aux;
75
76 isc->sc_iot = ifa->ifa_iot;
77 isc->sc_ioh = ifa->ifa_sc_ioh;
78 sc->sc_dev = self;
79 sc->sc_iounit = device_unit(sc->sc_dev);
80 sc->sc_frequency = IFPGA_UART_CLK;
81 sc->sc_iot = ifa->ifa_iot;
82 sc->sc_hwflags = 0;
83 sc->sc_swflags = 0;
84 sc->sc_set_mcr = plcom_ifpga_set_mcr;
85 sc->sc_set_mcr_arg = (void *)isc;
86
87 if (bus_space_map(ifa->ifa_iot, ifa->ifa_addr, PLCOM_UART_SIZE, 0,
88 &sc->sc_ioh)) {
89 printf("%s: unable to map device\n", device_xname(sc->sc_dev));
90 return;
91 }
92
93 plcom_attach_subr(sc);
94 isc->sc_ih = ifpga_intr_establish(ifa->ifa_irq, IPL_SERIAL, plcomintr,
95 sc);
96 if (isc->sc_ih == NULL)
97 panic("%s: cannot install interrupt handler",
98 device_xname(sc->sc_dev));
99 }
100
101 static void plcom_ifpga_set_mcr(void *aux, int unit, u_int mcr)
102 {
103 struct plcom_ifpga_softc *isc = (struct plcom_ifpga_softc *)aux;
104 u_int set, clr;
105
106 set = clr = 0;
107
108 switch (unit) {
109 case 0:
110 if (mcr & PL01X_MCR_RTS)
111 set |= IFPGA_SC_CTRL_UART0RTS;
112 else
113 clr |= IFPGA_SC_CTRL_UART0RTS;
114 if (mcr & PL01X_MCR_DTR)
115 set |= IFPGA_SC_CTRL_UART0DTR;
116 else
117 clr |= IFPGA_SC_CTRL_UART0DTR;
118 case 1:
119 if (mcr & PL01X_MCR_RTS)
120 set |= IFPGA_SC_CTRL_UART1RTS;
121 else
122 clr |= IFPGA_SC_CTRL_UART1RTS;
123 if (mcr & PL01X_MCR_DTR)
124 set |= IFPGA_SC_CTRL_UART1DTR;
125 else
126 clr |= IFPGA_SC_CTRL_UART1DTR;
127 default:
128 return;
129 }
130
131 if (set)
132 bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLS,
133 set);
134 if (clr)
135 bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLC,
136 clr);
137 }
138