imx23_olinuxino_machdep.c revision 1.2.4.3
1 1.2.4.2 tls /* $Id: imx23_olinuxino_machdep.c,v 1.2.4.3 2014/08/20 00:02:54 tls Exp $ */ 2 1.2.4.2 tls 3 1.2.4.2 tls /* 4 1.2.4.2 tls * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 1.2.4.2 tls * All rights reserved. 6 1.2.4.2 tls * 7 1.2.4.2 tls * This code is derived from software contributed to The NetBSD Foundation 8 1.2.4.2 tls * by Petri Laakso. 9 1.2.4.2 tls * 10 1.2.4.2 tls * Redistribution and use in source and binary forms, with or without 11 1.2.4.2 tls * modification, are permitted provided that the following conditions 12 1.2.4.2 tls * are met: 13 1.2.4.2 tls * 1. Redistributions of source code must retain the above copyright 14 1.2.4.2 tls * notice, this list of conditions and the following disclaimer. 15 1.2.4.2 tls * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.4.2 tls * notice, this list of conditions and the following disclaimer in the 17 1.2.4.2 tls * documentation and/or other materials provided with the distribution. 18 1.2.4.2 tls * 19 1.2.4.2 tls * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.4.2 tls * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.4.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.4.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.4.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.4.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.4.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.4.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.4.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.4.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.4.2 tls * POSSIBILITY OF SUCH DAMAGE. 30 1.2.4.2 tls */ 31 1.2.4.2 tls 32 1.2.4.2 tls #include <sys/bus.h> 33 1.2.4.2 tls #include <sys/cdefs.h> 34 1.2.4.2 tls #include <sys/device.h> 35 1.2.4.2 tls #include <sys/mount.h> 36 1.2.4.2 tls #include <sys/reboot.h> 37 1.2.4.2 tls #include <sys/systm.h> 38 1.2.4.2 tls #include <sys/termios.h> 39 1.2.4.2 tls #include <sys/types.h> 40 1.2.4.2 tls 41 1.2.4.2 tls #include <uvm/uvm_prot.h> 42 1.2.4.2 tls 43 1.2.4.2 tls #include <machine/bootconfig.h> 44 1.2.4.3 tls #include <machine/db_machdep.h> 45 1.2.4.2 tls #include <machine/pmap.h> 46 1.2.4.2 tls 47 1.2.4.3 tls #include <arm/armreg.h> 48 1.2.4.3 tls #include <arm/cpu.h> 49 1.2.4.3 tls #include <arm/cpufunc.h> 50 1.2.4.3 tls #include <arm/locore.h> 51 1.2.4.3 tls 52 1.2.4.2 tls #include <arm/arm32/machdep.h> 53 1.2.4.3 tls #include <arm/arm32/pte.h> 54 1.2.4.2 tls 55 1.2.4.2 tls #include <arm/imx/imx23_clkctrlreg.h> 56 1.2.4.3 tls #include <arm/imx/imx23_digctlreg.h> 57 1.2.4.2 tls #include <arm/imx/imx23_rtcreg.h> 58 1.2.4.2 tls #include <arm/imx/imx23_uartdbgreg.h> 59 1.2.4.2 tls #include <arm/imx/imx23var.h> 60 1.2.4.2 tls 61 1.2.4.2 tls #include "plcom.h" 62 1.2.4.2 tls #if (NPLCOM > 0) 63 1.2.4.2 tls #include <evbarm/dev/plcomreg.h> 64 1.2.4.2 tls #include <evbarm/dev/plcomvar.h> 65 1.2.4.2 tls #endif 66 1.2.4.2 tls 67 1.2.4.2 tls #include "opt_evbarm_boardtype.h" 68 1.2.4.2 tls 69 1.2.4.3 tls #define KERNEL_VM_BASE (KERNEL_BASE + 0x8000000) 70 1.2.4.3 tls #define KERNEL_VM_SIZE 0x20000000 71 1.2.4.3 tls 72 1.2.4.3 tls #define L1_PAGE_TABLE (DRAM_BASE + MEMSIZE * 1024 * 1024 - L1_TABLE_SIZE) 73 1.2.4.3 tls #define BOOTIMX23_ARGS (L1_PAGE_TABLE - MAX_BOOT_STRING - 1) 74 1.2.4.3 tls 75 1.2.4.3 tls #define PLCONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 76 1.2.4.3 tls #define PLCONSPEED 115200 77 1.2.4.3 tls 78 1.2.4.3 tls #define REG_RD(reg) *(volatile uint32_t *)(reg) 79 1.2.4.3 tls #define REG_WR(reg, val) \ 80 1.2.4.3 tls do { \ 81 1.2.4.3 tls *(volatile uint32_t *)((reg)) = val; \ 82 1.2.4.3 tls } while (0) 83 1.2.4.3 tls 84 1.2.4.3 tls #define KERNEL_BASE_PHYS ((paddr_t)&KERNEL_BASE_phys) 85 1.2.4.3 tls #define KERNEL_BASE_VIRT ((vaddr_t)&KERNEL_BASE_virt) 86 1.2.4.3 tls #define KERN_VTOPHYS(va) \ 87 1.2.4.3 tls ((paddr_t)((vaddr_t)(va) - KERNEL_BASE + KERNEL_BASE_PHYS)) 88 1.2.4.3 tls #define KERN_PHYSTOV(pa) \ 89 1.2.4.3 tls ((vaddr_t)((paddr_t)(pa) + KERNEL_BASE_VIRT + KERNEL_BASE)) 90 1.2.4.2 tls 91 1.2.4.2 tls /* 92 1.2.4.2 tls * Static device map for i.MX23 peripheral address space. 93 1.2.4.2 tls */ 94 1.2.4.2 tls #define _A(a) ((a) & ~L1_S_OFFSET) 95 1.2.4.2 tls #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 96 1.2.4.3 tls static const struct pmap_devmap devmap[] = { 97 1.2.4.2 tls { 98 1.2.4.2 tls _A(APBH_BASE), /* Virtual address. */ 99 1.2.4.2 tls _A(APBH_BASE), /* Physical address. */ 100 1.2.4.2 tls _S(APBH_SIZE + APBX_SIZE), /* APBX located after APBH. */ 101 1.2.4.2 tls VM_PROT_READ|VM_PROT_WRITE, /* Protection bits. */ 102 1.2.4.2 tls PTE_NOCACHE /* Cache attributes. */ 103 1.2.4.2 tls }, 104 1.2.4.2 tls { 0, 0, 0, 0, 0 } 105 1.2.4.2 tls }; 106 1.2.4.2 tls #undef _A 107 1.2.4.2 tls #undef _S 108 1.2.4.2 tls 109 1.2.4.3 tls static struct plcom_instance imx23_pi = { 110 1.2.4.3 tls .pi_type = PLCOM_TYPE_PL011, 111 1.2.4.3 tls .pi_iot = &imx23_bus_space, 112 1.2.4.3 tls .pi_size = PL011COM_UART_SIZE, 113 1.2.4.3 tls .pi_iobase = HW_UARTDBG_BASE 114 1.2.4.3 tls }; 115 1.2.4.2 tls 116 1.2.4.2 tls extern char KERNEL_BASE_phys; 117 1.2.4.2 tls extern char KERNEL_BASE_virt; 118 1.2.4.3 tls BootConfig bootconfig; 119 1.2.4.3 tls char *boot_args; 120 1.2.4.3 tls static char kernel_boot_args[MAX_BOOT_STRING]; 121 1.2.4.2 tls 122 1.2.4.3 tls #define SSP_DIV 2 123 1.2.4.3 tls #define IO_FRAC 27 124 1.2.4.2 tls 125 1.2.4.3 tls static void power_vddio_from_dcdc(int, int); 126 1.2.4.3 tls static void set_ssp_div(unsigned int); 127 1.2.4.3 tls static void set_io_frac(unsigned int); 128 1.2.4.3 tls static void bypass_ssp(void); 129 1.2.4.2 tls 130 1.2.4.2 tls /* 131 1.2.4.3 tls * Initialize ARM and return new SVC stack pointer. 132 1.2.4.2 tls */ 133 1.2.4.2 tls u_int 134 1.2.4.2 tls initarm(void *arg) 135 1.2.4.2 tls { 136 1.2.4.3 tls psize_t ram_size; 137 1.2.4.2 tls 138 1.2.4.2 tls if (set_cpufuncs()) 139 1.2.4.2 tls panic("set_cpufuncs failed"); 140 1.2.4.2 tls 141 1.2.4.3 tls pmap_devmap_register(devmap); 142 1.2.4.2 tls consinit(); 143 1.2.4.2 tls 144 1.2.4.2 tls #define BDSTR(s) _BDSTR(s) 145 1.2.4.2 tls #define _BDSTR(s) #s 146 1.2.4.2 tls printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 147 1.2.4.2 tls #undef BDSTR 148 1.2.4.2 tls #undef _BDSTR 149 1.2.4.2 tls 150 1.2.4.3 tls /* 151 1.2.4.3 tls * SSP_CLK setup was postponed here from bootimx23 because SB wasn't 152 1.2.4.3 tls * able to load kernel if clocks were changed. 153 1.2.4.3 tls */ 154 1.2.4.3 tls power_vddio_from_dcdc(3300, 2925); 155 1.2.4.3 tls set_ssp_div(SSP_DIV); 156 1.2.4.3 tls set_io_frac(IO_FRAC); 157 1.2.4.3 tls bypass_ssp(); 158 1.2.4.3 tls 159 1.2.4.3 tls cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 160 1.2.4.3 tls 161 1.2.4.2 tls /* Copy boot arguments passed from bootimx23. */ 162 1.2.4.3 tls boot_args = (char *)KERN_PHYSTOV(BOOTIMX23_ARGS); 163 1.2.4.2 tls memcpy(kernel_boot_args, boot_args, MAX_BOOT_STRING); 164 1.2.4.2 tls boot_args = kernel_boot_args; 165 1.2.4.2 tls #ifdef VERBOSE_INIT_ARM 166 1.2.4.3 tls printf("boot_args @ %lx: '%s'\n", KERN_PHYSTOV(BOOTIMX23_ARGS), 167 1.2.4.3 tls boot_args); 168 1.2.4.2 tls #endif 169 1.2.4.2 tls parse_mi_bootargs(boot_args); 170 1.2.4.2 tls 171 1.2.4.3 tls ram_size = MEMSIZE * 1024 * 1024; 172 1.2.4.2 tls 173 1.2.4.2 tls bootconfig.dramblocks = 1; 174 1.2.4.2 tls bootconfig.dram[0].address = DRAM_BASE; 175 1.2.4.3 tls bootconfig.dram[0].pages = ram_size / PAGE_SIZE; 176 1.2.4.3 tls bootconfig.dram[0].flags = BOOT_DRAM_CAN_DMA | BOOT_DRAM_PREFER; 177 1.2.4.2 tls 178 1.2.4.3 tls arm32_bootmem_init(bootconfig.dram[0].address, ram_size, 179 1.2.4.3 tls ((vsize_t)&KERNEL_BASE_phys)); 180 1.2.4.2 tls 181 1.2.4.3 tls arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, devmap, 182 1.2.4.3 tls true); 183 1.2.4.2 tls 184 1.2.4.3 tls return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 185 1.2.4.2 tls } 186 1.2.4.2 tls 187 1.2.4.2 tls /* 188 1.2.4.2 tls * Initialize console. 189 1.2.4.2 tls */ 190 1.2.4.2 tls void 191 1.2.4.2 tls consinit(void) 192 1.2.4.2 tls { 193 1.2.4.2 tls /* consinit() is called from also from the main(). */ 194 1.2.4.2 tls static int consinit_called = 0; 195 1.2.4.2 tls 196 1.2.4.2 tls if (consinit_called) 197 1.2.4.2 tls return; 198 1.2.4.2 tls 199 1.2.4.2 tls plcomcnattach(&imx23_pi, PLCONSPEED, IMX23_UART_CLK, PLCONMODE, 0); 200 1.2.4.2 tls 201 1.2.4.2 tls consinit_called = 1; 202 1.2.4.2 tls 203 1.2.4.2 tls return; 204 1.2.4.2 tls } 205 1.2.4.2 tls 206 1.2.4.2 tls /* 207 1.2.4.2 tls * Reboot or halt the system. 208 1.2.4.2 tls */ 209 1.2.4.2 tls void 210 1.2.4.2 tls cpu_reboot(int howto, char *bootstr) 211 1.2.4.2 tls { 212 1.2.4.2 tls static int cpu_reboot_called = 0; 213 1.2.4.2 tls 214 1.2.4.2 tls boothowto |= howto; 215 1.2.4.2 tls 216 1.2.4.2 tls /* 217 1.2.4.2 tls * If this is the first invocation of cpu_reboot() and the RB_NOSYNC 218 1.2.4.2 tls * flag is not set in howto; sync and unmount the system disks by 219 1.2.4.2 tls * calling vfs_shutdown(9) and set the time of day clock by calling 220 1.2.4.2 tls * resettodr(9). 221 1.2.4.2 tls */ 222 1.2.4.2 tls if (!cpu_reboot_called && !(boothowto & RB_NOSYNC)) { 223 1.2.4.2 tls vfs_shutdown(); 224 1.2.4.2 tls resettodr(); 225 1.2.4.2 tls } 226 1.2.4.2 tls 227 1.2.4.2 tls cpu_reboot_called = 1; 228 1.2.4.2 tls 229 1.2.4.2 tls IRQdisable; /* FIQ's stays on because they are special. */ 230 1.2.4.2 tls 231 1.2.4.2 tls /* 232 1.2.4.2 tls * If rebooting after a crash (i.e., if RB_DUMP is set in howto, but 233 1.2.4.2 tls * RB_HALT is not), save a system crash dump. 234 1.2.4.2 tls */ 235 1.2.4.3 tls if ((boothowto & RB_DUMP) && !(boothowto & RB_HALT)) { 236 1.2.4.2 tls panic("please implement crash dump!"); // XXX 237 1.2.4.3 tls for(;;); 238 1.2.4.3 tls /* NOTREACHED */ 239 1.2.4.3 tls } 240 1.2.4.2 tls 241 1.2.4.2 tls /* Run any shutdown hooks by calling pmf_system_shutdown(9). */ 242 1.2.4.2 tls pmf_system_shutdown(boothowto); 243 1.2.4.2 tls 244 1.2.4.2 tls printf("system %s.\n", boothowto & RB_HALT ? "halted" : "rebooted"); 245 1.2.4.2 tls 246 1.2.4.2 tls if (boothowto & RB_HALT) { 247 1.2.4.2 tls /* Enable i.MX233 wait-for-interrupt mode. */ 248 1.2.4.2 tls REG_WR(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU, 249 1.2.4.2 tls (REG_RD(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU) | 250 1.2.4.2 tls HW_CLKCTRL_CPU_INTERRUPT_WAIT)); 251 1.2.4.2 tls 252 1.2.4.2 tls /* Disable FIQ's and wait for interrupt (which never arrives) */ 253 1.2.4.3 tls __asm volatile( \ 254 1.2.4.2 tls "mrs r0, cpsr\n\t" \ 255 1.2.4.2 tls "orr r0, #0x40\n\t" \ 256 1.2.4.3 tls "msr cpsr_c, r0\n\t" \ 257 1.2.4.2 tls "mov r0, #0\n\t" \ 258 1.2.4.2 tls "mcr p15, 0, r0, c7, c0, 4\n\t" 259 1.2.4.2 tls ); 260 1.2.4.2 tls 261 1.2.4.2 tls for(;;); 262 1.2.4.2 tls 263 1.2.4.2 tls /* NOT REACHED */ 264 1.2.4.2 tls } 265 1.2.4.2 tls 266 1.2.4.2 tls /* Reboot the system. */ 267 1.2.4.2 tls REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 10000); 268 1.2.4.2 tls REG_WR(HW_RTC_BASE + HW_RTC_CTRL_SET, HW_RTC_CTRL_WATCHDOGEN); 269 1.2.4.2 tls REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 0); 270 1.2.4.2 tls 271 1.2.4.2 tls for(;;); 272 1.2.4.2 tls 273 1.2.4.2 tls /* NOT REACHED */ 274 1.2.4.2 tls } 275 1.2.4.2 tls 276 1.2.4.2 tls /* 277 1.2.4.2 tls * Delay us microseconds. 278 1.2.4.2 tls */ 279 1.2.4.2 tls void 280 1.2.4.2 tls delay(unsigned int us) 281 1.2.4.2 tls { 282 1.2.4.2 tls uint32_t start; 283 1.2.4.2 tls uint32_t now; 284 1.2.4.2 tls uint32_t elapsed; 285 1.2.4.2 tls uint32_t total; 286 1.2.4.2 tls uint32_t last; 287 1.2.4.2 tls 288 1.2.4.2 tls total = 0; 289 1.2.4.2 tls last = 0; 290 1.2.4.2 tls start = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS); 291 1.2.4.2 tls 292 1.2.4.2 tls do { 293 1.2.4.2 tls now = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS); 294 1.2.4.2 tls 295 1.2.4.2 tls if (start <= now) 296 1.2.4.2 tls elapsed = now - start; 297 1.2.4.2 tls else /* Take care of overflow. */ 298 1.2.4.2 tls elapsed = (UINT32_MAX - start) + 1 + now; 299 1.2.4.2 tls 300 1.2.4.2 tls total += elapsed - last; 301 1.2.4.2 tls last = elapsed; 302 1.2.4.2 tls 303 1.2.4.2 tls } while (total < us); 304 1.2.4.2 tls 305 1.2.4.2 tls return; 306 1.2.4.2 tls } 307 1.2.4.3 tls #include <arm/imx/imx23_powerreg.h> 308 1.2.4.3 tls #define PWR_VDDIOCTRL (HW_POWER_BASE + HW_POWER_VDDIOCTRL) 309 1.2.4.3 tls #define PWR_CTRL (HW_POWER_BASE + HW_POWER_CTRL) 310 1.2.4.3 tls #define PWR_CTRL_S (HW_POWER_BASE + HW_POWER_CTRL_SET) 311 1.2.4.3 tls #define PWR_CTRL_C (HW_POWER_BASE + HW_POWER_CTRL_CLR) 312 1.2.4.3 tls 313 1.2.4.3 tls static void 314 1.2.4.3 tls power_vddio_from_dcdc(int target, int brownout) 315 1.2.4.3 tls { 316 1.2.4.3 tls uint32_t tmp_r; 317 1.2.4.3 tls 318 1.2.4.3 tls /* BO_OFFSET must be withing 2700mV - 3475mV */ 319 1.2.4.3 tls if (brownout > 3475) 320 1.2.4.3 tls brownout = 3475; 321 1.2.4.3 tls else if (brownout < 2700) 322 1.2.4.3 tls brownout = 2700; 323 1.2.4.3 tls 324 1.2.4.3 tls 325 1.2.4.3 tls /* Set LINREG_OFFSET one step below TRG. */ 326 1.2.4.3 tls tmp_r = REG_RD(PWR_VDDIOCTRL); 327 1.2.4.3 tls tmp_r &= ~HW_POWER_VDDIOCTRL_LINREG_OFFSET; 328 1.2.4.3 tls tmp_r |= __SHIFTIN(2, HW_POWER_VDDIOCTRL_LINREG_OFFSET); 329 1.2.4.3 tls REG_WR(PWR_VDDIOCTRL, tmp_r); 330 1.2.4.3 tls delay(10000); 331 1.2.4.3 tls 332 1.2.4.3 tls /* Enable VDDIO switching converter output. */ 333 1.2.4.3 tls tmp_r = REG_RD(PWR_VDDIOCTRL); 334 1.2.4.3 tls tmp_r &= ~HW_POWER_VDDIOCTRL_DISABLE_FET; 335 1.2.4.3 tls REG_WR(PWR_VDDIOCTRL, tmp_r); 336 1.2.4.3 tls delay(10000); 337 1.2.4.3 tls 338 1.2.4.3 tls /* Set target voltage and brownout level. */ 339 1.2.4.3 tls tmp_r = REG_RD(PWR_VDDIOCTRL); 340 1.2.4.3 tls tmp_r &= ~(HW_POWER_VDDIOCTRL_BO_OFFSET | HW_POWER_VDDIOCTRL_TRG); 341 1.2.4.3 tls tmp_r |= __SHIFTIN(((target - brownout) / 25), 342 1.2.4.3 tls HW_POWER_VDDIOCTRL_BO_OFFSET); 343 1.2.4.3 tls tmp_r |= __SHIFTIN(((target - 2800) / 25), HW_POWER_VDDIOCTRL_TRG); 344 1.2.4.3 tls REG_WR(PWR_VDDIOCTRL, tmp_r); 345 1.2.4.3 tls delay(10000); 346 1.2.4.3 tls 347 1.2.4.3 tls /* Enable PWDN_BRNOUT. */ 348 1.2.4.3 tls REG_WR(PWR_CTRL_C, HW_POWER_CTRL_VDDIO_BO_IRQ); 349 1.2.4.3 tls 350 1.2.4.3 tls tmp_r = REG_RD(PWR_VDDIOCTRL); 351 1.2.4.3 tls tmp_r |= HW_POWER_VDDIOCTRL_PWDN_BRNOUT; 352 1.2.4.3 tls REG_WR(PWR_VDDIOCTRL, tmp_r); 353 1.2.4.3 tls 354 1.2.4.3 tls return; 355 1.2.4.3 tls } 356 1.2.4.3 tls #include <arm/imx/imx23_clkctrlreg.h> 357 1.2.4.3 tls #define CLKCTRL_SSP (HW_CLKCTRL_BASE + HW_CLKCTRL_SSP) 358 1.2.4.3 tls #define CLKCTRL_FRAC (HW_CLKCTRL_BASE + HW_CLKCTRL_FRAC) 359 1.2.4.3 tls #define CLKCTRL_SEQ_C (HW_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ_CLR) 360 1.2.4.3 tls 361 1.2.4.3 tls static 362 1.2.4.3 tls void set_ssp_div(unsigned int div) 363 1.2.4.3 tls { 364 1.2.4.3 tls uint32_t tmp_r; 365 1.2.4.3 tls 366 1.2.4.3 tls tmp_r = REG_RD(CLKCTRL_SSP); 367 1.2.4.3 tls tmp_r &= ~HW_CLKCTRL_SSP_CLKGATE; 368 1.2.4.3 tls REG_WR(CLKCTRL_SSP, tmp_r); 369 1.2.4.3 tls 370 1.2.4.3 tls while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY) 371 1.2.4.3 tls ; 372 1.2.4.3 tls 373 1.2.4.3 tls tmp_r = REG_RD(CLKCTRL_SSP); 374 1.2.4.3 tls tmp_r &= ~HW_CLKCTRL_SSP_DIV; 375 1.2.4.3 tls tmp_r |= __SHIFTIN(div, HW_CLKCTRL_SSP_DIV); 376 1.2.4.3 tls REG_WR(CLKCTRL_SSP, tmp_r); 377 1.2.4.3 tls 378 1.2.4.3 tls while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY) 379 1.2.4.3 tls ; 380 1.2.4.3 tls 381 1.2.4.3 tls return; 382 1.2.4.3 tls 383 1.2.4.3 tls } 384 1.2.4.3 tls static 385 1.2.4.3 tls void set_io_frac(unsigned int frac) 386 1.2.4.3 tls { 387 1.2.4.3 tls uint8_t *io_frac; 388 1.2.4.3 tls uint32_t tmp_r; 389 1.2.4.3 tls 390 1.2.4.3 tls io_frac = (uint8_t *)(CLKCTRL_FRAC); 391 1.2.4.3 tls io_frac++; /* emi */ 392 1.2.4.3 tls io_frac++; /* pix */ 393 1.2.4.3 tls io_frac++; /* io */ 394 1.2.4.3 tls tmp_r = (*io_frac)<<24; 395 1.2.4.3 tls tmp_r &= ~(HW_CLKCTRL_FRAC_CLKGATEIO | HW_CLKCTRL_FRAC_IOFRAC); 396 1.2.4.3 tls tmp_r |= __SHIFTIN(frac, HW_CLKCTRL_FRAC_IOFRAC); 397 1.2.4.3 tls 398 1.2.4.3 tls *io_frac = (uint8_t)(tmp_r>>24); 399 1.2.4.3 tls 400 1.2.4.3 tls return; 401 1.2.4.3 tls } 402 1.2.4.3 tls static 403 1.2.4.3 tls void bypass_ssp(void) 404 1.2.4.3 tls { 405 1.2.4.3 tls REG_WR(CLKCTRL_SEQ_C, HW_CLKCTRL_CLKSEQ_BYPASS_SSP); 406 1.2.4.3 tls 407 1.2.4.3 tls return; 408 1.2.4.3 tls } 409 1.2.4.3 tls 410 1.2.4.3 tls 411
Indexes created Tue Oct 14 15:09:51 GMT 2025