intr.h revision 1.19
11.19Smatt/*	$NetBSD: intr.h,v 1.19 2008/01/06 01:37:58 matt Exp $	*/
21.1Smatt
31.1Smatt/*
41.10Sthorpej * Copyright (c) 2001, 2003 Wasabi Systems, Inc.
51.1Smatt * All rights reserved.
61.1Smatt *
71.7Sthorpej * Written by Jason R. Thorpe for Wasabi Systems, Inc.
81.7Sthorpej *
91.1Smatt * Redistribution and use in source and binary forms, with or without
101.1Smatt * modification, are permitted provided that the following conditions
111.1Smatt * are met:
121.1Smatt * 1. Redistributions of source code must retain the above copyright
131.1Smatt *    notice, this list of conditions and the following disclaimer.
141.1Smatt * 2. Redistributions in binary form must reproduce the above copyright
151.1Smatt *    notice, this list of conditions and the following disclaimer in the
161.1Smatt *    documentation and/or other materials provided with the distribution.
171.1Smatt * 3. All advertising materials mentioning features or use of this software
181.1Smatt *    must display the following acknowledgement:
191.7Sthorpej *	This product includes software developed for the NetBSD Project by
201.7Sthorpej *	Wasabi Systems, Inc.
211.7Sthorpej * 4. The name of Wasabi Systems, Inc. may not be used to endorse
221.7Sthorpej *    or promote products derived from this software without specific prior
231.7Sthorpej *    written permission.
241.1Smatt *
251.7Sthorpej * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
261.7Sthorpej * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
271.7Sthorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
281.7Sthorpej * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
291.7Sthorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
301.7Sthorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
311.7Sthorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
321.7Sthorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
331.7Sthorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
341.7Sthorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
351.7Sthorpej * POSSIBILITY OF SUCH DAMAGE.
361.1Smatt */
371.1Smatt
381.7Sthorpej#ifndef	_EVBARM_INTR_H_
391.7Sthorpej#define	_EVBARM_INTR_H_
401.3Srearnsha
411.7Sthorpej#ifdef _KERNEL
421.3Srearnsha
431.7Sthorpej/* Interrupt priority "levels". */
441.19Smatt#ifdef __HAVE_FAST_SOFTINTS
451.19Smatt#define	IPL_NONE	0		/* nothing */
461.19Smatt#define	IPL_SOFTCLOCK	1		/* clock */
471.19Smatt#define	IPL_SOFTBIO	2		/* block I/O */
481.19Smatt#define	IPL_SOFTNET	3		/* software network interrupt */
491.19Smatt#define	IPL_SOFTSERIAL	4		/* software serial interrupt */
501.19Smatt#define	IPL_VM		5		/* memory allocation */
511.19Smatt#define	IPL_SCHED	6		/* clock interrupt */
521.19Smatt#define	IPL_HIGH	7		/* everything */
531.3Srearnsha
541.18Sad#define	NIPL		8
551.19Smatt#else
561.19Smatt#define	IPL_NONE	0		/* nothing */
571.19Smatt#define	IPL_SOFTCLOCK	IPL_NONE	/* clock */
581.19Smatt#define	IPL_SOFTBIO	IPL_NONE	/* block I/O */
591.19Smatt#define	IPL_SOFTNET	IPL_NONE	/* software network interrupt */
601.19Smatt#define	IPL_SOFTSERIAL	IPL_NONE	/* software serial interrupt */
611.19Smatt#define	IPL_VM		1		/* memory allocation */
621.19Smatt#define	IPL_SCHED	2		/* clock interrupt */
631.19Smatt#define	IPL_HIGH	3		/* everything */
641.19Smatt
651.19Smatt#define	NIPL		4
661.19Smatt#endif
671.3Srearnsha
681.7Sthorpej/* Interrupt sharing types. */
691.7Sthorpej#define	IST_NONE	0	/* none */
701.3Srearnsha#define	IST_PULSE	1	/* pulsed */
711.3Srearnsha#define	IST_EDGE	2	/* edge-triggered */
721.3Srearnsha#define	IST_LEVEL	3	/* level-triggered */
731.11Sbsh
741.11Sbsh#define IST_LEVEL_LOW	 IST_LEVEL
751.11Sbsh#define IST_LEVEL_HIGH   4
761.11Sbsh#define IST_EDGE_FALLING IST_EDGE
771.11Sbsh#define IST_EDGE_RISING  5
781.11Sbsh#define IST_EDGE_BOTH    6
791.3Srearnsha
801.7Sthorpej#ifdef __OLD_INTERRUPT_CODE	/* XXX XXX XXX */
811.7Sthorpej
821.3Srearnsha/* Software interrupt priority levels */
831.3Srearnsha
841.19Smatt#ifdef __HAVE_FAST_SOFTINTS
851.7Sthorpej#define SOFTIRQ_CLOCK   0
861.18Sad#define SOFTIRQ_BIO     1
871.18Sad#define SOFTIRQ_NET     2
881.18Sad#define SOFTIRQ_SERIAL  3
891.3Srearnsha
901.7Sthorpej#define SOFTIRQ_BIT(x)  (1 << x)
911.19Smatt#endif
921.3Srearnsha
931.6Sthorpej#include <arm/arm32/psl.h>
941.1Smatt
951.7Sthorpej#else /* ! __OLD_INTERRUPT_CODE */
961.7Sthorpej
971.7Sthorpej#define	__NEWINTR	/* enables new hooks in cpu_fork()/cpu_switch() */
981.7Sthorpej
991.7Sthorpej#ifndef _LOCORE
1001.7Sthorpej
1011.7Sthorpej#include <sys/device.h>
1021.7Sthorpej#include <sys/queue.h>
1031.7Sthorpej
1041.8Sbriggs#if defined(_LKM)
1051.8Sbriggs
1061.8Sbriggsint	_splraise(int);
1071.8Sbriggsint	_spllower(int);
1081.8Sbriggsvoid	splx(int);
1091.19Smatt#ifdef __HAVE_FAST_SOFTINTS
1101.8Sbriggsvoid	_setsoftintr(int);
1111.19Smatt#endif
1121.8Sbriggs
1131.8Sbriggs#else	/* _LKM */
1141.8Sbriggs
1151.10Sthorpej#include "opt_arm_intr_impl.h"
1161.8Sbriggs
1171.10Sthorpej#if defined(ARM_INTR_IMPL)
1181.8Sbriggs
1191.8Sbriggs/*
1201.8Sbriggs * Each board needs to define the following functions:
1211.8Sbriggs *
1221.8Sbriggs * int	_splraise(int);
1231.8Sbriggs * int	_spllower(int);
1241.8Sbriggs * void	splx(int);
1251.8Sbriggs *
1261.13Sperry * These may be defined as functions, static inline functions, or macros,
1271.8Sbriggs * but there must be a _spllower() and splx() defined as functions callable
1281.8Sbriggs * from assembly language (for cpu_switch()).  However, since it's quite
1291.8Sbriggs * useful to be able to inline splx(), you could do something like the
1301.8Sbriggs * following:
1311.8Sbriggs *
1321.8Sbriggs * in <boardtype>_intr.h:
1331.13Sperry * 	static inline int
1341.8Sbriggs *	boardtype_splx(int spl)
1351.8Sbriggs *	{...}
1361.8Sbriggs *
1371.8Sbriggs *	#define splx(nspl)	boardtype_splx(nspl)
1381.8Sbriggs *	...
1391.8Sbriggs * and in boardtype's machdep code:
1401.8Sbriggs *
1411.8Sbriggs *	...
1421.8Sbriggs *	#undef splx
1431.8Sbriggs *	int
1441.8Sbriggs *	splx(int spl)
1451.8Sbriggs *	{
1461.8Sbriggs *		return boardtype_splx(spl);
1471.8Sbriggs *	}
1481.8Sbriggs */
1491.8Sbriggs
1501.10Sthorpej#include ARM_INTR_IMPL
1511.8Sbriggs
1521.10Sthorpej#else /* ARM_INTR_IMPL */
1531.8Sbriggs
1541.10Sthorpej#error ARM_INTR_IMPL not defined.
1551.8Sbriggs
1561.10Sthorpej#endif	/* ARM_INTR_IMPL */
1571.8Sbriggs
1581.10Sthorpej#endif /* _LKM */
1591.7Sthorpej
1601.17Sthorpejtypedef uint8_t ipl_t;
1611.15Syamttypedef struct {
1621.15Syamt	ipl_t _ipl;
1631.15Syamt} ipl_cookie_t;
1641.15Syamt
1651.15Syamtstatic inline ipl_cookie_t
1661.15Syamtmakeiplcookie(ipl_t ipl)
1671.15Syamt{
1681.15Syamt
1691.15Syamt	return (ipl_cookie_t){._ipl = ipl};
1701.15Syamt}
1711.15Syamt
1721.15Syamtstatic inline int
1731.15Syamtsplraiseipl(ipl_cookie_t icookie)
1741.15Syamt{
1751.15Syamt
1761.15Syamt	return _splraise(icookie._ipl);
1771.15Syamt}
1781.7Sthorpej
1791.7Sthorpej#define	spl0()		_spllower(IPL_NONE)
1801.7Sthorpej
1811.14Syamt#include <sys/spl.h>
1821.7Sthorpej
1831.10Sthorpej#endif /* ! _LOCORE */
1841.7Sthorpej
1851.7Sthorpej#endif /* __OLD_INTERRUPT_CODE */
1861.7Sthorpej
1871.7Sthorpej#endif /* _KERNEL */
1881.7Sthorpej
1891.7Sthorpej#endif	/* _EVBARM_INTR_H_ */
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