intr.h revision 1.20
11.20Smatt/* $NetBSD: intr.h,v 1.20 2008/04/27 18:58:46 matt Exp $ */ 21.1Smatt 31.1Smatt/* 41.10Sthorpej * Copyright (c) 2001, 2003 Wasabi Systems, Inc. 51.1Smatt * All rights reserved. 61.1Smatt * 71.7Sthorpej * Written by Jason R. Thorpe for Wasabi Systems, Inc. 81.7Sthorpej * 91.1Smatt * Redistribution and use in source and binary forms, with or without 101.1Smatt * modification, are permitted provided that the following conditions 111.1Smatt * are met: 121.1Smatt * 1. Redistributions of source code must retain the above copyright 131.1Smatt * notice, this list of conditions and the following disclaimer. 141.1Smatt * 2. Redistributions in binary form must reproduce the above copyright 151.1Smatt * notice, this list of conditions and the following disclaimer in the 161.1Smatt * documentation and/or other materials provided with the distribution. 171.1Smatt * 3. All advertising materials mentioning features or use of this software 181.1Smatt * must display the following acknowledgement: 191.7Sthorpej * This product includes software developed for the NetBSD Project by 201.7Sthorpej * Wasabi Systems, Inc. 211.7Sthorpej * 4. The name of Wasabi Systems, Inc. may not be used to endorse 221.7Sthorpej * or promote products derived from this software without specific prior 231.7Sthorpej * written permission. 241.1Smatt * 251.7Sthorpej * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 261.7Sthorpej * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 271.7Sthorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 281.7Sthorpej * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 291.7Sthorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 301.7Sthorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 311.7Sthorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 321.7Sthorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 331.7Sthorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 341.7Sthorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 351.7Sthorpej * POSSIBILITY OF SUCH DAMAGE. 361.1Smatt */ 371.1Smatt 381.7Sthorpej#ifndef _EVBARM_INTR_H_ 391.7Sthorpej#define _EVBARM_INTR_H_ 401.3Srearnsha 411.7Sthorpej#ifdef _KERNEL 421.3Srearnsha 431.7Sthorpej/* Interrupt priority "levels". */ 441.19Smatt#ifdef __HAVE_FAST_SOFTINTS 451.19Smatt#define IPL_NONE 0 /* nothing */ 461.19Smatt#define IPL_SOFTCLOCK 1 /* clock */ 471.19Smatt#define IPL_SOFTBIO 2 /* block I/O */ 481.19Smatt#define IPL_SOFTNET 3 /* software network interrupt */ 491.19Smatt#define IPL_SOFTSERIAL 4 /* software serial interrupt */ 501.19Smatt#define IPL_VM 5 /* memory allocation */ 511.19Smatt#define IPL_SCHED 6 /* clock interrupt */ 521.19Smatt#define IPL_HIGH 7 /* everything */ 531.3Srearnsha 541.18Sad#define NIPL 8 551.19Smatt#else 561.19Smatt#define IPL_NONE 0 /* nothing */ 571.19Smatt#define IPL_SOFTCLOCK IPL_NONE /* clock */ 581.19Smatt#define IPL_SOFTBIO IPL_NONE /* block I/O */ 591.19Smatt#define IPL_SOFTNET IPL_NONE /* software network interrupt */ 601.19Smatt#define IPL_SOFTSERIAL IPL_NONE /* software serial interrupt */ 611.19Smatt#define IPL_VM 1 /* memory allocation */ 621.19Smatt#define IPL_SCHED 2 /* clock interrupt */ 631.19Smatt#define IPL_HIGH 3 /* everything */ 641.19Smatt 651.19Smatt#define NIPL 4 661.19Smatt#endif 671.3Srearnsha 681.7Sthorpej/* Interrupt sharing types. */ 691.7Sthorpej#define IST_NONE 0 /* none */ 701.3Srearnsha#define IST_PULSE 1 /* pulsed */ 711.3Srearnsha#define IST_EDGE 2 /* edge-triggered */ 721.3Srearnsha#define IST_LEVEL 3 /* level-triggered */ 731.11Sbsh 741.20Smatt#define IST_LEVEL_LOW IST_LEVEL 751.20Smatt#define IST_LEVEL_HIGH 4 761.11Sbsh#define IST_EDGE_FALLING IST_EDGE 771.20Smatt#define IST_EDGE_RISING 5 781.20Smatt#define IST_EDGE_BOTH 6 791.20Smatt#define IST_SOFT 7 801.3Srearnsha 811.7Sthorpej#ifdef __OLD_INTERRUPT_CODE /* XXX XXX XXX */ 821.7Sthorpej 831.3Srearnsha/* Software interrupt priority levels */ 841.3Srearnsha 851.19Smatt#ifdef __HAVE_FAST_SOFTINTS 861.7Sthorpej#define SOFTIRQ_CLOCK 0 871.18Sad#define SOFTIRQ_BIO 1 881.18Sad#define SOFTIRQ_NET 2 891.18Sad#define SOFTIRQ_SERIAL 3 901.3Srearnsha 911.7Sthorpej#define SOFTIRQ_BIT(x) (1 << x) 921.19Smatt#endif 931.3Srearnsha 941.6Sthorpej#include <arm/arm32/psl.h> 951.1Smatt 961.7Sthorpej#else /* ! __OLD_INTERRUPT_CODE */ 971.7Sthorpej 981.7Sthorpej#define __NEWINTR /* enables new hooks in cpu_fork()/cpu_switch() */ 991.7Sthorpej 1001.7Sthorpej#ifndef _LOCORE 1011.7Sthorpej 1021.7Sthorpej#include <sys/device.h> 1031.7Sthorpej#include <sys/queue.h> 1041.7Sthorpej 1051.8Sbriggs#if defined(_LKM) 1061.8Sbriggs 1071.8Sbriggsint _splraise(int); 1081.8Sbriggsint _spllower(int); 1091.8Sbriggsvoid splx(int); 1101.19Smatt#ifdef __HAVE_FAST_SOFTINTS 1111.8Sbriggsvoid _setsoftintr(int); 1121.19Smatt#endif 1131.8Sbriggs 1141.8Sbriggs#else /* _LKM */ 1151.8Sbriggs 1161.10Sthorpej#include "opt_arm_intr_impl.h" 1171.8Sbriggs 1181.10Sthorpej#if defined(ARM_INTR_IMPL) 1191.8Sbriggs 1201.8Sbriggs/* 1211.8Sbriggs * Each board needs to define the following functions: 1221.8Sbriggs * 1231.8Sbriggs * int _splraise(int); 1241.8Sbriggs * int _spllower(int); 1251.8Sbriggs * void splx(int); 1261.8Sbriggs * 1271.13Sperry * These may be defined as functions, static inline functions, or macros, 1281.8Sbriggs * but there must be a _spllower() and splx() defined as functions callable 1291.8Sbriggs * from assembly language (for cpu_switch()). However, since it's quite 1301.8Sbriggs * useful to be able to inline splx(), you could do something like the 1311.8Sbriggs * following: 1321.8Sbriggs * 1331.8Sbriggs * in <boardtype>_intr.h: 1341.13Sperry * static inline int 1351.8Sbriggs * boardtype_splx(int spl) 1361.8Sbriggs * {...} 1371.8Sbriggs * 1381.8Sbriggs * #define splx(nspl) boardtype_splx(nspl) 1391.8Sbriggs * ... 1401.8Sbriggs * and in boardtype's machdep code: 1411.8Sbriggs * 1421.8Sbriggs * ... 1431.8Sbriggs * #undef splx 1441.8Sbriggs * int 1451.8Sbriggs * splx(int spl) 1461.8Sbriggs * { 1471.8Sbriggs * return boardtype_splx(spl); 1481.8Sbriggs * } 1491.8Sbriggs */ 1501.8Sbriggs 1511.10Sthorpej#include ARM_INTR_IMPL 1521.8Sbriggs 1531.10Sthorpej#else /* ARM_INTR_IMPL */ 1541.8Sbriggs 1551.10Sthorpej#error ARM_INTR_IMPL not defined. 1561.8Sbriggs 1571.10Sthorpej#endif /* ARM_INTR_IMPL */ 1581.8Sbriggs 1591.10Sthorpej#endif /* _LKM */ 1601.7Sthorpej 1611.17Sthorpejtypedef uint8_t ipl_t; 1621.15Syamttypedef struct { 1631.15Syamt ipl_t _ipl; 1641.15Syamt} ipl_cookie_t; 1651.15Syamt 1661.15Syamtstatic inline ipl_cookie_t 1671.15Syamtmakeiplcookie(ipl_t ipl) 1681.15Syamt{ 1691.15Syamt 1701.15Syamt return (ipl_cookie_t){._ipl = ipl}; 1711.15Syamt} 1721.15Syamt 1731.15Syamtstatic inline int 1741.15Syamtsplraiseipl(ipl_cookie_t icookie) 1751.15Syamt{ 1761.15Syamt 1771.15Syamt return _splraise(icookie._ipl); 1781.15Syamt} 1791.7Sthorpej 1801.7Sthorpej#define spl0() _spllower(IPL_NONE) 1811.7Sthorpej 1821.14Syamt#include <sys/spl.h> 1831.7Sthorpej 1841.10Sthorpej#endif /* ! _LOCORE */ 1851.7Sthorpej 1861.7Sthorpej#endif /* __OLD_INTERRUPT_CODE */ 1871.7Sthorpej 1881.7Sthorpej#endif /* _KERNEL */ 1891.7Sthorpej 1901.7Sthorpej#endif /* _EVBARM_INTR_H_ */ 191