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intmmu.S revision 1.9
      1  1.9  rearnsha /*	$NetBSD: intmmu.S,v 1.9 2005/06/03 15:56:49 rearnsha Exp $ */
      2  1.1  rearnsha 
      3  1.1  rearnsha /*
      4  1.1  rearnsha  * Copyright (c) 2001 ARM Ltd
      5  1.1  rearnsha  * All rights reserved.
      6  1.1  rearnsha  *
      7  1.1  rearnsha  * Redistribution and use in source and binary forms, with or without
      8  1.1  rearnsha  * modification, are permitted provided that the following conditions
      9  1.1  rearnsha  * are met:
     10  1.1  rearnsha  * 1. Redistributions of source code must retain the above copyright
     11  1.1  rearnsha  *    notice, this list of conditions and the following disclaimer.
     12  1.1  rearnsha  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1  rearnsha  *    notice, this list of conditions and the following disclaimer in the
     14  1.1  rearnsha  *    documentation and/or other materials provided with the distribution.
     15  1.1  rearnsha  * 3. The name of the company may not be used to endorse or promote
     16  1.1  rearnsha  *    products derived from this software without specific prior written
     17  1.1  rearnsha  *    permission.
     18  1.1  rearnsha  *
     19  1.1  rearnsha  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     20  1.1  rearnsha  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     21  1.1  rearnsha  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  1.1  rearnsha  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     23  1.1  rearnsha  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     24  1.1  rearnsha  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     25  1.1  rearnsha  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26  1.1  rearnsha  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27  1.1  rearnsha  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28  1.1  rearnsha  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29  1.1  rearnsha  * SUCH DAMAGE.
     30  1.1  rearnsha  */
     31  1.2   thorpej 
     32  1.1  rearnsha #include "assym.h"
     33  1.1  rearnsha #include <machine/asm.h>
     34  1.1  rearnsha #include <arm/armreg.h>
     35  1.2   thorpej #include <arm/arm32/pte.h>
     36  1.1  rearnsha 
     37  1.5  rearnsha 	.section .start,"ax",%progbits
     38  1.1  rearnsha 
     39  1.1  rearnsha ASENTRY_NP(integrator_start)
     40  1.1  rearnsha 	mov	r6, #0x16000000		/* UART0 Physical base*/
     41  1.7  rearnsha #ifdef VERBOSE_INIT_ARM
     42  1.1  rearnsha 	mov	r3, #'A'
     43  1.1  rearnsha 	str	r3, [r6]		/* Let the world know we are alive */
     44  1.7  rearnsha #endif
     45  1.7  rearnsha /*
     46  1.7  rearnsha  * Check that the processor has a CP15.  Some core modules do not.
     47  1.7  rearnsha  * We can tell by reading CM_PROC.  If it is zero, then we're OK, otherwise
     48  1.7  rearnsha  * let the user know why we've died.
     49  1.7  rearnsha  */
     50  1.7  rearnsha 	mov	r7, #0x10000000
     51  1.7  rearnsha 	ldr	r3, [r7, #4]
     52  1.7  rearnsha 	cmp	r3, #0
     53  1.7  rearnsha 	bne	Lno_cp15
     54  1.7  rearnsha /*
     55  1.7  rearnsha  * Now read CP15 and check what sort of core we have.  We need to know
     56  1.7  rearnsha  * if it has an MMU.  There's no simple test for this, but the following
     57  1.9  rearnsha  * hack should be sufficient for all currently supported CM boards:
     58  1.9  rearnsha  *  - Check that the product code has a '2' or '3' in bits 8-11
     59  1.7  rearnsha  */
     60  1.7  rearnsha 	mrc	p15, 0, r3, c0, c0, 0
     61  1.7  rearnsha 	and	r0, r3, #0x00000f00
     62  1.9  rearnsha 	teq	r0, #0x00000200		/* ARM 920, 1020, 1026, etc */
     63  1.9  rearnsha 	teqne	r0, #0x00000300		/* ARM 1136 */
     64  1.7  rearnsha 	bne	Lno_mmu
     65  1.1  rearnsha 
     66  1.1  rearnsha /*
     67  1.1  rearnsha  * At this time the MMU is off.
     68  1.1  rearnsha  * We build up an initial memory map at 0x8000 that we can use to get
     69  1.1  rearnsha  * the kernel running from the top of memory.  All mappings in this table
     70  1.1  rearnsha  * use L1 section maps.
     71  1.1  rearnsha  */
     72  1.1  rearnsha 
     73  1.1  rearnsha /*
     74  1.1  rearnsha  * Set Virtual == Physical
     75  1.1  rearnsha  */
     76  1.4   thorpej 	mov	r3, #(L1_S_AP(AP_KRW))
     77  1.4   thorpej 	add	r3, r3, #(L1_TYPE_S)
     78  1.1  rearnsha 	mov	r2, #0x100000		/* advance by 1MB */
     79  1.1  rearnsha 	mov	r1, #0x8000		/* page table start */
     80  1.1  rearnsha 	mov	r0, #0x1000		/* page table size */
     81  1.1  rearnsha 
     82  1.1  rearnsha Lflat:
     83  1.1  rearnsha 	str	r3, [r1], #0x0004
     84  1.1  rearnsha 	add	r3, r3, r2
     85  1.1  rearnsha 	subs	r0, r0, #1
     86  1.1  rearnsha 	bgt	Lflat
     87  1.1  rearnsha 
     88  1.1  rearnsha /*
     89  1.5  rearnsha  * Map VA 0xc0000000->0xc03fffff to PA 0x00000000->0x003fffff
     90  1.1  rearnsha  */
     91  1.4   thorpej 	mov	r3, #(L1_S_AP(AP_KRW))
     92  1.4   thorpej 	add	r3, r3, #(L1_TYPE_S)
     93  1.1  rearnsha 	mov	r1, #0x8000		/* page table start */
     94  1.3   thorpej 	add	r1, r1, #(0xc00 * 4)	/* offset to 0xc00xxxxx */
     95  1.5  rearnsha #	add	r1, r1, #(0x001 * 4)	/* offset to 0xc01xxxxx */
     96  1.5  rearnsha 	mov	r0, #63
     97  1.1  rearnsha Lkern:
     98  1.5  rearnsha 	str	r3, [r1], #0x0004	/* 0xc000000-0xc03fffff */
     99  1.1  rearnsha 	add	r3, r3, r2
    100  1.1  rearnsha 	subs	r0, r0, #1
    101  1.1  rearnsha 	bgt	Lkern
    102  1.1  rearnsha /*
    103  1.1  rearnsha  * Mapping the peripheral register region (0x10000000->0x1fffffff) linearly
    104  1.1  rearnsha  * would require 256MB of virtual memory (as much space as the entire kernel
    105  1.1  rearnsha  * virtual space).  So we map the first 1M of each 16MB sub-space into the
    106  1.1  rearnsha  * region VA 0xfd000000->0xfdffffff; this should map enough of the peripheral
    107  1.1  rearnsha  * space to at least get us up and running.
    108  1.1  rearnsha  */
    109  1.4   thorpej 	mov	r3, #(L1_S_AP(AP_KRW))
    110  1.4   thorpej 	add	r3, r3, #L1_TYPE_S
    111  1.1  rearnsha 	add	r3, r3, #0x10000000	/* Peripherals base */
    112  1.1  rearnsha 	mov	r1, #0x8000		/* page table start */
    113  1.1  rearnsha 	add	r1, r1, #(0xfd0 * 4)
    114  1.1  rearnsha 	mov	r2, #0x01000000		/* 16MB increment.  */
    115  1.1  rearnsha 	mov	r0, #16
    116  1.1  rearnsha Lperiph:
    117  1.1  rearnsha 	str	r3, [r1], #4		/* 0xfd000000-0xfdffffff */
    118  1.1  rearnsha 	add	r3, r3, r2
    119  1.1  rearnsha 	subs	r0, r0, #1
    120  1.1  rearnsha 	bgt	Lperiph
    121  1.1  rearnsha 
    122  1.1  rearnsha /*
    123  1.1  rearnsha  * We now have our page table ready, so load it up and light the blue
    124  1.1  rearnsha  * touch paper.
    125  1.1  rearnsha  */
    126  1.1  rearnsha 
    127  1.1  rearnsha 	/* set the location of the L1 page table */
    128  1.1  rearnsha 	mov	r1, #0x8000
    129  1.1  rearnsha 	mcr	p15, 0, r1, c2, c0, 0
    130  1.1  rearnsha 
    131  1.1  rearnsha 	/* Flush the old TLBs (just in case) */
    132  1.1  rearnsha 	mcr	p15, 0, r1, c8, c7, 0
    133  1.9  rearnsha 	/* And the caches */
    134  1.9  rearnsha 	mov	r0, #0
    135  1.9  rearnsha 	mcr	p15, 0, r1, c7, c6, 0
    136  1.9  rearnsha 
    137  1.7  rearnsha #ifdef VERBOSE_INIT_ARM
    138  1.1  rearnsha 	mov	r2, #'B'
    139  1.1  rearnsha 	strb	r2, [r6]
    140  1.7  rearnsha #endif
    141  1.1  rearnsha 
    142  1.1  rearnsha 	/* Set the Domain Access register.  Very important! */
    143  1.1  rearnsha 	mov	r1, #1
    144  1.1  rearnsha 	mcr	p15, 0, r1, c3, c0, 0
    145  1.1  rearnsha 
    146  1.1  rearnsha 	/*
    147  1.1  rearnsha 	 * set mmu bit (don't set anything else for now, we don't know
    148  1.1  rearnsha 	 * what sort of CPU we have yet.
    149  1.1  rearnsha 	 */
    150  1.1  rearnsha 	mov	r1, #CPU_CONTROL_MMU_ENABLE
    151  1.1  rearnsha 
    152  1.1  rearnsha /*
    153  1.6       wiz  * This is where it might all start to go wrong if the CPU fitted to your
    154  1.1  rearnsha  * integrator does not have an MMU.
    155  1.1  rearnsha  */
    156  1.1  rearnsha 	/* fetch current control state */
    157  1.1  rearnsha 	mrc	p15, 0, r2, c1, c0, 0
    158  1.1  rearnsha 	orr	r2, r2, r1
    159  1.1  rearnsha 
    160  1.1  rearnsha 	/* set new control state */
    161  1.1  rearnsha 	mcr	p15, 0, r2, c1, c0, 0
    162  1.1  rearnsha 
    163  1.1  rearnsha 	mov	r0, r0
    164  1.1  rearnsha 	mov	r0, r0
    165  1.1  rearnsha 	mov	r0, r0
    166  1.1  rearnsha 
    167  1.7  rearnsha #ifdef VERBOSE_INIT_ARM
    168  1.1  rearnsha 	/* emit a char.  Uart is now at 0xfd600000 */
    169  1.1  rearnsha 	mov	r6, #0xfd000000
    170  1.1  rearnsha 	add	r6, r6, #0x00600000
    171  1.1  rearnsha 	mov	r2, #'C'
    172  1.1  rearnsha 	strb	r2, [r6]
    173  1.7  rearnsha #endif
    174  1.1  rearnsha 
    175  1.1  rearnsha 	/* jump to kernel space */
    176  1.1  rearnsha 	mov	r0, #0x0200
    177  1.1  rearnsha 
    178  1.1  rearnsha 	/* Switch to kernel VM and really set the ball rolling.  */
    179  1.1  rearnsha 	ldr	pc, Lstart
    180  1.1  rearnsha 
    181  1.1  rearnsha Lstart:	.long	start
    182  1.7  rearnsha 
    183  1.7  rearnsha Lmsg:
    184  1.7  rearnsha 	ldrb	r2, [r0], #1
    185  1.7  rearnsha 	cmp	r2, #0
    186  1.7  rearnsha 	strneb	r2, [r6]
    187  1.7  rearnsha Lwait:
    188  1.7  rearnsha 	ldrb	r3, [r6, #0x18]
    189  1.7  rearnsha 	tst	r3, #0x80
    190  1.7  rearnsha 	beq	Lwait
    191  1.7  rearnsha 	cmp	r2, #0
    192  1.7  rearnsha 	bne	Lmsg
    193  1.7  rearnsha 	/* We're toast! */
    194  1.7  rearnsha 	b	.
    195  1.7  rearnsha 
    196  1.7  rearnsha Lno_cp15:
    197  1.7  rearnsha 	adr	r0, Lcp15msg
    198  1.7  rearnsha 	b	Lmsg
    199  1.7  rearnsha Lno_mmu:
    200  1.7  rearnsha 	adr	r0, Lmmumsg
    201  1.7  rearnsha 	b	Lmsg
    202  1.7  rearnsha 
    203  1.7  rearnsha Lcp15msg:
    204  1.7  rearnsha 	.ascii "Core has no cp15\r\n\0"
    205  1.7  rearnsha Lmmumsg:
    206  1.7  rearnsha 	.ascii "Core has no MMU\r\n\0"
    207