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intmmu.S revision 1.1 
      1 /*	$NetBSD: intmmu.S,v 1.1 2001/10/27 16:17:52 rearnsha Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2001 ARM Ltd
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. The name of the company may not be used to endorse or promote
     16  *    products derived from this software without specific prior written
     17  *    permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     20  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     21  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29  * SUCH DAMAGE.
     30  */
     31 #include "assym.h"
     32 #include <machine/asm.h>
     33 #include <arm/armreg.h>
     34 #include <arm/pte.h>
     35 
     36 	.text
     37 
     38 ASENTRY_NP(integrator_start)
     39 	mov	r6, #0x16000000		/* UART0 Physical base*/
     40 	mov	r3, #'A'
     41 	str	r3, [r6]		/* Let the world know we are alive */
     42 
     43 /*
     44  * At this time the MMU is off.
     45  * We build up an initial memory map at 0x8000 that we can use to get
     46  * the kernel running from the top of memory.  All mappings in this table
     47  * use L1 section maps.
     48  */
     49 
     50 /*
     51  * Set Virtual == Physical
     52  */
     53 	mov	r3, #(AP_KRW << AP_SECTION_SHIFT)
     54 	add	r3, r3, #(L1_SECTION)
     55 	mov	r2, #0x100000		/* advance by 1MB */
     56 	mov	r1, #0x8000		/* page table start */
     57 	mov	r0, #0x1000		/* page table size */
     58 
     59 Lflat:
     60 	str	r3, [r1], #0x0004
     61 	add	r3, r3, r2
     62 	subs	r0, r0, #1
     63 	bgt	Lflat
     64 
     65 /*
     66  * Map VA 0xa0100000->0xa03fffff to PA 0x00000000->0x002fffff
     67  */
     68 	mov	r3, #(AP_KRW << AP_SECTION_SHIFT)
     69 	add	r3, r3, #(L1_SECTION)
     70 	mov	r1, #0x8000		/* page table start */
     71 	add	r1, r1, #(0xa00 * 4)	/* offset to 0xa00xxxxx */
     72 	add	r1, r1, #(0x001 * 4)	/* offset to 0xa01xxxxx */
     73 	mov	r0, #47
     74 Lkern:
     75 	str	r3, [r1], #0x0004	/* 0xa010000-0xa03fffff */
     76 	add	r3, r3, r2
     77 	subs	r0, r0, #1
     78 	bgt	Lkern
     79 /*
     80  * Mapping the peripheral register region (0x10000000->0x1fffffff) linearly
     81  * would require 256MB of virtual memory (as much space as the entire kernel
     82  * virtual space).  So we map the first 1M of each 16MB sub-space into the
     83  * region VA 0xfd000000->0xfdffffff; this should map enough of the peripheral
     84  * space to at least get us up and running.
     85  */
     86 	mov	r3, #(AP_KRW << AP_SECTION_SHIFT)
     87 	add	r3, r3, #L1_SECTION
     88 	add	r3, r3, #0x10000000	/* Peripherals base */
     89 	mov	r1, #0x8000		/* page table start */
     90 	add	r1, r1, #(0xfd0 * 4)
     91 	mov	r2, #0x01000000		/* 16MB increment.  */
     92 	mov	r0, #16
     93 Lperiph:
     94 	str	r3, [r1], #4		/* 0xfd000000-0xfdffffff */
     95 	add	r3, r3, r2
     96 	subs	r0, r0, #1
     97 	bgt	Lperiph
     98 
     99 /*
    100  * We now have our page table ready, so load it up and light the blue
    101  * touch paper.
    102  */
    103 
    104 	/* set the location of the L1 page table */
    105 	mov	r1, #0x8000
    106 	mcr	p15, 0, r1, c2, c0, 0
    107 
    108 	/* Flush the old TLBs (just in case) */
    109 	mcr	p15, 0, r1, c8, c7, 0
    110 	mov	r2, #'B'
    111 	strb	r2, [r6]
    112 
    113 	/* Set the Domain Access register.  Very important! */
    114 	mov	r1, #1
    115 	mcr	p15, 0, r1, c3, c0, 0
    116 
    117 	/*
    118 	 * set mmu bit (don't set anything else for now, we don't know
    119 	 * what sort of CPU we have yet.
    120 	 */
    121 	mov	r1, #CPU_CONTROL_MMU_ENABLE
    122 
    123 /*
    124  * This is where it might all start to go wrong if the cpu fitted to your
    125  * integrator does not have an MMU.
    126  */
    127 	/* fetch current control state */
    128 	mrc	p15, 0, r2, c1, c0, 0
    129 	orr	r2, r2, r1
    130 
    131 	/* set new control state */
    132 	mcr	p15, 0, r2, c1, c0, 0
    133 
    134 	mov	r0, r0
    135 	mov	r0, r0
    136 	mov	r0, r0
    137 
    138 	/* emit a char.  Uart is now at 0xfd600000 */
    139 	mov	r6, #0xfd000000
    140 	add	r6, r6, #0x00600000
    141 	mov	r2, #'C'
    142 	strb	r2, [r6]
    143 
    144 	/* jump to kernel space */
    145 	mov	r0, #0x0200
    146 
    147 	/* Switch to kernel VM and really set the ball rolling.  */
    148 	ldr	pc, Lstart
    149 
    150 Lstart:	.long	start
    151