iq80310_intr.c revision 1.18
1 /* $NetBSD: iq80310_intr.c,v 1.18 2002/10/09 00:03:42 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef EVBARM_SPL_NOINLINE 39 #define EVBARM_SPL_NOINLINE 40 #endif 41 42 /* 43 * Interrupt support for the Intel IQ80310. 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 50 #include <uvm/uvm_extern.h> 51 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 55 #include <arm/cpufunc.h> 56 57 #include <arm/xscale/i80200reg.h> 58 #include <arm/xscale/i80200var.h> 59 60 #include <evbarm/iq80310/iq80310reg.h> 61 #include <evbarm/iq80310/iq80310var.h> 62 #include <evbarm/iq80310/obiovar.h> 63 64 /* Interrupt handler queues. */ 65 struct intrq intrq[NIRQ]; 66 67 /* Interrupts to mask at each level. */ 68 int iq80310_imask[NIPL]; 69 70 /* Current interrupt priority level. */ 71 __volatile int current_spl_level; 72 73 /* Interrupts pending. */ 74 __volatile int iq80310_ipending; 75 76 /* Software copy of the IRQs we have enabled. */ 77 uint32_t intr_enabled; 78 79 /* 80 * Map a software interrupt queue index (at the top of the word, and 81 * highest priority softintr is encountered first in an ffs()). 82 */ 83 #define SI_TO_IRQBIT(si) (1U << (31 - (si))) 84 85 /* 86 * Map a software interrupt queue to an interrupt priority level. 87 */ 88 static const int si_to_ipl[SI_NQUEUES] = { 89 IPL_SOFT, /* SI_SOFT */ 90 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 91 IPL_SOFTNET, /* SI_SOFTNET */ 92 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 93 }; 94 95 void iq80310_intr_dispatch(struct clockframe *frame); 96 97 static __inline uint32_t 98 iq80310_intstat_read(void) 99 { 100 uint32_t intstat; 101 102 intstat = CPLD_READ(IQ80310_XINT3_STATUS) & 0x1f; 103 #if defined(IRQ_READ_XINT0) 104 if (IRQ_READ_XINT0) 105 intstat |= (CPLD_READ(IQ80310_XINT0_STATUS) & 0x7) << 5; 106 #endif 107 108 /* XXX Why do we have to mask off? */ 109 return (intstat & intr_enabled); 110 } 111 112 static __inline void 113 iq80310_set_intrmask(void) 114 { 115 uint32_t disabled; 116 117 intr_enabled |= IRQ_BITS_ALWAYS_ON; 118 119 /* The XINT_MASK register sets a bit to *disable*. */ 120 disabled = (~intr_enabled) & IRQ_BITS; 121 122 CPLD_WRITE(IQ80310_XINT_MASK, disabled & 0x1f); 123 } 124 125 static __inline void 126 iq80310_enable_irq(int irq) 127 { 128 129 intr_enabled |= (1U << irq); 130 iq80310_set_intrmask(); 131 } 132 133 static __inline void 134 iq80310_disable_irq(int irq) 135 { 136 137 intr_enabled &= ~(1U << irq); 138 iq80310_set_intrmask(); 139 } 140 141 /* 142 * NOTE: This routine must be called with interrupts disabled in the CPSR. 143 */ 144 static void 145 iq80310_intr_calculate_masks(void) 146 { 147 struct intrq *iq; 148 struct intrhand *ih; 149 int irq, ipl; 150 151 /* First, figure out which IPLs each IRQ has. */ 152 for (irq = 0; irq < NIRQ; irq++) { 153 int levels = 0; 154 iq = &intrq[irq]; 155 iq80310_disable_irq(irq); 156 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 157 ih = TAILQ_NEXT(ih, ih_list)) 158 levels |= (1U << ih->ih_ipl); 159 iq->iq_levels = levels; 160 } 161 162 /* Next, figure out which IRQs are used by each IPL. */ 163 for (ipl = 0; ipl < NIPL; ipl++) { 164 int irqs = 0; 165 for (irq = 0; irq < NIRQ; irq++) { 166 if (intrq[irq].iq_levels & (1U << ipl)) 167 irqs |= (1U << irq); 168 } 169 iq80310_imask[ipl] = irqs; 170 } 171 172 iq80310_imask[IPL_NONE] = 0; 173 174 /* 175 * Initialize the soft interrupt masks to block themselves. 176 */ 177 iq80310_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 178 iq80310_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 179 iq80310_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 180 iq80310_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 181 182 /* 183 * splsoftclock() is the only interface that users of the 184 * generic software interrupt facility have to block their 185 * soft intrs, so splsoftclock() must also block IPL_SOFT. 186 */ 187 iq80310_imask[IPL_SOFTCLOCK] |= iq80310_imask[IPL_SOFT]; 188 189 /* 190 * splsoftnet() must also block splsoftclock(), since we don't 191 * want timer-driven network events to occur while we're 192 * processing incoming packets. 193 */ 194 iq80310_imask[IPL_SOFTNET] |= iq80310_imask[IPL_SOFTCLOCK]; 195 196 /* 197 * Enforce a heirarchy that gives "slow" device (or devices with 198 * limited input buffer space/"real-time" requirements) a better 199 * chance at not dropping data. 200 */ 201 iq80310_imask[IPL_BIO] |= iq80310_imask[IPL_SOFTNET]; 202 iq80310_imask[IPL_NET] |= iq80310_imask[IPL_BIO]; 203 iq80310_imask[IPL_SOFTSERIAL] |= iq80310_imask[IPL_NET]; 204 iq80310_imask[IPL_TTY] |= iq80310_imask[IPL_SOFTSERIAL]; 205 206 /* 207 * splvm() blocks all interrupts that use the kernel memory 208 * allocation facilities. 209 */ 210 iq80310_imask[IPL_IMP] |= iq80310_imask[IPL_TTY]; 211 212 /* 213 * Audio devices are not allowed to perform memory allocation 214 * in their interrupt routines, and they have fairly "real-time" 215 * requirements, so give them a high interrupt priority. 216 */ 217 iq80310_imask[IPL_AUDIO] |= iq80310_imask[IPL_IMP]; 218 219 /* 220 * splclock() must block anything that uses the scheduler. 221 */ 222 iq80310_imask[IPL_CLOCK] |= iq80310_imask[IPL_AUDIO]; 223 224 /* 225 * No separate statclock on the IQ80310. 226 */ 227 iq80310_imask[IPL_STATCLOCK] |= iq80310_imask[IPL_CLOCK]; 228 229 /* 230 * splhigh() must block "everything". 231 */ 232 iq80310_imask[IPL_HIGH] |= iq80310_imask[IPL_STATCLOCK]; 233 234 /* 235 * XXX We need serial drivers to run at the absolute highest priority 236 * in order to avoid overruns, so serial > high. 237 */ 238 iq80310_imask[IPL_SERIAL] |= iq80310_imask[IPL_HIGH]; 239 240 /* 241 * Now compute which IRQs must be blocked when servicing any 242 * given IRQ. 243 */ 244 for (irq = 0; irq < NIRQ; irq++) { 245 int irqs = (1U << irq); 246 iq = &intrq[irq]; 247 if (TAILQ_FIRST(&iq->iq_list) != NULL) 248 iq80310_enable_irq(irq); 249 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 250 ih = TAILQ_NEXT(ih, ih_list)) 251 irqs |= iq80310_imask[ih->ih_ipl]; 252 iq->iq_mask = irqs; 253 } 254 } 255 256 void 257 iq80310_do_soft(void) 258 { 259 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 260 int new, oldirqstate; 261 262 if (__cpu_simple_lock_try(&processing) == 0) 263 return; 264 265 new = current_spl_level; 266 267 oldirqstate = disable_interrupts(I32_bit); 268 269 #define DO_SOFTINT(si) \ 270 if ((iq80310_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 271 iq80310_ipending &= ~SI_TO_IRQBIT(si); \ 272 current_spl_level |= iq80310_imask[si_to_ipl[(si)]]; \ 273 restore_interrupts(oldirqstate); \ 274 softintr_dispatch(si); \ 275 oldirqstate = disable_interrupts(I32_bit); \ 276 current_spl_level = new; \ 277 } 278 279 DO_SOFTINT(SI_SOFTSERIAL); 280 DO_SOFTINT(SI_SOFTNET); 281 DO_SOFTINT(SI_SOFTCLOCK); 282 DO_SOFTINT(SI_SOFT); 283 284 __cpu_simple_unlock(&processing); 285 286 restore_interrupts(oldirqstate); 287 } 288 289 int 290 _splraise(int ipl) 291 { 292 293 return (iq80310_splraise(ipl)); 294 } 295 296 __inline void 297 splx(int new) 298 { 299 300 return (iq80310_splx(new)); 301 } 302 303 int 304 _spllower(int ipl) 305 { 306 307 return (iq80310_spllower(ipl)); 308 } 309 310 void 311 _setsoftintr(int si) 312 { 313 int oldirqstate; 314 315 oldirqstate = disable_interrupts(I32_bit); 316 iq80310_ipending |= SI_TO_IRQBIT(si); 317 restore_interrupts(oldirqstate); 318 319 /* Process unmasked pending soft interrupts. */ 320 if ((iq80310_ipending & ~IRQ_BITS) & ~current_spl_level) 321 iq80310_do_soft(); 322 } 323 324 void 325 iq80310_intr_init(void) 326 { 327 struct intrq *iq; 328 int i; 329 330 /* 331 * The Secondary PCI interrupts INTA, INTB, and INTC 332 * area always enabled, since they cannot be masked 333 * in the CPLD. 334 */ 335 intr_enabled |= IRQ_BITS_ALWAYS_ON; 336 337 for (i = 0; i < NIRQ; i++) { 338 iq = &intrq[i]; 339 TAILQ_INIT(&iq->iq_list); 340 341 sprintf(iq->iq_name, "irq %d", i); 342 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 343 NULL, "iq80310", iq->iq_name); 344 } 345 346 iq80310_intr_calculate_masks(); 347 348 /* Enable external interrupts on the i80200. */ 349 i80200_extirq_dispatch = iq80310_intr_dispatch; 350 i80200_intr_enable(INTCTL_IM | INTCTL_PM); 351 352 /* Enable IRQs (don't yet use FIQs). */ 353 enable_interrupts(I32_bit); 354 } 355 356 void * 357 iq80310_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 358 { 359 struct intrq *iq; 360 struct intrhand *ih; 361 u_int oldirqstate; 362 363 if (irq < 0 || irq > NIRQ) 364 panic("iq80310_intr_establish: IRQ %d out of range", irq); 365 366 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 367 if (ih == NULL) 368 return (NULL); 369 370 ih->ih_func = func; 371 ih->ih_arg = arg; 372 ih->ih_ipl = ipl; 373 ih->ih_irq = irq; 374 375 iq = &intrq[irq]; 376 377 /* All IQ80310 interrupts are level-triggered. */ 378 iq->iq_ist = IST_LEVEL; 379 380 oldirqstate = disable_interrupts(I32_bit); 381 382 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 383 384 iq80310_intr_calculate_masks(); 385 386 restore_interrupts(oldirqstate); 387 388 return (ih); 389 } 390 391 void 392 iq80310_intr_disestablish(void *cookie) 393 { 394 struct intrhand *ih = cookie; 395 struct intrq *iq = &intrq[ih->ih_irq]; 396 int oldirqstate; 397 398 oldirqstate = disable_interrupts(I32_bit); 399 400 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 401 402 iq80310_intr_calculate_masks(); 403 404 restore_interrupts(oldirqstate); 405 } 406 407 void 408 iq80310_intr_dispatch(struct clockframe *frame) 409 { 410 struct intrq *iq; 411 struct intrhand *ih; 412 int oldirqstate, pcpl, irq, ibit, hwpend, rv, stray; 413 414 stray = 1; 415 416 /* First, disable external IRQs. */ 417 i80200_intr_disable(INTCTL_IM | INTCTL_PM); 418 419 pcpl = current_spl_level; 420 421 for (hwpend = iq80310_intstat_read(); hwpend != 0;) { 422 irq = ffs(hwpend) - 1; 423 ibit = (1U << irq); 424 425 stray = 0; 426 427 hwpend &= ~ibit; 428 429 if (pcpl & ibit) { 430 /* 431 * IRQ is masked; mark it as pending and check 432 * the next one. Note: external IRQs are already 433 * disabled. 434 */ 435 iq80310_ipending |= ibit; 436 continue; 437 } 438 439 iq80310_ipending &= ~ibit; 440 rv = 0; 441 442 iq = &intrq[irq]; 443 iq->iq_ev.ev_count++; 444 uvmexp.intrs++; 445 current_spl_level |= iq->iq_mask; 446 oldirqstate = enable_interrupts(I32_bit); 447 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 448 ih = TAILQ_NEXT(ih, ih_list)) { 449 rv |= (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 450 } 451 restore_interrupts(oldirqstate); 452 453 current_spl_level = pcpl; 454 455 #if 0 /* XXX */ 456 if (rv == 0) 457 printf("Stray interrupt: IRQ %d\n", irq); 458 #endif 459 } 460 461 #if 0 /* XXX */ 462 if (stray) 463 printf("Stray external interrupt\n"); 464 #endif 465 466 /* Check for pendings soft intrs. */ 467 if ((iq80310_ipending & ~IRQ_BITS) & ~current_spl_level) { 468 oldirqstate = enable_interrupts(I32_bit); 469 iq80310_do_soft(); 470 restore_interrupts(oldirqstate); 471 } 472 473 /* 474 * If no hardware interrupts are masked, re-enable external 475 * interrupts. 476 */ 477 if ((iq80310_ipending & IRQ_BITS) == 0) 478 i80200_intr_enable(INTCTL_IM | INTCTL_PM); 479 } 480
Indexes created Wed Oct 01 13:09:50 GMT 2025