iq80310_intr.c revision 1.26
1 /* $NetBSD: iq80310_intr.c,v 1.26 2008/04/27 18:58:46 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: iq80310_intr.c,v 1.26 2008/04/27 18:58:46 matt Exp $"); 40 41 #ifndef EVBARM_SPL_NOINLINE 42 #define EVBARM_SPL_NOINLINE 43 #endif 44 45 /* 46 * Interrupt support for the Intel IQ80310. 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/malloc.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 58 #include <arm/cpufunc.h> 59 60 #include <arm/xscale/i80200reg.h> 61 #include <arm/xscale/i80200var.h> 62 63 #include <evbarm/iq80310/iq80310reg.h> 64 #include <evbarm/iq80310/iq80310var.h> 65 #include <evbarm/iq80310/obiovar.h> 66 67 /* Interrupt handler queues. */ 68 struct intrq intrq[NIRQ]; 69 70 /* Interrupts to mask at each level. */ 71 int iq80310_imask[NIPL]; 72 73 /* Interrupts pending. */ 74 volatile int iq80310_ipending; 75 76 /* Software copy of the IRQs we have enabled. */ 77 uint32_t intr_enabled; 78 79 #ifdef __HAVE_FAST_SOFTINTRS 80 /* 81 * Map a software interrupt queue index (at the top of the word, and 82 * highest priority softintr is encountered first in an ffs()). 83 */ 84 #define SI_TO_IRQBIT(si) (1U << (31 - (si))) 85 86 /* 87 * Map a software interrupt queue to an interrupt priority level. 88 */ 89 static const int si_to_ipl[SI_NQUEUES] = { 90 IPL_SOFT, /* SI_SOFT */ 91 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 92 IPL_SOFTNET, /* SI_SOFTNET */ 93 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 94 }; 95 #endif 96 97 void iq80310_intr_dispatch(struct irqframe *frame); 98 99 static inline uint32_t 100 iq80310_intstat_read(void) 101 { 102 uint32_t intstat; 103 104 intstat = CPLD_READ(IQ80310_XINT3_STATUS) & 0x1f; 105 #if defined(IRQ_READ_XINT0) 106 if (IRQ_READ_XINT0) 107 intstat |= (CPLD_READ(IQ80310_XINT0_STATUS) & 0x7) << 5; 108 #endif 109 110 /* XXX Why do we have to mask off? */ 111 return (intstat & intr_enabled); 112 } 113 114 static inline void 115 iq80310_set_intrmask(void) 116 { 117 uint32_t disabled; 118 119 intr_enabled |= IRQ_BITS_ALWAYS_ON; 120 121 /* The XINT_MASK register sets a bit to *disable*. */ 122 disabled = (~intr_enabled) & IRQ_BITS; 123 124 CPLD_WRITE(IQ80310_XINT_MASK, disabled & 0x1f); 125 } 126 127 static inline void 128 iq80310_enable_irq(int irq) 129 { 130 131 intr_enabled |= (1U << irq); 132 iq80310_set_intrmask(); 133 } 134 135 static inline void 136 iq80310_disable_irq(int irq) 137 { 138 139 intr_enabled &= ~(1U << irq); 140 iq80310_set_intrmask(); 141 } 142 143 /* 144 * NOTE: This routine must be called with interrupts disabled in the CPSR. 145 */ 146 static void 147 iq80310_intr_calculate_masks(void) 148 { 149 struct intrq *iq; 150 struct intrhand *ih; 151 int irq, ipl; 152 153 /* First, figure out which IPLs each IRQ has. */ 154 for (irq = 0; irq < NIRQ; irq++) { 155 int levels = 0; 156 iq = &intrq[irq]; 157 iq80310_disable_irq(irq); 158 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 159 ih = TAILQ_NEXT(ih, ih_list)) 160 levels |= (1U << ih->ih_ipl); 161 iq->iq_levels = levels; 162 } 163 164 /* Next, figure out which IRQs are used by each IPL. */ 165 for (ipl = 0; ipl < NIPL; ipl++) { 166 int irqs = 0; 167 for (irq = 0; irq < NIRQ; irq++) { 168 if (intrq[irq].iq_levels & (1U << ipl)) 169 irqs |= (1U << irq); 170 } 171 iq80310_imask[ipl] = irqs; 172 } 173 174 iq80310_imask[IPL_NONE] = 0; 175 iq80310_imask[IPL_SOFTCLOCK] = 0; 176 iq80310_imask[IPL_SOFTNET] = 0; 177 iq80310_imask[IPL_SOFTSERIAL] = 0; 178 179 /* 180 * splsoftnet() must also block splsoftclock(), since we don't 181 * want timer-driven network events to occur while we're 182 * processing incoming packets. 183 */ 184 iq80310_imask[IPL_SOFTNET] |= iq80310_imask[IPL_SOFTCLOCK]; 185 186 /* 187 * Enforce a hierarchy that gives "slow" device (or devices with 188 * limited input buffer space/"real-time" requirements) a better 189 * chance at not dropping data. 190 */ 191 iq80310_imask[IPL_BIO] |= iq80310_imask[IPL_SOFTNET]; 192 iq80310_imask[IPL_NET] |= iq80310_imask[IPL_BIO]; 193 iq80310_imask[IPL_SOFTSERIAL] |= iq80310_imask[IPL_NET]; 194 iq80310_imask[IPL_TTY] |= iq80310_imask[IPL_SOFTSERIAL]; 195 196 /* 197 * splvm() blocks all interrupts that use the kernel memory 198 * allocation facilities. 199 */ 200 iq80310_imask[IPL_VM] |= iq80310_imask[IPL_TTY]; 201 202 /* 203 * Audio devices are not allowed to perform memory allocation 204 * in their interrupt routines, and they have fairly "real-time" 205 * requirements, so give them a high interrupt priority. 206 */ 207 iq80310_imask[IPL_AUDIO] |= iq80310_imask[IPL_VM]; 208 209 /* 210 * splclock() must block anything that uses the scheduler. 211 */ 212 iq80310_imask[IPL_CLOCK] |= iq80310_imask[IPL_AUDIO]; 213 214 /* 215 * No separate statclock on the IQ80310. 216 */ 217 #ifdef IPL_STATCLOCK 218 iq80310_imask[IPL_STATCLOCK] |= iq80310_imask[IPL_CLOCK]; 219 #endif 220 221 /* 222 * splhigh() must block "everything". 223 */ 224 #ifdef IPL_STATCLOCK 225 iq80310_imask[IPL_HIGH] |= iq80310_imask[IPL_STATCLOCK]; 226 #else 227 iq80310_imask[IPL_HIGH] |= iq80310_imask[IPL_CLOCK]; 228 #endif 229 230 /* 231 * XXX We need serial drivers to run at the absolute highest priority 232 * in order to avoid overruns, so serial > high. 233 */ 234 iq80310_imask[IPL_SERIAL] |= iq80310_imask[IPL_HIGH]; 235 236 /* 237 * Now compute which IRQs must be blocked when servicing any 238 * given IRQ. 239 */ 240 for (irq = 0; irq < NIRQ; irq++) { 241 int irqs = (1U << irq); 242 iq = &intrq[irq]; 243 if (TAILQ_FIRST(&iq->iq_list) != NULL) 244 iq80310_enable_irq(irq); 245 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 246 ih = TAILQ_NEXT(ih, ih_list)) 247 irqs |= iq80310_imask[ih->ih_ipl]; 248 iq->iq_mask = irqs; 249 } 250 } 251 252 #ifdef __HAVE_FAST_SOFTINTRS 253 void 254 iq80310_do_soft(void) 255 { 256 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 257 struct cpu_info * const ci = curcpu(); 258 int new, oldirqstate; 259 260 if (__cpu_simple_lock_try(&processing) == 0) 261 return; 262 263 new = ci->ci_cpl; 264 265 oldirqstate = disable_interrupts(I32_bit); 266 267 #define DO_SOFTINT(si) \ 268 if ((iq80310_ipending & ~new) & SI_TO_IRQBIT(si)) { \ 269 iq80310_ipending &= ~SI_TO_IRQBIT(si); \ 270 ci->ci_cpl |= iq80310_imask[si_to_ipl[(si)]]; \ 271 restore_interrupts(oldirqstate); \ 272 softintr_dispatch(si); \ 273 oldirqstate = disable_interrupts(I32_bit); \ 274 ci->ci_cpl = new; \ 275 } 276 277 DO_SOFTINT(SI_SOFTSERIAL); 278 DO_SOFTINT(SI_SOFTNET); 279 DO_SOFTINT(SI_SOFTCLOCK); 280 DO_SOFTINT(SI_SOFT); 281 282 __cpu_simple_unlock(&processing); 283 284 restore_interrupts(oldirqstate); 285 } 286 #endif /* __HAVE_SOFT_FASTINTRS */ 287 288 int 289 _splraise(int ipl) 290 { 291 292 return (iq80310_splraise(ipl)); 293 } 294 295 inline void 296 splx(int new) 297 { 298 299 return (iq80310_splx(new)); 300 } 301 302 int 303 _spllower(int ipl) 304 { 305 306 return (iq80310_spllower(ipl)); 307 } 308 309 #ifdef __HAVE_FAST_SOFTINTRS 310 void 311 _setsoftintr(int si) 312 { 313 int oldirqstate; 314 315 oldirqstate = disable_interrupts(I32_bit); 316 iq80310_ipending |= SI_TO_IRQBIT(si); 317 restore_interrupts(oldirqstate); 318 319 /* Process unmasked pending soft interrupts. */ 320 if ((iq80310_ipending & ~IRQ_BITS) & ~curcpl()) 321 iq80310_do_soft(); 322 } 323 #endif 324 325 void 326 iq80310_intr_init(void) 327 { 328 struct intrq *iq; 329 int i; 330 331 /* 332 * The Secondary PCI interrupts INTA, INTB, and INTC 333 * area always enabled, since they cannot be masked 334 * in the CPLD. 335 */ 336 intr_enabled |= IRQ_BITS_ALWAYS_ON; 337 338 for (i = 0; i < NIRQ; i++) { 339 iq = &intrq[i]; 340 TAILQ_INIT(&iq->iq_list); 341 342 sprintf(iq->iq_name, "irq %d", i); 343 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 344 NULL, "iq80310", iq->iq_name); 345 } 346 347 iq80310_intr_calculate_masks(); 348 349 /* Enable external interrupts on the i80200. */ 350 i80200_extirq_dispatch = iq80310_intr_dispatch; 351 i80200_intr_enable(INTCTL_IM | INTCTL_PM); 352 353 /* Enable IRQs (don't yet use FIQs). */ 354 enable_interrupts(I32_bit); 355 } 356 357 void * 358 iq80310_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 359 { 360 struct intrq *iq; 361 struct intrhand *ih; 362 u_int oldirqstate; 363 364 if (irq < 0 || irq > NIRQ) 365 panic("iq80310_intr_establish: IRQ %d out of range", irq); 366 367 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 368 if (ih == NULL) 369 return (NULL); 370 371 ih->ih_func = func; 372 ih->ih_arg = arg; 373 ih->ih_ipl = ipl; 374 ih->ih_irq = irq; 375 376 iq = &intrq[irq]; 377 378 /* All IQ80310 interrupts are level-triggered. */ 379 iq->iq_ist = IST_LEVEL; 380 381 oldirqstate = disable_interrupts(I32_bit); 382 383 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 384 385 iq80310_intr_calculate_masks(); 386 387 restore_interrupts(oldirqstate); 388 389 return (ih); 390 } 391 392 void 393 iq80310_intr_disestablish(void *cookie) 394 { 395 struct intrhand *ih = cookie; 396 struct intrq *iq = &intrq[ih->ih_irq]; 397 int oldirqstate; 398 399 oldirqstate = disable_interrupts(I32_bit); 400 401 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 402 403 iq80310_intr_calculate_masks(); 404 405 restore_interrupts(oldirqstate); 406 } 407 408 void 409 iq80310_intr_dispatch(struct irqframe *frame) 410 { 411 struct intrq *iq; 412 struct intrhand *ih; 413 int oldirqstate, pcpl, irq, ibit, hwpend, rv, stray; 414 struct cpu_info * const ci = curcpu(); 415 416 stray = 1; 417 418 /* First, disable external IRQs. */ 419 i80200_intr_disable(INTCTL_IM | INTCTL_PM); 420 421 pcpl = ci->ci_cpl; 422 423 for (hwpend = iq80310_intstat_read(); hwpend != 0;) { 424 irq = ffs(hwpend) - 1; 425 ibit = (1U << irq); 426 427 stray = 0; 428 429 hwpend &= ~ibit; 430 431 if (pcpl & ibit) { 432 /* 433 * IRQ is masked; mark it as pending and check 434 * the next one. Note: external IRQs are already 435 * disabled. 436 */ 437 iq80310_ipending |= ibit; 438 continue; 439 } 440 441 iq80310_ipending &= ~ibit; 442 rv = 0; 443 444 iq = &intrq[irq]; 445 iq->iq_ev.ev_count++; 446 uvmexp.intrs++; 447 ci->ci_cpl |= iq->iq_mask; 448 oldirqstate = enable_interrupts(I32_bit); 449 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 450 ih = TAILQ_NEXT(ih, ih_list)) { 451 rv |= (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 452 } 453 restore_interrupts(oldirqstate); 454 455 ci->ci_cpl = pcpl; 456 457 #if 0 /* XXX */ 458 if (rv == 0) 459 printf("Stray interrupt: IRQ %d\n", irq); 460 #endif 461 } 462 463 #if 0 /* XXX */ 464 if (stray) 465 printf("Stray external interrupt\n"); 466 #endif 467 468 #ifdef __HAVE_FAST_SOFTINTS 469 /* Check for pendings soft intrs. */ 470 if ((iq80310_ipending & ~IRQ_BITS) & ~ci->ci_cpl) { 471 oldirqstate = enable_interrupts(I32_bit); 472 iq80310_do_soft(); 473 restore_interrupts(oldirqstate); 474 } 475 #endif 476 477 /* 478 * If no hardware interrupts are masked, re-enable external 479 * interrupts. 480 */ 481 if ((iq80310_ipending & IRQ_BITS) == 0) 482 i80200_intr_enable(INTCTL_IM | INTCTL_PM); 483 } 484
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