iq80310_intr.c revision 1.5
1 /* $NetBSD: iq80310_intr.c,v 1.5 2001/11/23 19:36:50 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Interrupt support for the Intel IQ80310. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 #include <machine/cpu.h> 49 #include <arm/cpufunc.h> 50 51 #include <evbarm/iq80310/iq80310reg.h> 52 #include <evbarm/iq80310/iq80310var.h> 53 #include <evbarm/iq80310/obiovar.h> 54 55 irqhandler_t *irqhandlers[NIRQS]; 56 57 int current_intr_depth; /* Depth of interrupt nesting */ 58 u_int intr_claimed_mask; /* Interrupts that are claimed */ 59 u_int intr_disabled_mask; /* Interrupts that are temporarily disabled */ 60 u_int intr_current_mask; /* Interrupts currently allowable */ 61 u_int spl_mask; 62 u_int irqmasks[IPL_LEVELS]; 63 u_int irqblock[NIRQS]; 64 65 extern u_int soft_interrupts; /* Only so we can initialise it */ 66 67 extern char *_intrnames; 68 extern void set_spl_masks(void); 69 70 /* Called only from assembler code. */ 71 uint32_t iq80310_intstat_read(void); 72 void stray_irqhandler(int); 73 74 /* 75 * We have 8 interrupt source bits -- 5 in the XINT3 register, and 3 76 * in the XINT0 register (the upper 3). 77 */ 78 #define IRQ_BITS 0xff 79 80 void 81 irq_init(void) 82 { 83 int loop; 84 85 /* Clear all the IRQ handlers and the IRQ block masks. */ 86 for (loop = 0; loop < NIRQS; ++loop) { 87 irqhandlers[loop] = NULL; 88 irqblock[loop] = 0; 89 } 90 91 /* 92 * Set up the irqmasks for the different interrupt priority 93 * levels. We will start with no bits set and these will be 94 * updated as handlers are installed at different IPLs. 95 */ 96 for (loop = 0; loop < IPL_LEVELS; ++loop) 97 irqmasks[loop] = 0; 98 99 current_intr_depth = 0; 100 intr_claimed_mask = 0x00000000; 101 intr_disabled_mask = 0x00000000; 102 intr_current_mask = 0x00000000; 103 spl_mask = 0x00000000; 104 soft_interrupts = 0x00000000; 105 106 set_spl_masks(); 107 irq_setmasks(); 108 109 /* Enable IRQs and FIQs. */ 110 enable_interrupts(I32_bit | F32_bit); 111 } 112 113 uint32_t 114 iq80310_intstat_read(void) 115 { 116 uint32_t intstat; 117 118 intstat = CPLD_READ(IQ80310_XINT3_STATUS) & 0x1f; 119 if (1/*rev F or later board*/) 120 intstat |= (CPLD_READ(IQ80310_XINT0_STATUS) & 0x7) << 5; 121 122 /* XXX Why do we have to mask off? */ 123 return (intstat & intr_current_mask); 124 } 125 126 __inline void 127 irq_setmasks_nointr(void) 128 { 129 u_int disabled; 130 131 /* 132 * The XINT_MASK register sets a bit to *disable*. 133 */ 134 disabled = (~(intr_current_mask & spl_mask)) & IRQ_BITS; 135 136 /* 137 * The PCI interrupts are all masked by a single 138 * bit in XINT3. 139 */ 140 if (disabled >> 5) 141 disabled |= XINT3_SINTD; 142 143 CPLD_WRITE(IQ80310_XINT_MASK, disabled & 0x1f); 144 } 145 146 void 147 irq_setmasks(void) 148 { 149 u_int oldirqstate; 150 151 oldirqstate = disable_interrupts(I32_bit); 152 irq_setmasks_nointr(); 153 restore_interrupts(oldirqstate); 154 } 155 156 void 157 enable_irq(int irq) 158 { 159 160 intr_claimed_mask |= (1U << irq); 161 intr_current_mask = intr_claimed_mask & ~intr_disabled_mask; 162 irq_setmasks_nointr(); 163 } 164 165 void 166 disable_irq(int irq) 167 { 168 169 intr_claimed_mask &= ~(1U << irq); 170 intr_current_mask = intr_claimed_mask & ~intr_disabled_mask; 171 irq_setmasks_nointr(); 172 } 173 174 void 175 stray_irqhandler(int irq) 176 { 177 178 panic("no handlers for IRQ %d (xint_mask = 0x%02x)\n", irq, 179 CPLD_READ(IQ80310_XINT_MASK)); 180 } 181 182 void * 183 iq80310_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 184 { 185 irqhandler_t *ih, *ptr; 186 u_int oldirqstate; 187 int loop; 188 189 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 190 if (ih == NULL) 191 return (NULL); 192 193 ih->ih_level = ipl; 194 ih->ih_name = NULL; 195 ih->ih_func = func; 196 ih->ih_arg = arg; 197 ih->ih_flags = 0; 198 ih->ih_num = irq; 199 200 oldirqstate = disable_interrupts(I32_bit); 201 202 /* Attach handler at top of chain */ 203 ih->ih_next = irqhandlers[irq]; 204 irqhandlers[irq] = ih; 205 206 /* Update the IRQ masks. */ 207 ptr = irqhandlers[irq]; 208 if (ptr) { 209 ipl = ptr->ih_level - 1; 210 while (ptr) { 211 if (ptr->ih_level - 1 < ipl) 212 ipl = ptr->ih_level - 1; 213 ptr = ptr->ih_next; 214 } 215 for (loop = 0; loop < IPL_LEVELS; ++loop) { 216 if (ipl >= loop) 217 irqmasks[loop] |= (1U << irq); 218 else 219 irqmasks[loop] &= ~(1U << irq); 220 } 221 } 222 223 /* splimp > spltty */ 224 irqmasks[IPL_NET] &= irqmasks[IPL_TTY]; 225 226 /* 227 * We now need to update the irqblock array. This array indicates 228 * what other interrupts should be blocked when a given interrupt 229 * is asserted. This basically emulates hardware interrupt 230 * priorities e.g. by blocking all other IPL_BIO interrupts when 231 * an IPL_BIO interrupt is asserted. For each interrupt, we find 232 * the highest IPL and set the block mask to the interrupt mask 233 * for that level. 234 */ 235 for (loop = 0; loop < NIRQS; ++loop) { 236 ptr = irqhandlers[loop]; 237 if (ptr) { 238 /* There is at least 1 handler so scan the chain */ 239 ipl = ptr->ih_level; 240 while (ptr) { 241 if (ptr->ih_level > ipl) 242 ipl = ptr->ih_level; 243 ptr = ptr->ih_next; 244 } 245 irqblock[loop] = ~irqmasks[ipl]; 246 } else { 247 /* No handlers, so nothing else needs to be blocked. */ 248 irqblock[loop] = 0; 249 } 250 } 251 252 enable_irq(irq); 253 set_spl_masks(); 254 255 restore_interrupts(oldirqstate); 256 257 return (ih); 258 } 259 260 void 261 iq80310_intr_disestablish(void *cookie) 262 { 263 264 panic("iq80310_intr_disestablish"); 265 } 266
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