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iq80310_intr.c revision 1.7 
      1 /*	$NetBSD: iq80310_intr.c,v 1.7 2002/01/20 03:41:48 thorpej Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2001 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed for the NetBSD Project by
     20  *	Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 /*
     39  * Interrupt support for the Intel IQ80310.
     40  */
     41 
     42 #include <sys/param.h>
     43 #include <sys/systm.h>
     44 #include <sys/malloc.h>
     45 
     46 #include <machine/bus.h>
     47 #include <machine/intr.h>
     48 #include <machine/cpu.h>
     49 #include <arm/cpufunc.h>
     50 
     51 #include <arm/xscale/i80200reg.h>
     52 
     53 #include <evbarm/iq80310/iq80310reg.h>
     54 #include <evbarm/iq80310/iq80310var.h>
     55 #include <evbarm/iq80310/obiovar.h>
     56 
     57 irqhandler_t *irqhandlers[NIRQS];
     58 
     59 int current_intr_depth;		/* Depth of interrupt nesting */
     60 u_int intr_claimed_mask;	/* Interrupts that are claimed */
     61 u_int intr_disabled_mask;	/* Interrupts that are temporarily disabled */
     62 u_int intr_current_mask;	/* Interrupts currently allowable */
     63 u_int spl_mask;
     64 u_int irqmasks[IPL_LEVELS];
     65 u_int irqblock[NIRQS];
     66 
     67 u_int iq80310_intrmask;		/* actual interrupts currently enabled */
     68 
     69 extern u_int soft_interrupts;   /* Only so we can initialise it */
     70 
     71 extern char *_intrnames;
     72 extern void set_spl_masks(void);
     73 
     74 /* Called only from assembler code. */
     75 uint32_t iq80310_intstat_read(void);
     76 void	 stray_irqhandler(int);
     77 
     78 /*
     79  * We have 8 interrupt source bits -- 5 in the XINT3 register, and 3
     80  * in the XINT0 register (the upper 3).
     81  */
     82 #define	IRQ_BITS	0xff
     83 
     84 void
     85 irq_init(void)
     86 {
     87 	int loop;
     88 
     89 	/* Clear all the IRQ handlers and the IRQ block masks. */
     90 	for (loop = 0; loop < NIRQS; ++loop) {
     91 		irqhandlers[loop] = NULL;
     92 		irqblock[loop] = 0;
     93 	}
     94 
     95 	/*
     96 	 * Set up the irqmasks for the different interrupt priority
     97 	 * levels.  We will start with no bits set and these will be
     98 	 * updated as handlers are installed at different IPLs.
     99 	 */
    100 	for (loop = 0; loop < IPL_LEVELS; ++loop)
    101 		irqmasks[loop] = 0;
    102 
    103 	current_intr_depth = 0;
    104 	intr_claimed_mask = 0x00000000;
    105 	intr_disabled_mask = 0x00000000;
    106 	intr_current_mask = 0x00000000;
    107 	spl_mask = 0x00000000;
    108 	soft_interrupts = 0x00000000;
    109 
    110 	set_spl_masks();
    111 	irq_setmasks();
    112 
    113 	/* Steer PMU and BCU interrupts to IRQ. */
    114 	__asm __volatile("mcr p13, 0, %0, c2, c0, 0"
    115 		:
    116 		: "r" (0));
    117 
    118 	/*
    119 	 * Enable external IRQs, disable external FIQs and
    120 	 * the PMU and BCU interrupts.
    121 	 */
    122 	__asm __volatile("mcr p13, 0, %0, c0, c0, 0"
    123 		:
    124 		: "r" (INTCTL_IM));
    125 
    126 	/* Enable IRQs. */
    127 	enable_interrupts(I32_bit);
    128 }
    129 
    130 uint32_t
    131 iq80310_intstat_read(void)
    132 {
    133 	uint32_t intstat;
    134 
    135 	intstat = CPLD_READ(IQ80310_XINT3_STATUS) & 0x1f;
    136 	if (1/*rev F or later board*/)
    137 		intstat |= (CPLD_READ(IQ80310_XINT0_STATUS) & 0x7) << 5;
    138 
    139 	/*
    140 	 * Yuck.  Even if the interrupt is disabled, the bit will
    141 	 * still light up in the interrupt status register (it
    142 	 * just won't assert IRQ#).
    143 	 */
    144 	return (intstat & iq80310_intrmask);
    145 }
    146 
    147 __inline void irq_setmasks_nointr(void);	/* called from asm */
    148 
    149 __inline void
    150 irq_setmasks_nointr(void)
    151 {
    152 	u_int disabled;
    153 
    154 	/* The actual mask of IRQs actually right *right now*. */
    155 	iq80310_intrmask = (intr_current_mask & spl_mask) & IRQ_BITS;
    156 
    157 	/*
    158 	 * The XINT_MASK register sets a bit to *disable*.
    159 	 */
    160 	disabled = ~iq80310_intrmask;
    161 
    162 	/*
    163 	 * The PCI interrupts are all masked by a single
    164 	 * bit in XINT3.
    165 	 */
    166 	if (disabled >> 5)
    167 		disabled |= XINT3_SINTD;
    168 
    169 	CPLD_WRITE(IQ80310_XINT_MASK, disabled & 0x1f);
    170 }
    171 
    172 void
    173 irq_setmasks(void)
    174 {
    175 	u_int oldirqstate;
    176 
    177 	oldirqstate = disable_interrupts(I32_bit);
    178 	irq_setmasks_nointr();
    179 	restore_interrupts(oldirqstate);
    180 }
    181 
    182 void
    183 enable_irq(int irq)
    184 {
    185 
    186 	intr_claimed_mask |= (1U << irq);
    187 	intr_current_mask = intr_claimed_mask & ~intr_disabled_mask;
    188 	irq_setmasks_nointr();
    189 }
    190 
    191 void
    192 disable_irq(int irq)
    193 {
    194 
    195 	intr_claimed_mask &= ~(1U << irq);
    196 	intr_current_mask = intr_claimed_mask & ~intr_disabled_mask;
    197 	irq_setmasks_nointr();
    198 }
    199 
    200 void
    201 stray_irqhandler(int irq)
    202 {
    203 
    204 	panic("no handlers for IRQ %d (xint_mask = 0x%02x)\n", irq,
    205 	    CPLD_READ(IQ80310_XINT_MASK));
    206 }
    207 
    208 void *
    209 iq80310_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)
    210 {
    211 	irqhandler_t *ih, *ptr;
    212 	u_int oldirqstate;
    213 	int loop;
    214 
    215 	ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
    216 	if (ih == NULL)
    217 		return (NULL);
    218 
    219 	ih->ih_level = ipl;
    220 	ih->ih_name = NULL;
    221 	ih->ih_func = func;
    222 	ih->ih_arg = arg;
    223 	ih->ih_flags = 0;
    224 	ih->ih_num = irq;
    225 
    226 	oldirqstate = disable_interrupts(I32_bit);
    227 
    228 	/* Attach handler at top of chain */
    229 	ih->ih_next = irqhandlers[irq];
    230 	irqhandlers[irq] = ih;
    231 
    232 	/* Update the IRQ masks. */
    233 	ptr = irqhandlers[irq];
    234 	if (ptr) {
    235 		ipl = ptr->ih_level - 1;
    236 		while (ptr) {
    237 			if (ptr->ih_level - 1 < ipl)
    238 				ipl = ptr->ih_level - 1;
    239 			ptr = ptr->ih_next;
    240 		}
    241 		for (loop = 0; loop < IPL_LEVELS; ++loop) {
    242 			if (ipl >= loop)
    243 				irqmasks[loop] |= (1U << irq);
    244 			else
    245 				irqmasks[loop] &= ~(1U << irq);
    246 		}
    247 	}
    248 
    249 	/* splimp > spltty */
    250 	irqmasks[IPL_NET] &= irqmasks[IPL_TTY];
    251 
    252 	/*
    253 	 * We now need to update the irqblock array.  This array indicates
    254 	 * what other interrupts should be blocked when a given interrupt
    255 	 * is asserted.  This basically emulates hardware interrupt
    256 	 * priorities e.g. by blocking all other IPL_BIO interrupts when
    257 	 * an IPL_BIO interrupt is asserted.  For each interrupt, we find
    258 	 * the highest IPL and set the block mask to the interrupt mask
    259 	 * for that level.
    260 	 */
    261 	for (loop = 0; loop < NIRQS; ++loop) {
    262 		ptr = irqhandlers[loop];
    263 		if (ptr) {
    264 			/* There is at least 1 handler so scan the chain */
    265 			ipl = ptr->ih_level;
    266 			while (ptr) {
    267 				if (ptr->ih_level > ipl)
    268 					ipl = ptr->ih_level;
    269 				ptr = ptr->ih_next;
    270 			}
    271 			irqblock[loop] = ~irqmasks[ipl];
    272 		} else {
    273 			/* No handlers, so nothing else needs to be blocked. */
    274 			irqblock[loop] = 0;
    275 		}
    276 	}
    277 
    278 	enable_irq(irq);
    279 	set_spl_masks();
    280 
    281 	restore_interrupts(oldirqstate);
    282 
    283 	return (ih);
    284 }
    285 
    286 void
    287 iq80310_intr_disestablish(void *cookie)
    288 {
    289 
    290 	panic("iq80310_intr_disestablish");
    291 }
    292