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iq80310_intr.h revision 1.6 
      1 /*	$NetBSD: iq80310_intr.h,v 1.6 2008/01/06 01:37:58 matt Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed for the NetBSD Project by
     20  *	Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 #ifndef _IQ80310_INTR_H_
     39 #define _IQ80310_INTR_H_
     40 
     41 #include "opt_iop310.h"
     42 
     43 #include <arm/armreg.h>
     44 #include <arm/cpufunc.h>
     45 
     46 #include <arm/xscale/i80200reg.h>
     47 #include <arm/xscale/i80200var.h>
     48 
     49 #if defined(IOP310_TEAMASA_NPWR)
     50 /*
     51  * We have 5 interrupt source bits -- all in XINT3.  All interrupts
     52  * can be masked in the CPLD.
     53  */
     54 #define	IRQ_BITS		0x1f
     55 #define	IRQ_BITS_ALWAYS_ON	0x00
     56 #else /* Default to stock IQ80310 */
     57 /*
     58  * We have 8 interrupt source bits -- 5 in the XINT3 register, and 3
     59  * in the XINT0 register (the upper 3).  Note that the XINT0 IRQs
     60  * (SPCI INTA, INTB, and INTC) are always enabled, since they can not
     61  * be masked out in the CPLD (it provides only status, not masking,
     62  * for those interrupts).
     63  */
     64 #define	IRQ_BITS		0xff
     65 #define	IRQ_BITS_ALWAYS_ON	0xe0
     66 #define	IRQ_READ_XINT0		1	/* XXX only if board rev >= F */
     67 #endif /* list of IQ80310-based designs */
     68 
     69 #ifdef __HAVE_FAST_SOFTINTS
     70 void	iq80310_do_soft(void);
     71 #endif
     72 
     73 static inline int __attribute__((__unused__))
     74 iq80310_splraise(int ipl)
     75 {
     76 	extern volatile int current_spl_level;
     77 	extern int iq80310_imask[];
     78 	int old;
     79 
     80 	old = current_spl_level;
     81 	current_spl_level |= iq80310_imask[ipl];
     82 
     83 	/* Don't let the compiler re-order this code with subsequent code */
     84 	__insn_barrier();
     85 
     86 	return (old);
     87 }
     88 
     89 static inline void __attribute__((__unused__))
     90 iq80310_splx(int new)
     91 {
     92 	extern volatile int iq80310_ipending;
     93 	extern volatile int current_spl_level;
     94 	int old;
     95 
     96 	/* Don't let the compiler re-order this code with preceding code */
     97 	__insn_barrier();
     98 
     99 	old = current_spl_level;
    100 	current_spl_level = new;
    101 
    102 #ifdef __HAVE_FAST_SOFTINTS
    103 	/* If there are software interrupts to process, do it. */
    104 	if ((iq80310_ipending & ~IRQ_BITS) & ~new)
    105 		iq80310_do_soft();
    106 #endif
    107 
    108 	/*
    109 	 * If there are pending hardware interrupts (i.e. the
    110 	 * external interrupt is disabled in the ICU), and all
    111 	 * hardware interrupts are being unblocked, then re-enable
    112 	 * the external hardware interrupt.
    113 	 *
    114 	 * XXX We have to wait for ALL hardware interrupts to
    115 	 * XXX be unblocked, because we currently lose if we
    116 	 * XXX get nested interrupts, and I don't know why yet.
    117 	 */
    118 	if ((new & IRQ_BITS) == 0 && (iq80310_ipending & IRQ_BITS))
    119 		i80200_intr_enable(INTCTL_IM | INTCTL_PM);
    120 }
    121 
    122 static inline int __attribute__((__unused__))
    123 iq80310_spllower(int ipl)
    124 {
    125 	extern volatile int current_spl_level;
    126 	extern int iq80310_imask[];
    127 	int old = current_spl_level;
    128 
    129 	iq80310_splx(iq80310_imask[ipl]);
    130 	return (old);
    131 }
    132 
    133 #if !defined(EVBARM_SPL_NOINLINE)
    134 
    135 #define _splraise(ipl)		iq80310_splraise(ipl)
    136 #define	_spllower(ipl)		iq80310_spllower(ipl)
    137 #define	splx(spl)		iq80310_splx(spl)
    138 #ifdef __HAVE_FAST_SOFTINTS
    139 void	_setsoftintr(int);
    140 #endif
    141 
    142 #else
    143 
    144 int	_splraise(int);
    145 int	_spllower(int);
    146 void	splx(int);
    147 #ifdef __HAVE_FAST_SOFTINTS
    148 void	_setsoftintr(int);
    149 #endif
    150 
    151 #endif /* ! EVBARM_SPL_NOINLINE */
    152 
    153 #endif /* _IQ80310_INTR_H_ */
    154