iq80310_machdep.c revision 1.29
1 /* $NetBSD: iq80310_machdep.c,v 1.29 2002/02/22 17:23:13 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1997,1998 Mark Brinicombe. 40 * Copyright (c) 1997,1998 Causality Limited. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Mark Brinicombe 54 * for the NetBSD Project. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * Machine dependant functions for kernel setup for Intel IQ80310 evaluation 72 * boards using RedBoot firmware. 73 */ 74 75 #include "opt_ddb.h" 76 #include "opt_pmap_debug.h" 77 78 #include <sys/param.h> 79 #include <sys/device.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/exec.h> 83 #include <sys/proc.h> 84 #include <sys/msgbuf.h> 85 #include <sys/reboot.h> 86 #include <sys/termios.h> 87 88 #include <dev/cons.h> 89 90 #include <machine/db_machdep.h> 91 #include <ddb/db_sym.h> 92 #include <ddb/db_extern.h> 93 94 #include <machine/bootconfig.h> 95 #include <machine/bus.h> 96 #include <machine/cpu.h> 97 #include <machine/frame.h> 98 #include <arm/undefined.h> 99 100 #include <arm/arm32/machdep.h> 101 102 #include <arm/xscale/i80312reg.h> 103 #include <arm/xscale/i80312var.h> 104 105 #include <dev/pci/ppbreg.h> 106 107 #include <evbarm/iq80310/iq80310reg.h> 108 #include <evbarm/iq80310/iq80310var.h> 109 #include <evbarm/iq80310/obiovar.h> 110 111 #include "opt_ipkdb.h" 112 113 /* 114 * Address to call from cpu_reset() to reset the machine. 115 * This is machine architecture dependant as it varies depending 116 * on where the ROM appears when you turn the MMU off. 117 */ 118 119 u_int cpu_reset_address = 0; 120 121 /* Define various stack sizes in pages */ 122 #define IRQ_STACK_SIZE 1 123 #define ABT_STACK_SIZE 1 124 #ifdef IPKDB 125 #define UND_STACK_SIZE 2 126 #else 127 #define UND_STACK_SIZE 1 128 #endif 129 130 BootConfig bootconfig; /* Boot config storage */ 131 char *boot_args = NULL; 132 char *boot_file = NULL; 133 134 vm_offset_t physical_start; 135 vm_offset_t physical_freestart; 136 vm_offset_t physical_freeend; 137 vm_offset_t physical_end; 138 u_int free_pages; 139 vm_offset_t pagetables_start; 140 int physmem = 0; 141 142 /*int debug_flags;*/ 143 #ifndef PMAP_STATIC_L1S 144 int max_processes = 64; /* Default number */ 145 #endif /* !PMAP_STATIC_L1S */ 146 147 /* Physical and virtual addresses for some global pages */ 148 pv_addr_t systempage; 149 pv_addr_t irqstack; 150 pv_addr_t undstack; 151 pv_addr_t abtstack; 152 pv_addr_t kernelstack; 153 pv_addr_t minidataclean; 154 155 vm_offset_t msgbufphys; 156 157 extern u_int data_abort_handler_address; 158 extern u_int prefetch_abort_handler_address; 159 extern u_int undefined_handler_address; 160 161 #ifdef PMAP_DEBUG 162 extern int pmap_debug_level; 163 #endif 164 165 #define KERNEL_PT_SYS 0 /* L2 table for mapping zero page */ 166 167 #define KERNEL_PT_KERNEL 1 /* L2 table for mapping kernel */ 168 #define KERNEL_PT_KERNEL_NUM 2 169 170 /* L2 table for mapping i80312 */ 171 #define KERNEL_PT_IOPXS (KERNEL_PT_KERNEL + KERNEL_PT_KERNEL_NUM) 172 173 /* L2 tables for mapping kernel VM */ 174 #define KERNEL_PT_VMDATA (KERNEL_PT_IOPXS + 1) 175 #define KERNEL_PT_VMDATA_NUM (KERNEL_VM_SIZE >> (PDSHIFT + 2)) 176 #define NUM_KERNEL_PTS (KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM) 177 178 pv_addr_t kernel_pt_table[NUM_KERNEL_PTS]; 179 180 struct user *proc0paddr; 181 182 /* Prototypes */ 183 184 void consinit(void); 185 186 #include "com.h" 187 #if NCOM > 0 188 #include <dev/ic/comreg.h> 189 #include <dev/ic/comvar.h> 190 #endif 191 192 /* 193 * Define the default console speed for the board. This is generally 194 * what the firmware provided with the board defaults to. 195 */ 196 #ifndef CONSPEED 197 #if defined(IOP310_TEAMASA_NPWR) 198 #define CONSPEED B19200 199 #else /* Default to stock IQ80310 */ 200 #define CONSPEED B115200 201 #endif /* list of IQ80310-based designs */ 202 #endif /* ! CONSPEED */ 203 204 #ifndef CONUNIT 205 #define CONUNIT 0 206 #endif 207 208 #ifndef CONMODE 209 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 210 #endif 211 212 int comcnspeed = CONSPEED; 213 int comcnmode = CONMODE; 214 int comcnunit = CONUNIT; 215 216 /* 217 * void cpu_reboot(int howto, char *bootstr) 218 * 219 * Reboots the system 220 * 221 * Deal with any syncing, unmounting, dumping and shutdown hooks, 222 * then reset the CPU. 223 */ 224 void 225 cpu_reboot(int howto, char *bootstr) 226 { 227 #ifdef DIAGNOSTIC 228 /* info */ 229 printf("boot: howto=%08x curproc=%p\n", howto, curproc); 230 #endif 231 232 /* 233 * If we are still cold then hit the air brakes 234 * and crash to earth fast 235 */ 236 if (cold) { 237 doshutdownhooks(); 238 printf("The operating system has halted.\n"); 239 printf("Please press any key to reboot.\n\n"); 240 cngetc(); 241 printf("rebooting...\n"); 242 cpu_reset(); 243 /*NOTREACHED*/ 244 } 245 246 /* Disable console buffering */ 247 248 /* 249 * If RB_NOSYNC was not specified sync the discs. 250 * Note: Unless cold is set to 1 here, syslogd will die during the 251 * unmount. It looks like syslogd is getting woken up only to find 252 * that it cannot page part of the binary in as the filesystem has 253 * been unmounted. 254 */ 255 if (!(howto & RB_NOSYNC)) 256 bootsync(); 257 258 /* Say NO to interrupts */ 259 splhigh(); 260 261 /* Do a dump if requested. */ 262 if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP) 263 dumpsys(); 264 265 /* Run any shutdown hooks */ 266 doshutdownhooks(); 267 268 /* Make sure IRQ's are disabled */ 269 IRQdisable; 270 271 if (howto & RB_HALT) { 272 printf("The operating system has halted.\n"); 273 printf("Please press any key to reboot.\n\n"); 274 cngetc(); 275 } 276 277 printf("rebooting...\n"); 278 cpu_reset(); 279 /*NOTREACHED*/ 280 } 281 282 /* 283 * Mapping table for core kernel memory. This memory is mapped at init 284 * time with section mappings. 285 */ 286 struct l1_sec_map { 287 vaddr_t va; 288 vaddr_t pa; 289 vsize_t size; 290 vm_prot_t prot; 291 int cache; 292 } l1_sec_table[] = { 293 /* 294 * Map the on-board devices VA == PA so that we can access them 295 * with the MMU on or off. 296 */ 297 { 298 IQ80310_OBIO_BASE, 299 IQ80310_OBIO_BASE, 300 IQ80310_OBIO_SIZE, 301 VM_PROT_READ|VM_PROT_WRITE, 302 PTE_NOCACHE, 303 }, 304 305 { 306 0, 307 0, 308 0, 309 0, 310 0, 311 } 312 }; 313 314 /* 315 * u_int initarm(...) 316 * 317 * Initial entry point on startup. This gets called before main() is 318 * entered. 319 * It should be responsible for setting up everything that must be 320 * in place when main is called. 321 * This includes 322 * Taking a copy of the boot configuration structure. 323 * Initialising the physical console so characters can be printed. 324 * Setting up page tables for the kernel 325 * Relocating the kernel to the bottom of physical memory 326 */ 327 u_int 328 initarm(void *arg) 329 { 330 extern vaddr_t xscale_cache_clean_addr, xscale_minidata_clean_addr; 331 extern vsize_t xscale_minidata_clean_size; 332 int loop; 333 int loop1; 334 u_int l1pagetable; 335 extern char page0[], page0_end[]; 336 pv_addr_t kernel_l1pt; 337 pv_addr_t kernel_ptpt; 338 paddr_t memstart; 339 psize_t memsize; 340 341 /* 342 * Clear out the 7-segment display. Whee, the first visual 343 * indication that we're running kernel code. 344 */ 345 iq80310_7seg(' ', ' '); 346 347 /* 348 * Heads up ... Setup the CPU / MMU / TLB functions 349 */ 350 if (set_cpufuncs()) 351 panic("cpu not recognized!"); 352 353 /* Calibrate the delay loop. */ 354 iq80310_calibrate_delay(); 355 356 /* 357 * Since we map the on-board devices VA==PA, and the kernel 358 * is running VA==PA, it's possible for us to initialize 359 * the console now. 360 */ 361 consinit(); 362 363 /* Talk to the user */ 364 printf("\nNetBSD/evbarm (IQ80310) booting ...\n"); 365 366 /* 367 * Reset the secondary PCI bus. RedBoot doesn't stop devices 368 * on the PCI bus before handing us control, so we have to 369 * do this. 370 * 371 * XXX This is arguably a bug in RedBoot, and doing this reset 372 * XXX could be problematic in the future if we encounter an 373 * XXX application where the PPB in the i80312 is used as a 374 * XXX PPB. 375 */ 376 { 377 uint32_t reg; 378 379 printf("Resetting secondary PCI bus...\n"); 380 reg = bus_space_read_4(&obio_bs_tag, 381 I80312_PMMR_BASE + I80312_PPB_BASE, PPB_REG_BRIDGECONTROL); 382 bus_space_write_4(&obio_bs_tag, 383 I80312_PMMR_BASE + I80312_PPB_BASE, PPB_REG_BRIDGECONTROL, 384 reg | PPB_BC_SECONDARY_RESET); 385 delay(10 * 1000); /* 10ms enough? */ 386 bus_space_write_4(&obio_bs_tag, 387 I80312_PMMR_BASE + I80312_PPB_BASE, PPB_REG_BRIDGECONTROL, 388 reg); 389 } 390 391 /* 392 * Okay, RedBoot has provided us with the following memory map: 393 * 394 * Physical Address Range Description 395 * ----------------------- ---------------------------------- 396 * 0x00000000 - 0x00000fff flash Memory 397 * 0x00001000 - 0x00001fff 80312 Internal Registers 398 * 0x00002000 - 0x007fffff flash Memory 399 * 0x00800000 - 0x7fffffff PCI ATU Outbound Direct Window 400 * 0x80000000 - 0x83ffffff Primary PCI 32-bit Memory 401 * 0x84000000 - 0x87ffffff Primary PCI 64-bit Memory 402 * 0x88000000 - 0x8bffffff Secondary PCI 32-bit Memory 403 * 0x8c000000 - 0x8fffffff Secondary PCI 64-bit Memory 404 * 0x90000000 - 0x9000ffff Primary PCI IO Space 405 * 0x90010000 - 0x9001ffff Secondary PCI IO Space 406 * 0x90020000 - 0x9fffffff Unused 407 * 0xa0000000 - 0xbfffffff SDRAM 408 * 0xc0000000 - 0xefffffff Unused 409 * 0xf0000000 - 0xffffffff 80200 Internal Registers 410 * 411 * 412 * Virtual Address Range C B Description 413 * ----------------------- - - ---------------------------------- 414 * 0x00000000 - 0x00000fff Y Y SDRAM 415 * 0x00001000 - 0x00001fff N N 80312 Internal Registers 416 * 0x00002000 - 0x007fffff Y N flash Memory 417 * 0x00800000 - 0x7fffffff N N PCI ATU Outbound Direct Window 418 * 0x80000000 - 0x83ffffff N N Primary PCI 32-bit Memory 419 * 0x84000000 - 0x87ffffff N N Primary PCI 64-bit Memory 420 * 0x88000000 - 0x8bffffff N N Secondary PCI 32-bit Memory 421 * 0x8c000000 - 0x8fffffff N N Secondary PCI 64-bit Memory 422 * 0x90000000 - 0x9000ffff N N Primary PCI IO Space 423 * 0x90010000 - 0x9001ffff N N Secondary PCI IO Space 424 * 0xa0000000 - 0xa0000fff Y N flash 425 * 0xa0001000 - 0xbfffffff Y Y SDRAM 426 * 0xc0000000 - 0xcfffffff Y Y Cache Flush Region 427 * 0xf0000000 - 0xffffffff N N 80200 Internal Registers 428 * 429 * The first level page table is at 0xa0004000. There are also 430 * 2 second-level tables at 0xa0008000 and 0xa0008400. 431 * 432 * This corresponds roughly to the physical memory map, i.e. 433 * we are quite nearly running VA==PA. 434 */ 435 436 /* 437 * Examine the boot args string for options we need to know about 438 * now. 439 */ 440 #if 0 441 process_kernel_args((char *)nwbootinfo.bt_args); 442 #endif 443 444 /* 445 * Fetch the SDRAM start/size from the i80312 SDRAM configration 446 * registers. 447 */ 448 i80312_sdram_bounds(&obio_bs_tag, I80312_PMMR_BASE + I80312_MEM_BASE, 449 &memstart, &memsize); 450 451 printf("initarm: Configuring system ...\n"); 452 453 /* Fake bootconfig structure for the benefit of pmap.c */ 454 /* XXX must make the memory description h/w independant */ 455 bootconfig.dramblocks = 1; 456 bootconfig.dram[0].address = memstart; 457 bootconfig.dram[0].pages = memsize / NBPG; 458 459 /* 460 * Set up the variables that define the availablilty of 461 * physical memory. For now, we're going to set 462 * physical_freestart to 0xa0200000 (where the kernel 463 * was loaded), and allocate the memory we need downwards. 464 * If we get too close to the page tables that RedBoot 465 * set up, we will panic. We will update physical_freestart 466 * and physical_freeend later to reflect what pmap_bootstrap() 467 * wants to see. 468 * 469 * XXX pmap_bootstrap() needs an enema. 470 */ 471 physical_start = bootconfig.dram[0].address; 472 physical_end = physical_start + (bootconfig.dram[0].pages * NBPG); 473 474 physical_freestart = 0xa0009000UL; 475 physical_freeend = 0xa0200000UL; 476 477 physmem = (physical_end - physical_start) / NBPG; 478 479 /* Tell the user about the memory */ 480 printf("physmemory: %d pages at 0x%08lx -> 0x%08lx\n", physmem, 481 physical_start, physical_end - 1); 482 483 /* 484 * Okay, the kernel starts 2MB in from the bottom of physical 485 * memory. We are going to allocate our bootstrap pages downwards 486 * from there. 487 * 488 * We need to allocate some fixed page tables to get the kernel 489 * going. We allocate one page directory and a number of page 490 * tables and store the physical addresses in the kernel_pt_table 491 * array. 492 * 493 * The kernel page directory must be on a 16K boundary. The page 494 * tables must be on 4K bounaries. What we do is allocate the 495 * page directory on the first 16K boundary that we encounter, and 496 * the page tables on 4K boundaries otherwise. Since we allocate 497 * at least 3 L2 page tables, we are guaranteed to encounter at 498 * least one 16K aligned region. 499 */ 500 501 #ifdef VERBOSE_INIT_ARM 502 printf("Allocating page tables\n"); 503 #endif 504 505 free_pages = (physical_freeend - physical_freestart) / NBPG; 506 507 #ifdef VERBOSE_INIT_ARM 508 printf("freestart = 0x%08lx, free_pages = %d (0x%08x)\n", 509 physical_freestart, free_pages, free_pages); 510 #endif 511 512 /* Define a macro to simplify memory allocation */ 513 #define valloc_pages(var, np) \ 514 alloc_pages((var).pv_pa, (np)); \ 515 (var).pv_va = KERNEL_BASE + (var).pv_pa - physical_start; 516 517 #define alloc_pages(var, np) \ 518 physical_freeend -= ((np) * NBPG); \ 519 if (physical_freeend < physical_freestart) \ 520 panic("initarm: out of memory"); \ 521 (var) = physical_freeend; \ 522 free_pages -= (np); \ 523 memset((char *)(var), 0, ((np) * NBPG)); 524 525 loop1 = 0; 526 kernel_l1pt.pv_pa = 0; 527 for (loop = 0; loop <= NUM_KERNEL_PTS; ++loop) { 528 /* Are we 16KB aligned for an L1 ? */ 529 if (((physical_freeend - PD_SIZE) & (PD_SIZE - 1)) == 0 530 && kernel_l1pt.pv_pa == 0) { 531 valloc_pages(kernel_l1pt, PD_SIZE / NBPG); 532 } else { 533 alloc_pages(kernel_pt_table[loop1].pv_pa, 534 PT_SIZE / NBPG); 535 kernel_pt_table[loop1].pv_va = 536 kernel_pt_table[loop1].pv_pa; 537 ++loop1; 538 } 539 } 540 541 /* This should never be able to happen but better confirm that. */ 542 if (!kernel_l1pt.pv_pa || (kernel_l1pt.pv_pa & (PD_SIZE-1)) != 0) 543 panic("initarm: Failed to align the kernel page directory\n"); 544 545 /* 546 * Allocate a page for the system page mapped to V0x00000000 547 * This page will just contain the system vectors and can be 548 * shared by all processes. 549 */ 550 alloc_pages(systempage.pv_pa, 1); 551 552 /* Allocate a page for the page table to map kernel page tables. */ 553 valloc_pages(kernel_ptpt, PT_SIZE / NBPG); 554 555 /* Allocate stacks for all modes */ 556 valloc_pages(irqstack, IRQ_STACK_SIZE); 557 valloc_pages(abtstack, ABT_STACK_SIZE); 558 valloc_pages(undstack, UND_STACK_SIZE); 559 valloc_pages(kernelstack, UPAGES); 560 561 /* Allocate enough pages for cleaning the Mini-Data cache. */ 562 KASSERT(xscale_minidata_clean_size <= NBPG); 563 valloc_pages(minidataclean, 1); 564 xscale_minidata_clean_addr = minidataclean.pv_va; 565 566 #ifdef VERBOSE_INIT_ARM 567 printf("IRQ stack: p0x%08lx v0x%08lx\n", irqstack.pv_pa, 568 irqstack.pv_va); 569 printf("ABT stack: p0x%08lx v0x%08lx\n", abtstack.pv_pa, 570 abtstack.pv_va); 571 printf("UND stack: p0x%08lx v0x%08lx\n", undstack.pv_pa, 572 undstack.pv_va); 573 printf("SVC stack: p0x%08lx v0x%08lx\n", kernelstack.pv_pa, 574 kernelstack.pv_va); 575 #endif 576 577 /* 578 * XXX Defer this to later so that we can reclaim the memory 579 * XXX used by the RedBoot page tables. 580 */ 581 alloc_pages(msgbufphys, round_page(MSGBUFSIZE) / NBPG); 582 583 /* 584 * Ok we have allocated physical pages for the primary kernel 585 * page tables 586 */ 587 588 #ifdef VERBOSE_INIT_ARM 589 printf("Creating L1 page table at 0x%08lx\n", kernel_l1pt.pv_pa); 590 #endif 591 592 /* 593 * Now we start construction of the L1 page table 594 * We start by mapping the L2 page tables into the L1. 595 * This means that we can replace L1 mappings later on if necessary 596 */ 597 l1pagetable = kernel_l1pt.pv_pa; 598 599 /* Map the L2 pages tables in the L1 page table */ 600 pmap_link_l2pt(l1pagetable, 0x00000000, 601 &kernel_pt_table[KERNEL_PT_SYS]); 602 for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++) 603 pmap_link_l2pt(l1pagetable, KERNEL_BASE + loop * 0x00400000, 604 &kernel_pt_table[KERNEL_PT_KERNEL + loop]); 605 pmap_link_l2pt(l1pagetable, IQ80310_IOPXS_VBASE, 606 &kernel_pt_table[KERNEL_PT_IOPXS]); 607 for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++) 608 pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00400000, 609 &kernel_pt_table[KERNEL_PT_VMDATA + loop]); 610 pmap_link_l2pt(l1pagetable, PROCESS_PAGE_TBLS_BASE, &kernel_ptpt); 611 612 #ifdef VERBOSE_INIT_ARM 613 printf("Mapping kernel\n"); 614 #endif 615 616 /* Now we fill in the L2 pagetable for the kernel static code/data */ 617 618 { 619 extern char etext[], _end[]; 620 size_t textsize = (uintptr_t) etext - KERNEL_TEXT_BASE; 621 size_t totalsize = (uintptr_t) _end - KERNEL_TEXT_BASE; 622 u_int logical; 623 624 textsize = (textsize + PGOFSET) & ~PGOFSET; 625 totalsize = (totalsize + PGOFSET) & ~PGOFSET; 626 627 logical = 0x00200000; /* offset of kernel in RAM */ 628 629 /* 630 * This maps the kernel text/data/bss VA==PA. 631 */ 632 logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical, 633 physical_start + logical, textsize, 634 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 635 logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical, 636 physical_start + logical, totalsize - textsize, 637 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 638 639 #if 0 /* XXX No symbols yet. */ 640 logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical, 641 physical_start + logical, kernexec->a_syms + sizeof(int) 642 + *(u_int *)((int)end + kernexec->a_syms + sizeof(int)), 643 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 644 #endif 645 } 646 647 #ifdef VERBOSE_INIT_ARM 648 printf("Constructing L2 page tables\n"); 649 #endif 650 651 /* Map the stack pages */ 652 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa, 653 IRQ_STACK_SIZE * NBPG, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 654 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa, 655 ABT_STACK_SIZE * NBPG, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 656 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa, 657 UND_STACK_SIZE * NBPG, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 658 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa, 659 UPAGES * NBPG, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 660 661 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, 662 PD_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE); 663 664 /* Map the Mini-Data cache clean area. */ 665 pmap_map_chunk(l1pagetable, minidataclean.pv_va, minidataclean.pv_pa, 666 NBPG, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 667 668 /* Map the page table that maps the kernel pages */ 669 pmap_map_entry(l1pagetable, kernel_ptpt.pv_va, kernel_ptpt.pv_pa, 670 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE); 671 672 /* 673 * Map entries in the page table used to map PTE's 674 * Basically every kernel page table gets mapped here 675 */ 676 /* The -2 is slightly bogus, it should be -log2(sizeof(pt_entry_t)) */ 677 for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++) { 678 pmap_map_entry(l1pagetable, 679 PROCESS_PAGE_TBLS_BASE + ((KERNEL_BASE + 680 (loop * 0x00400000)) >> (PGSHIFT-2)), 681 kernel_pt_table[KERNEL_PT_KERNEL + loop].pv_pa, 682 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE); 683 } 684 pmap_map_entry(l1pagetable, 685 PROCESS_PAGE_TBLS_BASE + (PROCESS_PAGE_TBLS_BASE >> (PGSHIFT-2)), 686 kernel_ptpt.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE); 687 pmap_map_entry(l1pagetable, 688 PROCESS_PAGE_TBLS_BASE + (0x00000000 >> (PGSHIFT-2)), 689 kernel_pt_table[KERNEL_PT_SYS].pv_pa, 690 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE); 691 for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++) 692 pmap_map_entry(l1pagetable, 693 PROCESS_PAGE_TBLS_BASE + ((KERNEL_VM_BASE + 694 (loop * 0x00400000)) >> (PGSHIFT-2)), 695 kernel_pt_table[KERNEL_PT_VMDATA + loop].pv_pa, 696 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE); 697 698 /* 699 * Map the system page in the kernel page table for the bottom 1Meg 700 * of the virtual memory map. 701 */ 702 pmap_map_entry(l1pagetable, 0x00000000, systempage.pv_pa, 703 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 704 705 /* 706 * Map devices we can map w/ section mappings. 707 */ 708 loop = 0; 709 while (l1_sec_table[loop].size) { 710 vm_size_t sz; 711 712 #ifdef VERBOSE_INIT_ARM 713 printf("%08lx -> %08lx @ %08lx\n", l1_sec_table[loop].pa, 714 l1_sec_table[loop].pa + l1_sec_table[loop].size - 1, 715 l1_sec_table[loop].va); 716 #endif 717 for (sz = 0; sz < l1_sec_table[loop].size; sz += L1_SEC_SIZE) 718 pmap_map_section(l1pagetable, 719 l1_sec_table[loop].va + sz, 720 l1_sec_table[loop].pa + sz, 721 l1_sec_table[loop].prot, 722 l1_sec_table[loop].cache); 723 ++loop; 724 } 725 726 /* 727 * Map the PCI I/O spaces and i80312 registers. These are too 728 * small to be mapped w/ section mappings. 729 */ 730 #ifdef VERBOSE_INIT_ARM 731 printf("Mapping PIOW 0x%08lx -> 0x%08lx @ 0x%08lx\n", 732 I80312_PCI_XLATE_PIOW_BASE, 733 I80312_PCI_XLATE_PIOW_BASE + I80312_PCI_XLATE_IOSIZE - 1, 734 IQ80310_PIOW_VBASE); 735 #endif 736 pmap_map_chunk(l1pagetable, IQ80310_PIOW_VBASE, 737 I80312_PCI_XLATE_PIOW_BASE, I80312_PCI_XLATE_IOSIZE, 738 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE); 739 740 #ifdef VERBOSE_INIT_ARM 741 printf("Mapping SIOW 0x%08lx -> 0x%08lx @ 0x%08lx\n", 742 I80312_PCI_XLATE_SIOW_BASE, 743 I80312_PCI_XLATE_SIOW_BASE + I80312_PCI_XLATE_IOSIZE - 1, 744 IQ80310_SIOW_VBASE); 745 #endif 746 pmap_map_chunk(l1pagetable, IQ80310_SIOW_VBASE, 747 I80312_PCI_XLATE_SIOW_BASE, I80312_PCI_XLATE_IOSIZE, 748 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE); 749 750 #ifdef VERBOSE_INIT_ARM 751 printf("Mapping 80312 0x%08lx -> 0x%08lx @ 0x%08lx\n", 752 I80312_PMMR_BASE, 753 I80312_PMMR_BASE + I80312_PMMR_SIZE - 1, 754 IQ80310_80312_VBASE); 755 #endif 756 pmap_map_chunk(l1pagetable, IQ80310_80312_VBASE, 757 I80312_PMMR_BASE, I80312_PMMR_SIZE, 758 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE); 759 760 /* 761 * Give the XScale global cache clean code an appropriately 762 * sized chunk of unmapped VA space starting at 0xff000000 763 * (our device mappings end before this address). 764 */ 765 xscale_cache_clean_addr = 0xff000000U; 766 767 /* 768 * Now we have the real page tables in place so we can switch to them. 769 * Once this is done we will be running with the REAL kernel page 770 * tables. 771 */ 772 773 /* 774 * Update the physical_freestart/physical_freeend/free_pages 775 * variables. 776 */ 777 { 778 extern char _end[]; 779 780 physical_freestart = (((uintptr_t) _end) + PGOFSET) & ~PGOFSET; 781 physical_freeend = physical_end; 782 free_pages = (physical_freeend - physical_freestart) / NBPG; 783 } 784 785 /* Switch tables */ 786 #ifdef VERBOSE_INIT_ARM 787 printf("freestart = 0x%08lx, free_pages = %d (0x%x)\n", 788 physical_freestart, free_pages, free_pages); 789 printf("switching to new L1 page table @%#lx...", kernel_l1pt.pv_pa); 790 #endif 791 setttb(kernel_l1pt.pv_pa); 792 793 #ifdef VERBOSE_INIT_ARM 794 printf("done!\n"); 795 #endif 796 797 #ifdef VERBOSE_INIT_ARM 798 printf("bootstrap done.\n"); 799 #endif 800 801 /* Right, set up the vectors at the bottom of page 0 */ 802 memcpy((char *)0x00000000, page0, page0_end - page0); 803 804 /* We have modified a text page so sync the icache */ 805 cpu_icache_sync_all(); 806 807 /* 808 * Pages were allocated during the secondary bootstrap for the 809 * stacks for different CPU modes. 810 * We must now set the r13 registers in the different CPU modes to 811 * point to these stacks. 812 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 813 * of the stack memory. 814 */ 815 printf("init subsystems: stacks "); 816 817 set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE * NBPG); 818 set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE * NBPG); 819 set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE * NBPG); 820 821 /* 822 * Well we should set a data abort handler. 823 * Once things get going this will change as we will need a proper 824 * handler. 825 * Until then we will use a handler that just panics but tells us 826 * why. 827 * Initialisation of the vectors will just panic on a data abort. 828 * This just fills in a slighly better one. 829 */ 830 printf("vectors "); 831 data_abort_handler_address = (u_int)data_abort_handler; 832 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 833 undefined_handler_address = (u_int)undefinedinstruction_bounce; 834 835 /* At last ! 836 * We now have the kernel in physical memory from the bottom upwards. 837 * Kernel page tables are physically above this. 838 * The kernel is mapped to KERNEL_TEXT_BASE 839 * The kernel data PTs will handle the mapping of 0xf1000000-0xf3ffffff 840 * The page tables are mapped to 0xefc00000 841 */ 842 843 /* Initialise the undefined instruction handlers */ 844 printf("undefined "); 845 undefined_init(); 846 847 /* Boot strap pmap telling it where the kernel page table is */ 848 printf("pmap "); 849 pmap_bootstrap((pd_entry_t *)kernel_l1pt.pv_va, kernel_ptpt); 850 851 /* Setup the IRQ system */ 852 printf("irq "); 853 iq80310_intr_init(); 854 printf("done.\n"); 855 856 #ifdef IPKDB 857 /* Initialise ipkdb */ 858 ipkdb_init(); 859 if (boothowto & RB_KDB) 860 ipkdb_connect(0); 861 #endif 862 863 #ifdef DDB 864 db_machine_init(); 865 866 /* Firmware doesn't load symbols. */ 867 ddb_init(0, NULL, NULL); 868 869 if (boothowto & RB_KDB) 870 Debugger(); 871 #endif 872 873 /* We return the new stack pointer address */ 874 return(kernelstack.pv_va + USPACE_SVC_STACK_TOP); 875 } 876 877 #if 0 878 void 879 process_kernel_args(char *args) 880 { 881 static char bootargs[MAX_BOOT_STRING + 1]; 882 883 boothowto = 0; 884 885 /* Make a local copy of the bootargs */ 886 strncpy(bootargs, args, MAX_BOOT_STRING); 887 888 args = bootargs; 889 boot_file = bootargs; 890 891 /* Skip the kernel image filename */ 892 while (*args != ' ' && *args != 0) 893 ++args; 894 895 if (*args != 0) 896 *args++ = 0; 897 898 while (*args == ' ') 899 ++args; 900 901 boot_args = args; 902 903 printf("bootfile: %s\n", boot_file); 904 printf("bootargs: %s\n", boot_args); 905 906 parse_mi_bootargs(boot_args); 907 } 908 #endif 909 910 void 911 consinit(void) 912 { 913 static const bus_addr_t comcnaddrs[] = { 914 IQ80310_UART2, /* com0 (J9) */ 915 IQ80310_UART1, /* com1 (J10) */ 916 }; 917 static int consinit_called; 918 919 if (consinit_called != 0) 920 return; 921 922 consinit_called = 1; 923 924 #if NCOM > 0 925 if (comcnattach(&obio_bs_tag, comcnaddrs[comcnunit], comcnspeed, 926 COM_FREQ, comcnmode)) 927 panic("can't init serial console @%lx", comcnaddrs[comcnunit]); 928 #else 929 panic("serial console @%lx not configured", comcnaddrs[comcnunit]); 930 #endif 931 } 932
Indexes created Mon Oct 20 20:10:13 GMT 2025