iq80310_pci.c revision 1.2
1 /* $NetBSD: iq80310_pci.c,v 1.2 2001/11/09 22:47:48 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * IQ80310 PCI interrupt support, using he i80312 Companion I/O chip. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/autoconf.h> 47 #include <machine/bus.h> 48 49 #include <evbarm/iq80310/iq80310reg.h> 50 #include <evbarm/iq80310/iq80310var.h> 51 52 #include <arm/xscale/i80312reg.h> 53 #include <arm/xscale/i80312var.h> 54 55 #include <dev/pci/pcidevs.h> 56 #include <dev/pci/ppbreg.h> 57 58 int iq80310_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 59 const char *iq80310_pci_intr_string(void *, pci_intr_handle_t); 60 const struct evcnt *iq80310_pci_intr_evcnt(void *, pci_intr_handle_t); 61 void *iq80310_pci_intr_establish(void *, pci_intr_handle_t, 62 int, int (*func)(void *), void *); 63 void iq80310_pci_intr_disestablish(void *, void *); 64 65 void 66 iq80310_pci_init(pci_chipset_tag_t pc, void *cookie) 67 { 68 69 pc->pc_intr_v = cookie; /* the i80312 softc */ 70 pc->pc_intr_map = iq80310_pci_intr_map; 71 pc->pc_intr_string = iq80310_pci_intr_string; 72 pc->pc_intr_evcnt = iq80310_pci_intr_evcnt; 73 pc->pc_intr_establish = iq80310_pci_intr_establish; 74 pc->pc_intr_disestablish = iq80310_pci_intr_disestablish; 75 } 76 77 int 78 iq80310_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 79 { 80 struct i80312_softc *sc = pa->pa_pc->pc_intr_v; 81 pcitag_t tag; 82 pcireg_t reg; 83 int sbus, pbus; 84 85 /* 86 * Mapping of PCI interrupts on the IQ80310 is pretty easy; there 87 * is a single interrupt line for all PCI devices on pre-F boards, 88 * and an interrupt line for each INTx# signal on F and later boards. 89 * 90 * The only exception is the on-board Ethernet; this devices has 91 * its own dedicated interrupt line. The location of this device 92 * looks like this: 93 * 94 * 80312 Secondary -> PPB at dev #7 -> i82559 at dev #0 95 * 96 * In order to determine if we're mapping the interrupt for the 97 * on-board Ethernet, we must read the Secondary Bus # of the 98 * i80312, then use that to read the Secondary Bus # of the 99 * 21154 PPB. At that point, we know that b/d/f of the i82559, 100 * and can determine if we're looking at that device. 101 */ 102 103 reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 104 pbus = PPB_BUSINFO_PRIMARY(reg); 105 sbus = PPB_BUSINFO_SECONDARY(reg); 106 107 /* 108 * XXX We don't know how to map interrupts on the Primary 109 * XXX PCI bus right now. 110 */ 111 if (pa->pa_bus == pbus) { 112 printf("iq80310_pci_intr_map: can't map interrupts on " 113 "Primary bus\n"); 114 return (1); 115 } 116 117 tag = pci_make_tag(pa->pa_pc, sbus, 7, 0); 118 119 /* Make sure the PPB is there. */ 120 reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG); 121 if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID || 122 PCI_VENDOR(reg) == 0) { 123 /* 124 * That's odd... no PPB there? Oh well, issue a warning 125 * and continue on. 126 */ 127 printf("iq80310_pci_intr_map: PPB not found at %d/%d/%d ??\n", 128 sbus, 7, 0); 129 goto pinmap; 130 } 131 132 /* Make sure the device that's there is a PPB. */ 133 reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG); 134 if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE || 135 PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI) { 136 /* 137 * That's odd... the device that's there isn't a PPB. 138 * Oh well, issue a warning and continue on. 139 */ 140 printf("iq80310_pci_intr_map: %d/%d/%d isn't a PPB ??\n", 141 sbus, 7, 0); 142 goto pinmap; 143 } 144 145 /* Now read the PPB's secondary bus number. */ 146 reg = pci_conf_read(pa->pa_pc, tag, PPB_REG_BUSINFO); 147 sbus = PPB_BUSINFO_SECONDARY(reg); 148 149 if (pa->pa_bus == sbus && pa->pa_device == 0 && 150 pa->pa_function == 0) { 151 /* On-board i82559 Ethernet! */ 152 *ihp = XINT3_IRQ(XINT3_ETHERNET); 153 return (0); 154 } 155 156 pinmap: 157 if (pa->pa_intrpin == 0) { 158 /* No IRQ used. */ 159 return (1); 160 } 161 if (pa->pa_intrpin > 4) { 162 printf("iq80310_pci_intr_map: bad interrupt pin %d\n", 163 pa->pa_intrpin); 164 return (1); 165 } 166 167 /* INTD# is always in XINT3. */ 168 if (pa->pa_intrpin == 4) { 169 *ihp = XINT3_IRQ(XINT3_SINTD); 170 return (0); 171 } 172 173 /* On pre-F boards, ALL of them are on XINT3. */ 174 if (/*pre-F*/0) 175 *ihp = XINT3_IRQ(XINT3_SINTD); 176 else 177 *ihp = XINT0_IRQ(pa->pa_intrpin - 1); 178 179 return (0); 180 } 181 182 const char * 183 iq80310_pci_intr_string(void *v, pci_intr_handle_t ih) 184 { 185 static char irqstr[sizeof("CPLD irq xx")]; 186 187 sprintf(irqstr, "CPLD irq %ld", ih); 188 return (irqstr); 189 } 190 191 const struct evcnt * 192 iq80310_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 193 { 194 195 /* XXX For now. */ 196 return (NULL); 197 } 198 199 void * 200 iq80310_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 201 int (*func)(void *), void *arg) 202 { 203 204 return (iq80310_intr_establish(ih, ipl, func, arg)); 205 } 206 207 void 208 iq80310_pci_intr_disestablish(void *v, void *cookie) 209 { 210 211 iq80310_intr_disestablish(cookie); 212 } 213
Indexes created Tue Oct 21 06:10:07 GMT 2025