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iq80310_start.S revision 1.4 
      1 /*	$NetBSD: iq80310_start.S,v 1.4 2002/10/14 22:32:53 bjh21 Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2002 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed for the NetBSD Project by
     20  *	Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 #include <machine/asm.h>
     39 #include <arm/armreg.h>
     40 #include <arm/arm32/pte.h>
     41 
     42 	.section .start,"ax",%progbits
     43 
     44 	.global	_C_LABEL(iq80310_start)
     45 _C_LABEL(iq80310_start):
     46 	/*
     47 	 * We assume we've been loaded VA==PA, or that the MMU is
     48 	 * disabled.  We will go ahead and disable the MMU here
     49 	 * so that we don't have to worry about flushing caches, etc.
     50 	 */
     51 	mrc	p15, 0, r2, c1, c0, 0
     52 	bic	r2, r2, #CPU_CONTROL_MMU_ENABLE
     53 	mcr	p15, 0, r2, c1, c0, 0
     54 
     55 	nop
     56 	nop
     57 	nop
     58 
     59 	/*
     60 	 * We want to construct a memory map that maps us
     61 	 * VA==PA (SDRAM at 0xa0000000) and also double-maps
     62 	 * that space at 0xc0000000 (where the kernel address
     63 	 * space starts).  We create these mappings uncached
     64 	 * and unbuffered to be safe.
     65 	 *
     66 	 * We also want to map the various devices we want to
     67 	 * talk to VA==PA during bootstrap.
     68 	 *
     69 	 * We just use section mappings for all of this to make it easy.
     70 	 *
     71 	 * We will put the L1 table to do all this at 0xa0004000, which
     72 	 * is also where RedBoot puts it.
     73 	 */
     74 
     75 	/*
     76 	 * Step 1: Map the entire address space VA==PA.
     77 	 */
     78 	adr	r0, Ltable
     79 	ldr	r0, [r0]			/* r0 = &l1table */
     80 
     81 	mov	r3, #(L1_S_AP(AP_KRW))
     82 	orr	r3, r3, #(L1_TYPE_S)
     83 	mov	r2, #0x100000			/* advance by 1MB */
     84 	mov	r1, #0x1000			/* 4096MB */
     85 1:
     86 	str	r3, [r0], #0x04
     87 	add	r3, r3, r2
     88 	subs	r1, r1, #1
     89 	bgt	1b
     90 
     91 	/*
     92 	 * Step 2: Map VA 0xc0000000->0xc3ffffff to PA 0xa0000000->0xa3ffffff.
     93 	 */
     94 	adr	r0, Ltable			/* r0 = &l1table */
     95 	ldr	r0, [r0]
     96 
     97 	mov	r3, #(L1_S_AP(AP_KRW))
     98 	orr	r3, r3, #(L1_TYPE_S)
     99 	orr	r3, r3, #0xa0000000
    100 	add	r0, r0, #(0xc00 * 4)		/* offset to 0xc00xxxxx */
    101 	mov	r1, #0x40			/* 64MB */
    102 1:
    103 	str	r3, [r0], #0x04
    104 	add	r3, r3, r2
    105 	subs	r1, r1, #1
    106 	bgt	1b
    107 
    108 	/* OK!  Page table is set up.  Give it to the CPU. */
    109 	adr	r0, Ltable
    110 	ldr	r0, [r0]
    111 	mcr	p15, 0, r0, c2, c0, 0
    112 
    113 	/* Flush the old TLBs, just in case. */
    114 	mcr	p15, 0, r0, c8, c7, 0
    115 
    116 	/* Set the Domain Access register.  Very important! */
    117 	mov	r0, #1
    118 	mcr	p15, 0, r0, c3, c0, 0
    119 
    120 	/* Get ready to jump to the "real" kernel entry point... */
    121 	ldr	r0, Lstart
    122 
    123 	/* OK, let's enable the MMU. */
    124 	mrc	p15, 0, r2, c1, c0, 0
    125 	orr	r2, r2, #CPU_CONTROL_MMU_ENABLE
    126 	mcr	p15, 0, r2, c1, c0, 0
    127 
    128 	nop
    129 	nop
    130 	nop
    131 
    132 	/* CPWAIT sequence to make sure the MMU is on... */
    133 	mrc	p15, 0, r2, c2, c0, 0	/* arbitrary read of CP15 */
    134 	mov	r2, r2			/* force it to complete */
    135 	mov	pc, r0			/* leap to kernel entry point! */
    136 
    137 Ltable:
    138 	.word	0xa0004000
    139 
    140 Lstart:
    141 	.word	start
    142