iq80310reg.h revision 1.3
1 /* $NetBSD: iq80310reg.h,v 1.3 2001/11/08 03:28:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _IQ80310REG_H_ 39 #define _IQ80310REG_H_ 40 41 /* 42 * Memory map and register definitions for the Intel IQ80310 43 * Evaluation Board. 44 */ 45 46 /* 47 * The memory map of the IQ80310 looks like so: 48 * 49 * ------------------------------ 50 * On-board devices 51 * Flash Bank 0 52 * FE80 0000 ------------------------------ 53 * DRAM 54 * A000 0000 ------------------------------ 55 * Reserved 56 * 9002 0000 ------------------------------ 57 * ATU Outbound Transaction 58 * Windows 59 * 8000 0000 ------------------------------ 60 * ATU Outbound Direct 61 * Addressing Windows 62 * 0080 0000 ------------------------------ 63 * Flash Bank 1 64 * 0000 2000 ------------------------------ 65 * Reserved 66 * 0000 1900 ------------------------------ 67 * Peripheral Memory Mapped 68 * Registers 69 * 0000 1000 ------------------------------ 70 * Initialization Boot Code 71 * from Flash Bank 1 72 * 0000 0000 ------------------------------ 73 */ 74 75 /* 76 * We map the CPLD registers VA==PA, so we go ahead and cheat 77 * with register access. 78 */ 79 #define CPLD_READ(x) *((__volatile uint8_t *)(x)) 80 #define CPLD_WRITE(x, v) *((__volatile uint8_t *)(x)) = (v) 81 82 /* 83 * We allocate a page table for VA 0xfe400000 (4MB) and map the i80312 84 * PCI I/O space (2 * 64L) and i80312 regisers (4K) there. 85 */ 86 #define IQ80310_IOPXS_VBASE 0xfe400000UL 87 #define IQ80310_PIOW_VBASE IQ80310_IOPXS_VBASE 88 #define IQ80310_SIOW_VBASE (IQ80310_PIOW_VBASE + I80312_PCI_XLATE_IOSIZE) 89 #define IQ80310_80312_VBASE (IQ80310_SIOW_VBASE + I80312_PCI_XLATE_IOSIZE) 90 91 /* 92 * The IQ80310 on-board devices are mapped VA==PA during bootstrap. 93 * Conveniently, the size of the on-board register space is 1 section 94 * mapping. 95 */ 96 #define IQ80310_OBIO_BASE 0xfe800000UL 97 #define IQ80310_OBIO_SIZE 0x00100000UL /* 1MB */ 98 99 #define IQ80310_UART1 0xfe800000UL /* XR 16550 */ 100 101 #define IQ80310_UART2 0xfe810000UL /* XR 16550 */ 102 103 #define IQ80310_XINT3_STATUS 0xfe820000UL 104 #define XINT3_TIMER 0 /* CPLD timer */ 105 #define XINT3_ETHERNET 1 /* on-board i82559 */ 106 #define XINT3_UART1 2 /* 16550 #1 */ 107 #define XINT3_UART2 3 /* 16550 #2 */ 108 #define XINT3_SINTD 4 /* INTD# */ 109 #define XINT3_BIT(x) (1U << (x)) 110 111 #define IQ80310_BOARD_REV 0xfe830000UL /* rev F and later (??) */ 112 #define BOARD_REV(x) (((x) & 0xf) + '@') 113 114 #define IQ80310_CPLD_REV 0xfe840000UL 115 #define CPLD_REV(x) (((x) & 0xf) + '@') 116 117 #define IQ80310_7SEG_MSB 0xfe840000UL 118 #define IQ80310_7SEG_LSB 0xfe850000UL 119 /* 120 * The 7-segment display looks like so: 121 * 122 * A 123 * +-----+ 124 * | | 125 * F | | B 126 * | G | 127 * +-----+ 128 * | | 129 * E | | C 130 * | D | 131 * +-----+ o DP 132 * 133 * Setting a bit clears the corresponding segment on the 134 * display. 135 */ 136 #define SEG_A (1U << 0) 137 #define SEG_B (1U << 1) 138 #define SEG_C (1U << 2) 139 #define SEG_D (1U << 3) 140 #define SEG_E (1U << 4) 141 #define SEG_F (1U << 5) 142 #define SEG_G (1U << 6) 143 #define SEG_DP (1U << 7) 144 145 #define IQ80310_XINT0_STATUS 0xfe850000UL /* rev F and later */ 146 #define XINT0_SINTA 0 /* INTA# */ 147 #define XINT0_SINTB 1 /* INTB# */ 148 #define XINT0_SINTC 2 /* INTC# */ 149 #define XINT0_BIT(x) (1U << (x)) 150 151 #define IQ80310_XINT_MASK 0xfe860000UL 152 /* See XINT_STATUS bits: 0 == int enabled, 1 == int disabled */ 153 154 #define IQ80310_BACKPLANE_DET 0xfe870000UL 155 156 #define IQ80310_TIMER_LA0 0xfe880000UL 157 158 #define IQ80310_TIMER_LA1 0xfe890000UL 159 160 #define IQ80310_TIMER_LA2 0xfe8a0000UL 161 162 #define IQ80310_TIMER_LA3 0xfe8b0000UL 163 164 #define IQ80310_TIMER_ENABLE 0xfe8c0000UL 165 #define TIMER_ENABLE_EN (1U << 0) /* enable counter */ 166 #define TIMER_ENABLE_INTEN (1U << 1) /* enable interrupt */ 167 168 #define IQ80310_ROT_SWITCH 0xfe8d0000UL 169 170 #define IQ80310_JTAG 0xfe8e0000UL 171 172 #define IQ80310_BATTERY_STAT 0xfe8f0000UL 173 #define BATTERY_STAT_PRES (1U << 0) 174 #define BATTERY_STAT_CHRG (1U << 1) 175 #define BATTERY_STAT_DISCHRG (1U << 2) 176 #define BATTERY_STAT_PWRDELAY (1U << 3) /* rev F and later */ 177 178 #endif /* _IQ80310REG_H_ */ 179
Indexes created Fri Oct 03 02:09:57 GMT 2025