i80321_mainbus.c revision 1.1.8.2 1 /* $NetBSD: i80321_mainbus.c,v 1.1.8.2 2002/10/18 02:36:33 nathanw Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * IQ80321 front-end for the i80321 I/O Processor. We take care
40 * of setting up the i80321 memory map, PCI interrupt routing, etc.,
41 * which are all specific to the board the i80321 is wired up to.
42 */
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/device.h>
47
48 #include <machine/autoconf.h>
49 #include <machine/bus.h>
50
51 #include <evbarm/iq80321/iq80321reg.h>
52 #include <evbarm/iq80321/iq80321var.h>
53
54 #include <arm/xscale/i80321reg.h>
55 #include <arm/xscale/i80321var.h>
56
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcidevs.h>
59
60 int i80321_mainbus_match(struct device *, struct cfdata *, void *);
61 void i80321_mainbus_attach(struct device *, struct device *, void *);
62
63 CFATTACH_DECL(iopxs_mainbus, sizeof(struct i80321_softc),
64 i80321_mainbus_match, i80321_mainbus_attach, NULL, NULL);
65
66 /* There can be only one. */
67 int i80321_mainbus_found;
68
69 int
70 i80321_mainbus_match(struct device *parent, struct cfdata *cf, void *aux)
71 {
72 #if 0
73 struct mainbus_attach_args *ma = aux;
74 #endif
75
76 if (i80321_mainbus_found)
77 return (0);
78
79 #if 1
80 /* XXX Shoot arch/arm/mainbus in the head. */
81 return (1);
82 #else
83 if (strcmp(cf->cf_name, ma->ma_name) == 0)
84 return (1);
85
86 return (0);
87 #endif
88 }
89
90 void
91 i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
92 {
93 struct i80321_softc *sc = (void *) self;
94 paddr_t memstart;
95 psize_t memsize;
96
97 i80321_mainbus_found = 1;
98
99 /*
100 * Fill in the space tag for the i80321's own devices,
101 * and hand-craft the space handle for it (the device
102 * was mapped during early bootstrap).
103 */
104 i80321_bs_init(&i80321_bs_tag, sc);
105 sc->sc_st = &i80321_bs_tag;
106 sc->sc_sh = IQ80321_80321_VBASE;
107
108 /*
109 * Slice off a subregion for the Memory Controller -- we need it
110 * here in order read the memory size.
111 */
112 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE,
113 VERDE_MCU_SIZE, &sc->sc_mcu_sh))
114 panic("%s: unable to subregion MCU registers",
115 sc->sc_dev.dv_xname);
116
117 /*
118 * We have mapped the the PCI I/O windows in the early
119 * bootstrap phase.
120 */
121 sc->sc_iow_vaddr = IQ80321_IOW_VBASE;
122
123 /* Some boards are always considered "host". */
124 sc->sc_is_host = 1; /* XXX */
125
126 printf(": i80321 I/O Processor, acting as PCI %s\n",
127 sc->sc_is_host ? "host" : "slave");
128
129 i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize);
130
131 /*
132 * We set up the Inbound Windows as follows:
133 *
134 * 0 Access to i80321 PMMRs
135 *
136 * 1 Reserve space for private devices
137 *
138 * 2 RAM access
139 *
140 * 3 Unused.
141 *
142 * This chunk needs to be customized for each IOP321 application.
143 */
144 #if 0
145 sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE;
146 sc->sc_iwin[0].iwin_base_hi = 0;
147 sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE;
148 sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE;
149 #endif
150
151 if (sc->sc_is_host) {
152 /* Map PCI:Local 1:1. */
153 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
154 PCI_MAPREG_MEM_PREFETCHABLE_MASK |
155 PCI_MAPREG_MEM_TYPE_64BIT;
156 sc->sc_iwin[1].iwin_base_hi = 0;
157 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
158 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
159 } else {
160 panic("i80321: iwin[1] slave");
161 }
162
163 if (sc->sc_is_host) {
164 sc->sc_iwin[2].iwin_base_lo = memstart |
165 PCI_MAPREG_MEM_PREFETCHABLE_MASK |
166 PCI_MAPREG_MEM_TYPE_64BIT;
167 sc->sc_iwin[2].iwin_base_hi = 0;
168 sc->sc_iwin[2].iwin_xlate = memstart;
169 sc->sc_iwin[2].iwin_size = memsize;
170 } else {
171 panic("i80321: iwin[2] slave");
172 }
173
174 /*
175 * We set up the Outbound Windows as follows:
176 *
177 * 0 Access to private PCI space.
178 *
179 * 1 Unused.
180 */
181 sc->sc_owin[0].owin_xlate_lo =
182 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
183 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
184
185 /*
186 * Set the Secondary Outbound I/O window to map
187 * to PCI address 0 for all 64K of the I/O space.
188 */
189 sc->sc_ioout_xlate = 0;
190
191 /*
192 * Initialize the interrupt part of our PCI chipset tag.
193 */
194 iq80321_pci_init(&sc->sc_pci_chipset, sc);
195
196 i80321_attach(sc);
197 }
198