i80321_mainbus.c revision 1.10
1 /* $NetBSD: i80321_mainbus.c,v 1.10 2003/07/15 00:25:04 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * IQ80321 front-end for the i80321 I/O Processor. We take care 40 * of setting up the i80321 memory map, PCI interrupt routing, etc., 41 * which are all specific to the board the i80321 is wired up to. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: i80321_mainbus.c,v 1.10 2003/07/15 00:25:04 lukem Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 51 #include <machine/autoconf.h> 52 #include <machine/bus.h> 53 54 #include <evbarm/iq80321/iq80321reg.h> 55 #include <evbarm/iq80321/iq80321var.h> 56 57 #include <arm/xscale/i80321reg.h> 58 #include <arm/xscale/i80321var.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 int i80321_mainbus_match(struct device *, struct cfdata *, void *); 64 void i80321_mainbus_attach(struct device *, struct device *, void *); 65 66 CFATTACH_DECL(iopxs_mainbus, sizeof(struct i80321_softc), 67 i80321_mainbus_match, i80321_mainbus_attach, NULL, NULL); 68 69 /* There can be only one. */ 70 int i80321_mainbus_found; 71 72 int 73 i80321_mainbus_match(struct device *parent, struct cfdata *cf, void *aux) 74 { 75 #if 0 76 struct mainbus_attach_args *ma = aux; 77 #endif 78 79 if (i80321_mainbus_found) 80 return (0); 81 82 #if 1 83 /* XXX Shoot arch/arm/mainbus in the head. */ 84 return (1); 85 #else 86 if (strcmp(cf->cf_name, ma->ma_name) == 0) 87 return (1); 88 89 return (0); 90 #endif 91 } 92 93 void 94 i80321_mainbus_attach(struct device *parent, struct device *self, void *aux) 95 { 96 struct i80321_softc *sc = (void *) self; 97 paddr_t memstart; 98 psize_t memsize; 99 100 i80321_mainbus_found = 1; 101 102 /* 103 * Fill in the space tag for the i80321's own devices, 104 * and hand-craft the space handle for it (the device 105 * was mapped during early bootstrap). 106 */ 107 i80321_bs_init(&i80321_bs_tag, sc); 108 sc->sc_st = &i80321_bs_tag; 109 sc->sc_sh = IQ80321_80321_VBASE; 110 111 /* 112 * Slice off a subregion for the Memory Controller -- we need it 113 * here in order read the memory size. 114 */ 115 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE, 116 VERDE_MCU_SIZE, &sc->sc_mcu_sh)) 117 panic("%s: unable to subregion MCU registers", 118 sc->sc_dev.dv_xname); 119 120 /* 121 * We have mapped the the PCI I/O windows in the early 122 * bootstrap phase. 123 */ 124 sc->sc_iow_vaddr = IQ80321_IOW_VBASE; 125 126 /* Some boards are always considered "host". */ 127 sc->sc_is_host = 1; /* XXX */ 128 129 aprint_naive(": i80321 I/O Processor\n"); 130 aprint_normal(": i80321 I/O Processor, acting as PCI %s\n", 131 sc->sc_is_host ? "host" : "slave"); 132 133 i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize); 134 135 /* 136 * We set up the Inbound Windows as follows: 137 * 138 * 0 Access to i80321 PMMRs 139 * 140 * 1 Reserve space for private devices 141 * 142 * 2 Unused. 143 * 144 * 3 RAM access 145 * 146 * This chunk needs to be customized for each IOP321 application. 147 */ 148 #if 0 149 sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE; 150 sc->sc_iwin[0].iwin_base_hi = 0; 151 sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE; 152 sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE; 153 #endif 154 155 if (sc->sc_is_host) { 156 /* Map PCI:Local 1:1. */ 157 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE | 158 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 159 PCI_MAPREG_MEM_TYPE_64BIT; 160 sc->sc_iwin[1].iwin_base_hi = 0; 161 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE; 162 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE; 163 } else { 164 panic("i80321: iwin[1] slave"); 165 } 166 167 if (sc->sc_is_host) { 168 sc->sc_iwin[2].iwin_base_lo = memstart | 169 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 170 PCI_MAPREG_MEM_TYPE_64BIT; 171 sc->sc_iwin[2].iwin_base_hi = 0; 172 sc->sc_iwin[2].iwin_xlate = memstart; 173 sc->sc_iwin[2].iwin_size = memsize; 174 } else { 175 panic("i80321: iwin[2] slave"); 176 } 177 178 sc->sc_iwin[3].iwin_base_lo = 0 | 179 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 180 PCI_MAPREG_MEM_TYPE_64BIT; 181 sc->sc_iwin[3].iwin_base_hi = 0; 182 sc->sc_iwin[3].iwin_xlate = 0; 183 sc->sc_iwin[3].iwin_size = 0; 184 185 /* 186 * We set up the Outbound Windows as follows: 187 * 188 * 0 Access to private PCI space. 189 * 190 * 1 Unused. 191 */ 192 sc->sc_owin[0].owin_xlate_lo = 193 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo); 194 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi; 195 196 /* 197 * Set the Secondary Outbound I/O window to map 198 * to PCI address 0 for all 64K of the I/O space. 199 */ 200 sc->sc_ioout_xlate = 0; 201 202 /* 203 * Initialize the interrupt part of our PCI chipset tag. 204 */ 205 iq80321_pci_init(&sc->sc_pci_chipset, sc); 206 207 i80321_attach(sc); 208 } 209
Indexes created Wed Oct 22 00:09:40 GMT 2025