i80321_mainbus.c revision 1.17.2.1
1 /* $NetBSD: i80321_mainbus.c,v 1.17.2.1 2012/04/17 00:06:14 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * IQ80321 front-end for the i80321 I/O Processor. We take care 40 * of setting up the i80321 memory map, PCI interrupt routing, etc., 41 * which are all specific to the board the i80321 is wired up to. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: i80321_mainbus.c,v 1.17.2.1 2012/04/17 00:06:14 yamt Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 51 #include <machine/autoconf.h> 52 #include <sys/bus.h> 53 54 #include <evbarm/iq80321/iq80321reg.h> 55 #include <evbarm/iq80321/iq80321var.h> 56 57 #include <arm/xscale/i80321reg.h> 58 #include <arm/xscale/i80321var.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 int i80321_mainbus_match(device_t, cfdata_t, void *); 64 void i80321_mainbus_attach(device_t, device_t, void *); 65 66 CFATTACH_DECL_NEW(iopxs_mainbus, sizeof(struct i80321_softc), 67 i80321_mainbus_match, i80321_mainbus_attach, NULL, NULL); 68 69 /* There can be only one. */ 70 int i80321_mainbus_found; 71 72 int 73 i80321_mainbus_match(device_t parent, cfdata_t cf, void *aux) 74 { 75 #if 0 76 struct mainbus_attach_args *ma = aux; 77 #endif 78 79 if (i80321_mainbus_found) 80 return (0); 81 82 #if 1 83 /* XXX Shoot arch/arm/mainbus in the head. */ 84 return (1); 85 #else 86 if (strcmp(cf->cf_name, ma->ma_name) == 0) 87 return (1); 88 89 return (0); 90 #endif 91 } 92 93 void 94 i80321_mainbus_attach(device_t parent, device_t self, void *aux) 95 { 96 struct i80321_softc *sc = device_private(self); 97 const char *xname = device_xname(self); 98 pcireg_t b0u, b0l, b1u, b1l; 99 paddr_t memstart; 100 psize_t memsize; 101 102 sc->sc_dev = self; 103 i80321_mainbus_found = 1; 104 105 /* 106 * Fill in the space tag for the i80321's own devices, 107 * and hand-craft the space handle for it (the device 108 * was mapped during early bootstrap). 109 */ 110 i80321_bs_init(&i80321_bs_tag, sc); 111 sc->sc_st = &i80321_bs_tag; 112 sc->sc_sh = IQ80321_80321_VBASE; 113 114 /* 115 * Slice off a subregion for the Memory Controller -- we need it 116 * here in order read the memory size. 117 */ 118 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE, 119 VERDE_MCU_SIZE, &sc->sc_mcu_sh)) 120 panic("%s: unable to subregion MCU registers", xname); 121 122 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE, 123 VERDE_ATU_SIZE, &sc->sc_atu_sh)) 124 panic("%s: unable to subregion ATU registers", xname); 125 126 /* 127 * We have mapped the PCI I/O windows in the early bootstrap phase. 128 */ 129 sc->sc_iow_vaddr = IQ80321_IOW_VBASE; 130 131 /* 132 * Check the configuration of the ATU to see if another BIOS 133 * has configured us. If a PC BIOS didn't configure us, then: 134 * IQ80321: BAR0 00000000.0000000c BAR1 is 00000000.8000000c. 135 * IQ31244: BAR0 00000000.00000004 BAR1 is 00000000.0000000c. 136 * If a BIOS has configured us, at least one of those should be 137 * different. This is pretty fragile, but it's not clear what 138 * would work better. 139 */ 140 b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0); 141 b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4); 142 b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8); 143 b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc); 144 b0l &= PCI_MAPREG_MEM_ADDR_MASK; 145 b0u &= PCI_MAPREG_MEM_ADDR_MASK; 146 b1l &= PCI_MAPREG_MEM_ADDR_MASK; 147 b1u &= PCI_MAPREG_MEM_ADDR_MASK; 148 149 if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0)) 150 sc->sc_is_host = 0; 151 else 152 sc->sc_is_host = 1; 153 154 aprint_naive(": i80321 I/O Processor\n"); 155 aprint_normal(": i80321 I/O Processor, acting as PCI %s\n", 156 sc->sc_is_host ? "host" : "slave"); 157 158 i80321_intr_evcnt_attach(); 159 160 i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize); 161 162 /* 163 * We set up the Inbound Windows as follows: 164 * 165 * 0 Access to i80321 PMMRs 166 * 167 * 1 Reserve space for private devices 168 * 169 * 2 RAM access 170 * 171 * 3 Unused. 172 * 173 * This chunk needs to be customized for each IOP321 application. 174 */ 175 #if 0 176 sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE; 177 sc->sc_iwin[0].iwin_base_hi = 0; 178 sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE; 179 sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE; 180 #endif 181 182 if (sc->sc_is_host) { 183 /* Map PCI:Local 1:1. */ 184 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE | 185 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 186 PCI_MAPREG_MEM_TYPE_64BIT; 187 sc->sc_iwin[1].iwin_base_hi = 0; 188 } else { 189 sc->sc_iwin[1].iwin_base_lo = 0; 190 sc->sc_iwin[1].iwin_base_hi = 0; 191 } 192 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE; 193 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE; 194 195 if (sc->sc_is_host) { 196 sc->sc_iwin[2].iwin_base_lo = memstart | 197 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 198 PCI_MAPREG_MEM_TYPE_64BIT; 199 sc->sc_iwin[2].iwin_base_hi = 0; 200 } else { 201 sc->sc_iwin[2].iwin_base_lo = 0; 202 sc->sc_iwin[2].iwin_base_hi = 0; 203 } 204 sc->sc_iwin[2].iwin_xlate = memstart; 205 sc->sc_iwin[2].iwin_size = memsize; 206 207 if (sc->sc_is_host) { 208 sc->sc_iwin[3].iwin_base_lo = 0 | 209 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 210 PCI_MAPREG_MEM_TYPE_64BIT; 211 } else { 212 sc->sc_iwin[3].iwin_base_lo = 0; 213 } 214 sc->sc_iwin[3].iwin_base_hi = 0; 215 sc->sc_iwin[3].iwin_xlate = 0; 216 sc->sc_iwin[3].iwin_size = 0; 217 218 /* 219 * We set up the Outbound Windows as follows: 220 * 221 * 0 Access to private PCI space. 222 * 223 * 1 Unused. 224 */ 225 sc->sc_owin[0].owin_xlate_lo = 226 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo); 227 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi; 228 229 /* 230 * Set the Secondary Outbound I/O window to map 231 * to PCI address 0 for all 64K of the I/O space. 232 */ 233 sc->sc_ioout_xlate = 0; 234 sc->sc_ioout_xlate_offset = 0x1000; 235 236 /* 237 * Initialize the interrupt part of our PCI chipset tag. 238 */ 239 iq80321_pci_init(&sc->sc_pci_chipset, sc); 240 241 i80321_attach(sc); 242 } 243
Indexes created Wed Oct 22 00:09:40 GMT 2025