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i80321_mainbus.c revision 1.5
      1 /*	$NetBSD: i80321_mainbus.c,v 1.5 2002/10/02 05:10:35 thorpej Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed for the NetBSD Project by
     20  *	Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 /*
     39  * IQ80321 front-end for the i80321 I/O Processor.  We take care
     40  * of setting up the i80321 memory map, PCI interrupt routing, etc.,
     41  * which are all specific to the board the i80321 is wired up to.
     42  */
     43 
     44 #include <sys/param.h>
     45 #include <sys/systm.h>
     46 #include <sys/device.h>
     47 
     48 #include <machine/autoconf.h>
     49 #include <machine/bus.h>
     50 
     51 #include <evbarm/iq80321/iq80321reg.h>
     52 #include <evbarm/iq80321/iq80321var.h>
     53 
     54 #include <arm/xscale/i80321reg.h>
     55 #include <arm/xscale/i80321var.h>
     56 
     57 #include <dev/pci/pcireg.h>
     58 #include <dev/pci/pcidevs.h>
     59 
     60 int	i80321_mainbus_match(struct device *, struct cfdata *, void *);
     61 void	i80321_mainbus_attach(struct device *, struct device *, void *);
     62 
     63 CFATTACH_DECL(iopxs_mainbus, sizeof(struct i80321_softc),
     64     i80321_mainbus_match, , NULL, NULL);
     65 };
     66 
     67 /* There can be only one. */
     68 int	i80321_mainbus_found;
     69 
     70 int
     71 i80321_mainbus_match(struct device *parent, struct cfdata *cf, void *aux)
     72 {
     73 #if 0
     74 	struct mainbus_attach_args *ma = aux;
     75 #endif
     76 
     77 	if (i80321_mainbus_found)
     78 		return (0);
     79 
     80 #if 1
     81 	/* XXX Shoot arch/arm/mainbus in the head. */
     82 	return (1);
     83 #else
     84 	if (strcmp(cf->cf_name, ma->ma_name) == 0)
     85 		return (1);
     86 
     87 	return (0);
     88 #endif
     89 }
     90 
     91 void
     92 i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
     93 {
     94 	struct i80321_softc *sc = (void *) self;
     95 	paddr_t memstart;
     96 	psize_t memsize;
     97 
     98 	i80321_mainbus_found = 1;
     99 
    100 	/*
    101 	 * Fill in the space tag for the i80321's own devices,
    102 	 * and hand-craft the space handle for it (the device
    103 	 * was mapped during early bootstrap).
    104 	 */
    105 	i80321_bs_init(&i80321_bs_tag, sc);
    106 	sc->sc_st = &i80321_bs_tag;
    107 	sc->sc_sh = IQ80321_80321_VBASE;
    108 
    109 	/*
    110 	 * Slice off a subregion for the Memory Controller -- we need it
    111 	 * here in order read the memory size.
    112 	 */
    113 	if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE,
    114 	    VERDE_MCU_SIZE, &sc->sc_mcu_sh))
    115 		panic("%s: unable to subregion MCU registers",
    116 		    sc->sc_dev.dv_xname);
    117 
    118 	/*
    119 	 * We have mapped the the PCI I/O windows in the early
    120 	 * bootstrap phase.
    121 	 */
    122 	sc->sc_iow_vaddr = IQ80321_IOW_VBASE;
    123 
    124 	/* Some boards are always considered "host". */
    125 	sc->sc_is_host = 1;		/* XXX */
    126 
    127 	printf(": i80321 I/O Processor, acting as PCI %s\n",
    128 	    sc->sc_is_host ? "host" : "slave");
    129 
    130 	i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize);
    131 
    132 	/*
    133 	 * We set up the Inbound Windows as follows:
    134 	 *
    135 	 *	0	Access to i80321 PMMRs
    136 	 *
    137 	 *	1	Reserve space for private devices
    138 	 *
    139 	 *	2	RAM access
    140 	 *
    141 	 *	3	Unused.
    142 	 *
    143 	 * This chunk needs to be customized for each IOP321 application.
    144 	 */
    145 #if 0
    146 	sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE;
    147 	sc->sc_iwin[0].iwin_base_hi = 0;
    148 	sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE;
    149 	sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE;
    150 #endif
    151 
    152 	if (sc->sc_is_host) {
    153 		/* Map PCI:Local 1:1. */
    154 		sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
    155 		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
    156 		    PCI_MAPREG_MEM_TYPE_64BIT;
    157 		sc->sc_iwin[1].iwin_base_hi = 0;
    158 		sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
    159 		sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
    160 	} else {
    161 		panic("i80321: iwin[1] slave");
    162 	}
    163 
    164 	if (sc->sc_is_host) {
    165 		sc->sc_iwin[2].iwin_base_lo = memstart |
    166 		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
    167 		    PCI_MAPREG_MEM_TYPE_64BIT;
    168 		sc->sc_iwin[2].iwin_base_hi = 0;
    169 		sc->sc_iwin[2].iwin_xlate = memstart;
    170 		sc->sc_iwin[2].iwin_size = memsize;
    171 	} else {
    172 		panic("i80321: iwin[2] slave");
    173 	}
    174 
    175 	/*
    176 	 * We set up the Outbound Windows as follows:
    177 	 *
    178 	 *	0	Access to private PCI space.
    179 	 *
    180 	 *	1	Unused.
    181 	 */
    182 	sc->sc_owin[0].owin_xlate_lo =
    183 	    PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
    184 	sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
    185 
    186 	/*
    187 	 * Set the Secondary Outbound I/O window to map
    188 	 * to PCI address 0 for all 64K of the I/O space.
    189 	 */
    190 	sc->sc_ioout_xlate = 0;
    191 
    192 	/*
    193 	 * Initialize the interrupt part of our PCI chipset tag.
    194 	 */
    195 	iq80321_pci_init(&sc->sc_pci_chipset, sc);
    196 
    197 	i80321_attach(sc);
    198 }
    199