i80321_mainbus.c revision 1.9.2.3 1 /* $NetBSD: i80321_mainbus.c,v 1.9.2.3 2004/09/21 13:14:48 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * IQ80321 front-end for the i80321 I/O Processor. We take care
40 * of setting up the i80321 memory map, PCI interrupt routing, etc.,
41 * which are all specific to the board the i80321 is wired up to.
42 */
43
44 #include <sys/cdefs.h>
45 __KERNEL_RCSID(0, "$NetBSD: i80321_mainbus.c,v 1.9.2.3 2004/09/21 13:14:48 skrll Exp $");
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/device.h>
50
51 #include <machine/autoconf.h>
52 #include <machine/bus.h>
53
54 #include <evbarm/iq80321/iq80321reg.h>
55 #include <evbarm/iq80321/iq80321var.h>
56
57 #include <arm/xscale/i80321reg.h>
58 #include <arm/xscale/i80321var.h>
59
60 #include <dev/pci/pcireg.h>
61 #include <dev/pci/pcidevs.h>
62
63 int i80321_mainbus_match(struct device *, struct cfdata *, void *);
64 void i80321_mainbus_attach(struct device *, struct device *, void *);
65
66 CFATTACH_DECL(iopxs_mainbus, sizeof(struct i80321_softc),
67 i80321_mainbus_match, i80321_mainbus_attach, NULL, NULL);
68
69 /* There can be only one. */
70 int i80321_mainbus_found;
71
72 int
73 i80321_mainbus_match(struct device *parent, struct cfdata *cf, void *aux)
74 {
75 #if 0
76 struct mainbus_attach_args *ma = aux;
77 #endif
78
79 if (i80321_mainbus_found)
80 return (0);
81
82 #if 1
83 /* XXX Shoot arch/arm/mainbus in the head. */
84 return (1);
85 #else
86 if (strcmp(cf->cf_name, ma->ma_name) == 0)
87 return (1);
88
89 return (0);
90 #endif
91 }
92
93 void
94 i80321_mainbus_attach(struct device *parent, struct device *self, void *aux)
95 {
96 struct i80321_softc *sc = (void *) self;
97 pcireg_t b0u, b0l, b1u, b1l;
98 paddr_t memstart;
99 psize_t memsize;
100
101 i80321_mainbus_found = 1;
102
103 /*
104 * Fill in the space tag for the i80321's own devices,
105 * and hand-craft the space handle for it (the device
106 * was mapped during early bootstrap).
107 */
108 i80321_bs_init(&i80321_bs_tag, sc);
109 sc->sc_st = &i80321_bs_tag;
110 sc->sc_sh = IQ80321_80321_VBASE;
111
112 /*
113 * Slice off a subregion for the Memory Controller -- we need it
114 * here in order read the memory size.
115 */
116 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE,
117 VERDE_MCU_SIZE, &sc->sc_mcu_sh))
118 panic("%s: unable to subregion MCU registers",
119 sc->sc_dev.dv_xname);
120
121 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE,
122 VERDE_ATU_SIZE, &sc->sc_atu_sh))
123 panic("%s: unable to subregion ATU registers",
124 sc->sc_dev.dv_xname);
125
126 /*
127 * We have mapped the PCI I/O windows in the early bootstrap phase.
128 */
129 sc->sc_iow_vaddr = IQ80321_IOW_VBASE;
130
131 /*
132 * Check the configuration of the ATU to see if another BIOS
133 * has configured us. If a PC BIOS didn't configure us, then:
134 * IQ80321: BAR0 00000000.0000000c BAR1 is 00000000.8000000c.
135 * IQ31244: BAR0 00000000.00000004 BAR1 is 00000000.0000000c.
136 * If a BIOS has configured us, at least one of those should be
137 * different. This is pretty fragile, but it's not clear what
138 * would work better.
139 */
140 b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0);
141 b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4);
142 b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8);
143 b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc);
144 b0l &= PCI_MAPREG_MEM_ADDR_MASK;
145 b0u &= PCI_MAPREG_MEM_ADDR_MASK;
146 b1l &= PCI_MAPREG_MEM_ADDR_MASK;
147 b1u &= PCI_MAPREG_MEM_ADDR_MASK;
148
149 if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0))
150 sc->sc_is_host = 0;
151 else
152 sc->sc_is_host = 1;
153
154 aprint_naive(": i80321 I/O Processor\n");
155 aprint_normal(": i80321 I/O Processor, acting as PCI %s\n",
156 sc->sc_is_host ? "host" : "slave");
157
158 i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize);
159
160 /*
161 * We set up the Inbound Windows as follows:
162 *
163 * 0 Access to i80321 PMMRs
164 *
165 * 1 Reserve space for private devices
166 *
167 * 2 RAM access
168 *
169 * 3 Unused.
170 *
171 * This chunk needs to be customized for each IOP321 application.
172 */
173 #if 0
174 sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE;
175 sc->sc_iwin[0].iwin_base_hi = 0;
176 sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE;
177 sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE;
178 #endif
179
180 if (sc->sc_is_host) {
181 /* Map PCI:Local 1:1. */
182 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
183 PCI_MAPREG_MEM_PREFETCHABLE_MASK |
184 PCI_MAPREG_MEM_TYPE_64BIT;
185 sc->sc_iwin[1].iwin_base_hi = 0;
186 } else {
187 sc->sc_iwin[1].iwin_base_lo = 0;
188 sc->sc_iwin[1].iwin_base_hi = 0;
189 }
190 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
191 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
192
193 if (sc->sc_is_host) {
194 sc->sc_iwin[2].iwin_base_lo = memstart |
195 PCI_MAPREG_MEM_PREFETCHABLE_MASK |
196 PCI_MAPREG_MEM_TYPE_64BIT;
197 sc->sc_iwin[2].iwin_base_hi = 0;
198 } else {
199 sc->sc_iwin[2].iwin_base_lo = 0;
200 sc->sc_iwin[2].iwin_base_hi = 0;
201 }
202 sc->sc_iwin[2].iwin_xlate = memstart;
203 sc->sc_iwin[2].iwin_size = memsize;
204
205 if (sc->sc_is_host) {
206 sc->sc_iwin[3].iwin_base_lo = 0 |
207 PCI_MAPREG_MEM_PREFETCHABLE_MASK |
208 PCI_MAPREG_MEM_TYPE_64BIT;
209 } else {
210 sc->sc_iwin[3].iwin_base_lo = 0;
211 }
212 sc->sc_iwin[3].iwin_base_hi = 0;
213 sc->sc_iwin[3].iwin_xlate = 0;
214 sc->sc_iwin[3].iwin_size = 0;
215
216 /*
217 * We set up the Outbound Windows as follows:
218 *
219 * 0 Access to private PCI space.
220 *
221 * 1 Unused.
222 */
223 sc->sc_owin[0].owin_xlate_lo =
224 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
225 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
226
227 /*
228 * Set the Secondary Outbound I/O window to map
229 * to PCI address 0 for all 64K of the I/O space.
230 */
231 sc->sc_ioout_xlate = 0;
232
233 /*
234 * Initialize the interrupt part of our PCI chipset tag.
235 */
236 iq80321_pci_init(&sc->sc_pci_chipset, sc);
237
238 i80321_attach(sc);
239 }
240