iq80321_start.S revision 1.3.8.2
1 1.3.8.2 nathanw /* $NetBSD: iq80321_start.S,v 1.3.8.2 2002/10/18 02:36:33 nathanw Exp $ */ 2 1.3.8.2 nathanw 3 1.3.8.2 nathanw /* 4 1.3.8.2 nathanw * Copyright (c) 2002 Wasabi Systems, Inc. 5 1.3.8.2 nathanw * All rights reserved. 6 1.3.8.2 nathanw * 7 1.3.8.2 nathanw * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 1.3.8.2 nathanw * 9 1.3.8.2 nathanw * Redistribution and use in source and binary forms, with or without 10 1.3.8.2 nathanw * modification, are permitted provided that the following conditions 11 1.3.8.2 nathanw * are met: 12 1.3.8.2 nathanw * 1. Redistributions of source code must retain the above copyright 13 1.3.8.2 nathanw * notice, this list of conditions and the following disclaimer. 14 1.3.8.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 15 1.3.8.2 nathanw * notice, this list of conditions and the following disclaimer in the 16 1.3.8.2 nathanw * documentation and/or other materials provided with the distribution. 17 1.3.8.2 nathanw * 3. All advertising materials mentioning features or use of this software 18 1.3.8.2 nathanw * must display the following acknowledgement: 19 1.3.8.2 nathanw * This product includes software developed for the NetBSD Project by 20 1.3.8.2 nathanw * Wasabi Systems, Inc. 21 1.3.8.2 nathanw * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 1.3.8.2 nathanw * or promote products derived from this software without specific prior 23 1.3.8.2 nathanw * written permission. 24 1.3.8.2 nathanw * 25 1.3.8.2 nathanw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 1.3.8.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.3.8.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.3.8.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 1.3.8.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.3.8.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.3.8.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.3.8.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.3.8.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.3.8.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.3.8.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 36 1.3.8.2 nathanw */ 37 1.3.8.2 nathanw 38 1.3.8.2 nathanw #include <machine/asm.h> 39 1.3.8.2 nathanw #include <arm/armreg.h> 40 1.3.8.2 nathanw #include <arm/arm32/pte.h> 41 1.3.8.2 nathanw 42 1.3.8.2 nathanw .section .start,"ax",%progbits 43 1.3.8.2 nathanw 44 1.3.8.2 nathanw .global _C_LABEL(iq80321_start) 45 1.3.8.2 nathanw _C_LABEL(iq80321_start): 46 1.3.8.2 nathanw /* 47 1.3.8.2 nathanw * We will go ahead and disable the MMU here so that we don't 48 1.3.8.2 nathanw * have to worry about flushing caches, etc. 49 1.3.8.2 nathanw * 50 1.3.8.2 nathanw * Note that we may not currently be running VA==PA, which means 51 1.3.8.2 nathanw * we'll need to leap to the next insn after disabing the MMU. 52 1.3.8.2 nathanw */ 53 1.3.8.2 nathanw adr r8, Lunmapped 54 1.3.8.2 nathanw bic r8, r8, #0xff000000 /* clear upper 8 bits */ 55 1.3.8.2 nathanw orr r8, r8, #0xa0000000 /* OR in physical base address */ 56 1.3.8.2 nathanw 57 1.3.8.2 nathanw mrc p15, 0, r2, c1, c0, 0 58 1.3.8.2 nathanw bic r2, r2, #CPU_CONTROL_MMU_ENABLE 59 1.3.8.2 nathanw mcr p15, 0, r2, c1, c0, 0 60 1.3.8.2 nathanw 61 1.3.8.2 nathanw nop 62 1.3.8.2 nathanw nop 63 1.3.8.2 nathanw nop 64 1.3.8.2 nathanw 65 1.3.8.2 nathanw mov pc, r8 /* Heave-ho! */ 66 1.3.8.2 nathanw 67 1.3.8.2 nathanw Lunmapped: 68 1.3.8.2 nathanw /* 69 1.3.8.2 nathanw * We want to construct a memory map that maps us 70 1.3.8.2 nathanw * VA==PA (SDRAM at 0xa0000000) and also double-maps 71 1.3.8.2 nathanw * that space at 0xc0000000 (where the kernel address 72 1.3.8.2 nathanw * space starts). We create these mappings uncached 73 1.3.8.2 nathanw * and unbuffered to be safe. 74 1.3.8.2 nathanw * 75 1.3.8.2 nathanw * We also want to map the various devices we want to 76 1.3.8.2 nathanw * talk to VA==PA during bootstrap. 77 1.3.8.2 nathanw * 78 1.3.8.2 nathanw * We just use section mappings for all of this to make it easy. 79 1.3.8.2 nathanw * 80 1.3.8.2 nathanw * We will put the L1 table to do all this at 0xa0004000, which 81 1.3.8.2 nathanw * is also where RedBoot puts it. 82 1.3.8.2 nathanw */ 83 1.3.8.2 nathanw 84 1.3.8.2 nathanw /* 85 1.3.8.2 nathanw * Step 1: Map the entire address space VA==PA. 86 1.3.8.2 nathanw */ 87 1.3.8.2 nathanw adr r0, Ltable 88 1.3.8.2 nathanw ldr r0, [r0] /* r0 = &l1table */ 89 1.3.8.2 nathanw 90 1.3.8.2 nathanw mov r3, #(L1_S_AP(AP_KRW)) 91 1.3.8.2 nathanw orr r3, r3, #(L1_TYPE_S) 92 1.3.8.2 nathanw mov r2, #0x100000 /* advance by 1MB */ 93 1.3.8.2 nathanw mov r1, #0x1000 /* 4096MB */ 94 1.3.8.2 nathanw 1: 95 1.3.8.2 nathanw str r3, [r0], #0x04 96 1.3.8.2 nathanw add r3, r3, r2 97 1.3.8.2 nathanw subs r1, r1, #1 98 1.3.8.2 nathanw bgt 1b 99 1.3.8.2 nathanw 100 1.3.8.2 nathanw /* 101 1.3.8.2 nathanw * Step 2: Map VA 0xc0000000->0xc3ffffff to PA 0xa0000000->0xa3ffffff. 102 1.3.8.2 nathanw */ 103 1.3.8.2 nathanw adr r0, Ltable /* r0 = &l1table */ 104 1.3.8.2 nathanw ldr r0, [r0] 105 1.3.8.2 nathanw 106 1.3.8.2 nathanw mov r3, #(L1_S_AP(AP_KRW)) 107 1.3.8.2 nathanw orr r3, r3, #(L1_TYPE_S) 108 1.3.8.2 nathanw orr r3, r3, #0xa0000000 109 1.3.8.2 nathanw add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */ 110 1.3.8.2 nathanw mov r1, #0x40 /* 64MB */ 111 1.3.8.2 nathanw 1: 112 1.3.8.2 nathanw str r3, [r0], #0x04 113 1.3.8.2 nathanw add r3, r3, r2 114 1.3.8.2 nathanw subs r1, r1, #1 115 1.3.8.2 nathanw bgt 1b 116 1.3.8.2 nathanw 117 1.3.8.2 nathanw /* OK! Page table is set up. Give it to the CPU. */ 118 1.3.8.2 nathanw adr r0, Ltable 119 1.3.8.2 nathanw ldr r0, [r0] 120 1.3.8.2 nathanw mcr p15, 0, r0, c2, c0, 0 121 1.3.8.2 nathanw 122 1.3.8.2 nathanw /* Flush the old TLBs, just in case. */ 123 1.3.8.2 nathanw mcr p15, 0, r0, c8, c7, 0 124 1.3.8.2 nathanw 125 1.3.8.2 nathanw /* Set the Domain Access register. Very important! */ 126 1.3.8.2 nathanw mov r0, #1 127 1.3.8.2 nathanw mcr p15, 0, r0, c3, c0, 0 128 1.3.8.2 nathanw 129 1.3.8.2 nathanw /* Get ready to jump to the "real" kernel entry point... */ 130 1.3.8.2 nathanw ldr r0, Lstart 131 1.3.8.2 nathanw 132 1.3.8.2 nathanw /* OK, let's enable the MMU. */ 133 1.3.8.2 nathanw mrc p15, 0, r2, c1, c0, 0 134 1.3.8.2 nathanw orr r2, r2, #CPU_CONTROL_MMU_ENABLE 135 1.3.8.2 nathanw mcr p15, 0, r2, c1, c0, 0 136 1.3.8.2 nathanw 137 1.3.8.2 nathanw nop 138 1.3.8.2 nathanw nop 139 1.3.8.2 nathanw nop 140 1.3.8.2 nathanw 141 1.3.8.2 nathanw /* CPWAIT sequence to make sure the MMU is on... */ 142 1.3.8.2 nathanw mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 143 1.3.8.2 nathanw mov r2, r2 /* force it to complete */ 144 1.3.8.2 nathanw mov pc, r0 /* leap to kernel entry point! */ 145 1.3.8.2 nathanw 146 1.3.8.2 nathanw Ltable: 147 1.3.8.2 nathanw .word 0xa0004000 148 1.3.8.2 nathanw 149 1.3.8.2 nathanw Lstart: 150 1.3.8.2 nathanw .word start 151
Indexes created Thu Oct 23 22:10:10 GMT 2025